EP1147552A1 - Structure de transistor a effet de champ aux jonctions source/drain abruptes - Google Patents

Structure de transistor a effet de champ aux jonctions source/drain abruptes

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Publication number
EP1147552A1
EP1147552A1 EP99972373A EP99972373A EP1147552A1 EP 1147552 A1 EP1147552 A1 EP 1147552A1 EP 99972373 A EP99972373 A EP 99972373A EP 99972373 A EP99972373 A EP 99972373A EP 1147552 A1 EP1147552 A1 EP 1147552A1
Authority
EP
European Patent Office
Prior art keywords
substrate
layer
source
forming
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99972373A
Other languages
German (de)
English (en)
Inventor
Anand S. Murthy
Robert S. Chau
Patrick Morrow
Chia-Hong Jan
Paul Packan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
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Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP1147552A1 publication Critical patent/EP1147552A1/fr
Withdrawn legal-status Critical Current

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/107—Substrate region of field-effect devices
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    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the invention relates to metal-oxide-semiconductor field effect transistors (MOSFETs) and more particularly to transistor structures having abrupt junctions, and methods of making same.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • MOSFETs can not simply be scaled down linearly. That is, as the width and length attributes of a MOSFET are reduced, other parts of the transistor, such as the gate dielectric and the junctions must also be scaled so as to achieve the desired electrical characteristics.
  • Undesirable electrical characteristics in MOSFETs due to improper scaling include coupling of the electric field into the channel region and increased subthreshold conduction. These effects are sometimes referred to in this field as short channel effects.
  • a number of methods have been developed to form ever more shallow source/drain junctions for MOSFETs in order to achieve proper scaling. Unfortunately, these very shallow junctions create source/drain extensions that have increased resistivity as compared with deeper source/drain junctions.
  • the source/drain extension resistivity was negligible compared to the on-resistance of the MOSFET itself.
  • MOSFET channel lengths decrease into the deep sub-micron region, the increased source/drain extension resistivity becomes a significant performance limitation.
  • What is needed is a field effect transistor structure having very short channel length and low source/drain extension resistivity, yet operable to produce high drive currents without suffering from the short channel effects that produce significant levels of off-state current. What is further needed is a method of manufacturing such a structure.
  • a MOSFET structure includes highly conductive source/drain extensions of a first conductivity type, and super abrupt junctions with a semiconductor body of a second conductivity type.
  • a process for forming a MOSFET includes removing portions of the substrate to form recesses that are adjacent and partially subjacent a FET gate structure, and back filling the recesses with an epitaxial process.
  • Fig. 1 is a schematic cross-section of a wafer in process showing a substrate with a gate dielectric formed thereon, and a patterned gate electrode over the gate dielectric and a spacer layer formed over the surface of the wafer.
  • Fig. 2 is a schematic cross-section showing the structure of Fig. 1, after an anisotropic etch of the spacer layer forms thin sidewall spacers, and the gate dielectric not covered by the gate electrode or sidewall spacers is removed.
  • Fig. 3 is a schematic cross-section showing the structure of Fig. 2, after an isotropic etch removes portions of the substrate, to form recesses therein, and further showing a portion of the gate electrode etched away.
  • Fig. 4 is a schematic cross-section showing the structure of Fig. 3, after the recesses have been back-filled and the gate electrode thickness built up.
  • Fig. 5 is a schematic cross-section showing the structure of Fig. 4, after a salicidation operation.
  • Fig. 6 is a schematic cross-section showing the structure of Fig. 3, after an alternative process flow in which the back-filling of the recesses includes forming a layer of a first conductivity type followed by formation of a layer of a second conductivity type.
  • Fig. 7 is a flow diagram illustrating the various operations in a manufacturing process in accordance with the present invention.
  • An illustrative embodiment of the present invention provides a FET with highly conductive source/drain extensions and abrupt junctions.
  • Methods of forming the FET structure of the present invention include isotropically etching the substrate adjacent to, and partially underneath, the gate dielectric layer of a FET, and selectively depositing bilayers of in-situ doped material of a first conductivity type, and a second conductivity type.
  • FETs embodying the present invention include back-filled source and drain terminals.
  • the doping concentration of the source/drain terminals can be controlled by controlling the gas mixture, temperature, and pressure, in a reaction chamber.
  • the embodiments of the present invention include microelectronic devices having very abrupt junctions.
  • particular embodiments of the present invention may eliminate high-energy ion implantation of the source/drain junctions. Formation of the source/drain junctions in this way also provides increased margin for the process thermal budget, since a high temperature operation is not required to activate the dopants, or to thermally in-diffuse the dopants into the tip portion of the source/drain terminals.
  • chip integrated circuit
  • monolithic device semiconductor device, and microelectronic device
  • present invention is applicable to all the above as they are generally understood in the field.
  • metal line trace, wire, conductor, signal path and signaling medium are all related. The related terms listed above, are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnect or simply metal.
  • Metal lines generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling or interconnecting, electrical circuitry. Conductors other than metal are available in microelectronic devices.
  • doped polysilicon doped single-crystal silicon (often referred to simply as diffusion, regardless of whether such doping is achieved by thermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo), cobalt (Co), nickel (Ni) and tungsten (W) and refractory metal suicides are examples of other conductors.
  • contact and via both refer to structures for electrical connection of conductors from different interconnect levels. These terms are sometimes used in the art to describe both an opening in an insulator in which the structure will be completed, and the completed structure itself. For purposes of this disclosure contact and via refer to the completed structure.
  • Epitaxial layer refers to a layer of single crystal semiconductor material.
  • gate is context sensitive and can be used in two ways when describing integrated circuits.
  • gate refers to the insulated gate terminal of a three terminal FET when used in the context of transistor circuit configuration, and refers to a circuit for realizing an arbitrary logical function when used in the context of a logic gate.
  • a FET can be viewed as a four terminal device when the semiconductor body is considered.
  • Polycrystalline silicon is a nonporous form of silicon made up of randomly oriented crystallites or domains. Polycrystalline silicon is often formed by chemical vapor deposition from a silicon source gas or other methods and has a structure that contains large-angle grain boundaries, twin boundaries, or both. Polycrystalline silicon is often referred to in this field as polysilicon, or sometimes more simply as poly.
  • Source/drain terminals refer to the terminals of a FET, between which conduction occurs under the influence of an electric field, subsequent to the inversion of the semiconductor surface under the influence of an electric field resulting from a voltage applied to the gate terminal.
  • Source/drain terminals are typically formed in a semiconductor substrate and have a conductivity type (i.e., p-type or n-type) that is the opposite of the conductivity type of the substrate.
  • source/drain terminals are referred to as junctions.
  • the source and drain terminals are fabricated such that they are geometrically symmetrical.
  • Source/drain terminals may include extensions, sometimes referred to as tips, which are shallower than other portions of the source/drain terminals.
  • the tips typically extend toward the channel region of a FET, from the main portion of the source/drain terminal.
  • source/drain terminals With geometrically symmetrical source and drain terminals it is common to simply refer to these terminals as source/drain terminals, and this nomenclature is used herein.
  • Designers often designate a particular source/drain terminal to be a "source” or a “drain” on the basis of the voltage to be applied to that terminal when the FET is operated in a circuit.
  • Substrate refers to the physical object that is the basic workpiece that is transformed by various process operations into the desired microelectronic configuration.
  • a substrate may also be referred to as a wafer.
  • Wafers may be made of semiconducting, non- semiconducting, or combinations of semiconducting and non-semiconducting materials.
  • vertical as used herein, means substantially perpendicular to the surface of a substrate.
  • a wafer is processed in known ways to form a thin film layer over a patterned gate electrode and over a gate dielectric layer that has been disposed on the top surface of the wafer. More particularly, as shown in Fig. 1 , a substrate 102 has a gate dielectric layer 104 disposed over the surface thereof, and a patterned gate electrode 106 is formed over gate dielectric layer 104.
  • substrate 102 is a silicon wafer
  • gate dielectric layer 104 is a silicon dioxide layer
  • gate electrode 106 is formed from polysilicon.
  • gate dielectric layer 104 is typically a thin layer of oxidized silicon, the thickness and chemical make-up of the gate insulator layer may be varied within the scope of the invention.
  • field oxide isolation architectures include shallow trench isolation regions in a surface of a substrate, and the older local oxidation of silicon, which formed non-planarized oxide isolation regions.
  • a thin film layer 108 is deposited over the surface of gate electrode 106 and the portions of gate dielectric layer 104 not already covered by gate electrode 106. Thin film layer 108 may also be referred to as a spacer layer because spacers adjacent to the side walls of gate electrode 106 are formed from layer 108 in subsequent processing operations.
  • spacer layer 108 it is preferable for spacer layer 108 to have etch characteristics that are different from the etch characteristics of substrate 102 and gate electrode 106.
  • the material for spacer layer 108 could be any dielectric material including, but not limited to, nitride, oxynitride, and oxide.
  • a thin layer of silicon nitride is deposited over the surface of the substrate to form spacer layer 108.
  • the silicon nitride layer is approximately 20 nm thick, and is formed in a vertical diffusion furnace.
  • the thickness of the nitride layer is not a limitation of the invention and it may be made any practical thickness, for example, in a range of from 2 nm to 50 nm thick.
  • This nitride layer will be used to provide the needed selectivity during a subsequent epitaxial backfill operation.
  • the spacer layer may be formed of another material such as, for example, silicon dioxide. Silicon dioxide has a dielectric constant that is lower than the dielectric constant of silicon nitride, and this is advantageous in terms of lowering parasitic capacitance between the gate electrode and other nearby circuit nodes.
  • spacer layer 108 is etched anisotropically using, for example, conventional dry etch chemistries for silicon nitride. Subsequent to this etch operation, no significant amount of residual silicon nitride remains in the source/drain regions. In the illustrative embodiment, this anisotropic etch operation leaves a nitride layer approximately 150nm thick (when measured along a vertical axis) along the sidewalls of polysilicon gate electrode 106. Typically, the vertical height (i.e., thickness) of this layer is approximately equal to the thickness of gate electrode 106.
  • These post-etch nitride structures are referred to as spacers. As can be seen in Figs. 1-2, that portion of silicon nitride spacer layer 108 that is superjacent to the top surface of gate electrode 106 is removed by the spacer layer etch operation.
  • a plurality of recesses in substrate 102 are produced by using an isotropic dry etch process in a parallel plate RF plasma etching system.
  • a mixture of sulfur hexafluoride (SF 6 ) and helium (He), at process conditions that favor isotropy are employed. Such conditions include high pressure and low RF power density.
  • a process pressure of approximately 900 mT, a gap of 1.1 cm, an RF power of 100 W, a He flow of 150 seem, and a SF 6 flow of 100 seem is used.
  • RF power may be varied in a range, for example, of 50 W to 200 W, and the process pressure may be varied but should be greater than approximately 500 mT.
  • This etch process is highly selective and is characterized by a silicon etch rate that is much greater than the etch rate of the silicon dioxide that forms gate dielectric layer 104. Similarly, the etch rate of silicon substrate 102 is much greater than the etch rate of the silicon nitride that forms sidewall spacers 108. The electrical characteristics of gate dielectric layer 104 are not adversely affected by the etch process that forms the recesses in substrate 102.
  • the recesses include a portion that underlies gate dielectric layer 104.
  • substrate 102 is etched isotropically such that the lateral etch creates a recessed area that reaches underneath not only the spacer but also partially underneath a region defined by overlying gate electrode 106.
  • NFETs n-channel FETs
  • PFETs p-channel FETs
  • PFETs and NFETs are structurally similar, however the relative placement of p-type and n-type dopants is different. That is, a PFET includes p-type source/drain terminals in an n-type body, and an NFET includes n-type source/drain terminals in a p-type body.
  • an epitaxial film of boron doped Si 110 is formed using SiH 2 Cl 2 based chemistry such that the deposition is highly selective to nitride spacer 108, i.e., the film of boron doped Si 110 does not form on, nor adhere to, silicon nitride spacer 108.
  • the recesses are substantially filled by this deposition operation.
  • the recess may be completely filled by this operation. No ex-situ cleaning operations are performed. This is because an external wet clean would tend to damage thin gate dielectric layer 104.
  • boron doped SiGe may be used in place of boron doped Si to form the film that fills the recess.
  • epitaxial film 110 is deposited such that its top surface is above the plane of the original surface of substrate 102. This can be seen in Fig. 4 by comparing the relative positions of gate dielectric layer 104, which was formed on the original surface of substrate 102, with the top surface of Si layer 110. As is further shown in Fig. 4, an epitaxial film of boron doped Si 110 is also formed on top of gate electrode 106. In this way the thickness of polysilicon gate electrode 106 is increased from its post-etch dimensions.
  • boron doped Si film 110 is formed by a selective deposition.
  • a selective deposition of boron doped silicon creates Si film 110 on the exposed surfaces of silicon substrate 102, and polysilicon gate electrode 106.
  • a silicon film can be selectively deposited by heating the wafer to a temperature of approximately 600 °C to 900 °C, providing a deposition gas comprising dichlorosilane (SiH 2 Cl 2 ), and hydrogen (H 2 ).
  • an n-type silicon can be selectively deposited at a temperature of approximately 750°C, with approximately 10 slm H 2 , approximately 30 seem HC1, approximately 100 seem SiH 2 Cl 2 , and approximately 180 seem PH 3 , at approximately atmospheric pressure. Such process conditions can deposit a layer approximately 50 nm thick in approximately 6 minutes.
  • a p-type silicon can be selectively deposited at a temperature of approximately 800°C, with approximately 20 slm H 2 , approximately 70 seem HC1, approximately 120 seem SiH,Cl 2 , and approximately 75 seem B 2 H f ⁇ . Such process conditions can deposit a layer approximately 50 nm thick in approximately 155 seconds.
  • a silicon germanium alloy can be selectively deposited by heating the wafer to a temperature between approximately 700 °C and 750 °C, providing a deposition gas mix comprising dichlorosilane at a rate of between approximately 10 to 100 seem, 1 % hydrogen diluted germane (GeH 4 ) at a rate of between approximately 10 to 200 seem, and hydrogen at a rate of approximately 20 slm into a CVD chamber maintained at a pressure between approximately 50 to 760 torr.
  • a dopant gas such as diborane, phosphine, or arsine, can be included in the process gas mix if a doped silicon or silicon alloy film is desired.
  • a highly doped (>5xl0 20 atoms/cm 3 ) n-type silicon germanium epitaxial film can be selectively deposited onto silicon surfaces by thermal chemical vapor deposition utilizing a deposition gas mix comprising approximately 10 to 200 seem GeH 4 , approximately 10 to 100 seem dichlorosilane, 10 to 40 slm H 2 , 1 to 200 seem PH 3 , and 15 seem HCl, while maintaining the substrate at a temperature between 700°C and 750 °C and maintaining a deposition pressure of approximately 165 torr during film deposition.
  • a deposition gas mix comprising approximately 10 to 200 seem GeH 4 , approximately 10 to 100 seem dichlorosilane, 10 to 40 slm H 2 , 1 to 200 seem PH 3 , and 15 seem HCl, while maintaining the substrate at a temperature between 700°C and 750 °C and maintaining a deposition pressure of approximately 165 torr during film deposition.
  • Such a process will form a substantially uniformly doped
  • a p-type silicon germanium alloy can be formed by decomposition of approximately 20 seem of dichlorosilane, approximately 80 seem germane, approximately 20 slm H 2 and a p-type dopant source, such as approximately 1 -200 seem of B 2 H 6 at a temperature of approximately 740°C.
  • approximately 10 seem of HCl can be added to the gas mix. Such process conditions can deposit a layer approximately 50 nm thick in approximately 75 seconds.
  • the deposition operation is such that selectivity to oxide in field oxide regions, or shallow trench isolation regions is also achieved.
  • Fig. 5 shows the FET structure of Fig. 4 after further processing operations are performed.
  • Conventional processing may be used to form additional sidewall spacers 112 that are disposed along opposing sidewall spacers 108.
  • conventional processing may be used to form salicided regions 114 over the top surfaces of doped Si regions 110, that is, the source/drain extension regions and polysilicon gate electrode 106. It should be noted that the structure of the present invention is advantageous in the formation of salicided source/drain extensions.
  • a metal such as nickel, which diffuses in silicon relatively easily, is used to form a nickel salicide layer
  • lateral diffusion of nickel atoms is stopped by nitride side wall spacers 108 and the nickel atoms therefore do not penetrate into the channel region where they would otherwise adversely affect the electrical characteristics of the MOSFET.
  • the thickness of Si 110 and the depth of salicide layer 114 can be varied with the scope of the invention and still benefit from the structure's metal atom diffusion barrier characteristics.
  • a layer of phosphorous doped Si 111 is epitaxially formed, prior to an in-situ epitaxial formation of boron doped Si 110.
  • n-type dopants may be used in place of phosphorous.
  • Arsenic is an example of an alternative n-type dopant.
  • Desirable electrical characteristics may be obtained in this way by having a relatively lightly doped substrate 102 of a first conductivity type, highly doped source/drain terminals 110 of a second conductivity type, and a highly doped region 111 of the first conductivity type disposed between source/drain terminals 110 and lightly doped substrate 102. Due to the nature of the selective deposition process (described above), highly doped regions 110, 111, are not only highly doped in the source/drain extension regions, but also in the tip-to-gate overlap region. The term tip, is generally used to refer to that portion of the source/drain junction that is subjacent to the gate and adjacent to the channel portion of a FET.
  • an operation is performed wherein a spacer layer is formed over a patterned gate electrode.
  • the gate electrode is comprised of polysilicon that has previously been deposited over a gate dielectric layer.
  • the gate dielectric is typically oxidized silicon.
  • the spacer layer is typically silicon nitride.
  • the gate dielectric layer may consist of an oxide layer and a nitride layer in combination.
  • the gate electrode may be formed from a metal rather than polysilicon.
  • the spacer layer After the spacer layer has been formed, it is subjected to an anisotropic etch (block 204) in which sidewall spacers are formed. During the anisotropic etch, portions of the spacer layer that are superjacent the top surface the gate electrode and the top surface of the wafer are removed. The remaining portion of the spacer layer disposed along the opposing vertical sidewalls of the gate electrode.
  • Recesses are formed in the wafer (block 206) at locations where the source/drain terminals of the FET will be located.
  • the recesses are formed by the isotropic etch of the wafer. As is understood in this field, an isotropic etch operation will remove material from the wafer surface both vertically and laterally.
  • the etch chemistry and conditions are preferably chosen such that the etch is highly selective and preferentially etches the wafer rather than the side wall spacers or the gate dielectric layer.
  • the gate dielectric is an oxide of silicon
  • the gate electrode is polysilicon
  • the side wall spacers are silicon nitride
  • a plasma etch with sulfur hexafluoride (SF 6 ) and helium (He) is used.
  • the wafer is typically placed in an epitaxial reactor and a first layer of doped crystalline material is formed (block 208).
  • the crystalline material may be, for example, p-type silicon, p-type silicon germanium, n-type silicon, or n-type silicon germanium.
  • the conductivity type of the first layer matches the conductivity type of that portion of the wafer where the FET is being fabricated.
  • NFETs n-channel FETs
  • PFETs p-channel FETs
  • a second layer of doped crystalline material is formed (block 210).
  • the second layer is typically formed without exposing the first layer to the atmosphere. That is, the second layer and first layer are formed in a continuous in-situ operation, in the same reaction chamber simply by changing the gas mixture, temperature, and pressure in the epitaxial reactor.
  • the crystalline material may be, for example, p-type silicon, p-type silicon germanium, n-type silicon, or n-type silicon germanium.
  • the conductivity type of the second layer is chosen to be opposite that of the first layer. In this way, extremely abrupt junctions can be obtained.
  • a gate structure of a PFET is formed in a region of a n-type portion of a silicon wafer, and after the source/drain recesses are formed, a first layer of n-doped (e.g., phosphorous) silicon germanium is formed in the recesses, and then a second layer of p-doped (e.g., boron) silicon germanium is formed over the first layer.
  • n-doped e.g., phosphorous
  • p-doped silicon germanium e.g., boron
  • first and second layer are substantially free of counterdopants, whereas the n-type region of the wafer typically contains both n-type and p-type dopants.
  • a gate structure may be a gate electrode or a gate electrode and adjacent side wall spacers.
  • a salicidation operation is typically performed to further reduce the sheet resistivity of the source/drain terminals and gate electrode.
  • Embodiments of the present invention provide a field effect transistor structure having very short channel length and low source/drain extension resistivity, yet operable to produce high drive currents without suffering from the short channel effects that produce significant levels of off-state current. Further embodiments of the present invention provide methods of manufacturing such a structure.
  • An advantage of particular embodiments of the present invention is that source/drain terminals can be formed without annealing. By eliminating the high temperature step conventionally required to activate the dopants, thermal diffusion is avoided and the very abrupt junctions are maintained.
  • An advantage of particular embodiments of the present invention is that the raised junctions formed by back filling, in conjunction with the side wall spacers disposed along opposing vertical walls of the gate electrode, substantially prevent lateral diffusion of metal atoms in the transistor channel region during the salicidation operation.
  • An advantage of particular embodiments of the present invention is placement of active dopants directly in the tip portion of the source/drain terminals.
  • An advantage of particular embodiments of the present invention is that a very precise doping profile is achieved.
  • An advantage of particular embodiments of the present invention is that very shallow, highly doped, source/drain terminals can be formed without ion implantation of the tip portion. In some cases, even a deep source/drain implant, typically used to form portions of source/drain terminals that lie further from the channel region, may be eliminated. It will be understood by those skilled in the art having the benefit of this disclosure that many design choices are possible within the scope of the present invention. For example, structural parameters, including but not limited to, gate insulator thickness, gate insulator materials, gate electrode thickness, sidewall spacer material, inter-layer dielectric material, isolation trench depth, and S/D and well doping concentrations may all be varied from that shown or described in connection with the illustrative embodiments. Similarly, the operation of forming recesses and back filling with doped crystalline material may be repeated to tailor the shape and doping profile of the source/drain terminals.

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Abstract

Les structures électroniques de cette invention comprennent un transistor à effet de champ comportant des extensions source/drain extrêmement conductrices. Ces extensions source/drain extrêmement conductrices sont obtenues en formant un évidement passivé qui est recomblé par un dépôt épitaxial de matériau dopé de façon à former les jonctions source/drain. Les creux comportent une région s'étendant latéralement, sous-jacente à une partie de la structure de grille. Cette extension latérale peut être sous-jacente à un espaceur (108) de paroi latérale adjacent aux parois latérales verticales de l'électrode (106) de grille ou peut s'étendre également dans la partie canal d'un transistor à effet de champ de sorte que le creux latéral soit sous-jacent à la partie de l'électrode de grille de la structure de grille. Selon une réalisation, on recomble l'évidement en déposant in situ, de manière épitaxiale, une double couche de matériau à dopage opposé. On crée ainsi une jonction très abrupte qui forme une extension source/drain à résistance relativement faible et confère de bonnes caractéristiques de fuite par courant infraseuil à l'état bloqué. Selon d'autres réalisations, on peut effectuer le comblement d'un évidement par un seul type de conductivité.
EP99972373A 1998-11-12 1999-11-05 Structure de transistor a effet de champ aux jonctions source/drain abruptes Withdrawn EP1147552A1 (fr)

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US19107698A 1998-11-12 1998-11-12
US191076 1998-11-12
PCT/US1999/026224 WO2000030169A1 (fr) 1998-11-12 1999-11-05 Structure de transistor a effet de champ aux jonctions source/drain abruptes

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AU1470200A (en) 2000-06-05
JP2002530864A (ja) 2002-09-17

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