Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
  • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the invention relates to an integrated circuit with electrical connection points that can be separated by the action of energy, so-called fuse links.
• An integrated circuit with fuse links is known for example from JP-A 01-080 037. This shows two rows arranged parallel to each other, each with two fuse links. Each fuse link is an element of an electrical conductor track, the conductor tracks of each row being designed parallel to one another and in a straight line. Depending on the type, fuse links can be separated, for example, by means of increased currents flowing through the respective conductor track or by means of a laser beam. Depending on whether a fuse link is broken or not, two different states can be distinguished. In this way it is possible to configure an integrated circuit via the fuse links.
• fuse links are then arranged in a row, the interconnects connected to them being aligned parallel to one another and running in a straight line.
• fuse links are separated, in particular by means of a laser beam, the ones arranged above the fuse link are destroyed
• the invention has for its object to provide an integrated circuit with fuse links, the space requirement is reduced.
• the integrated circuit according to the invention has electrical connection points which can be separated by the action of energy and which, viewed both in a first direction and in a second direction perpendicular thereto, are arranged offset to one another.
• the connection points are each part of an electrical conductor track, which are arranged parallel to one another and run essentially in the first direction.
• the conductor tracks have an offset facing away from the connection point of the respectively adjacent conductor track, so that two adjacent ones of the conductor tracks have a smaller distance from each other where they have no connection point than where one of the adjacent conductor tracks has a connection point.
• the invention has the advantage that by the provided offsets of the conductor tracks at the level of the respectively adjacent connection point, the respectively predetermined minimum distance to avoid short circuits between the conductor tracks as a result of the separation of the connection points can be maintained without problems.
• the minimum distance caused by the laser system is also easier to hold.
• there is a relatively high packing density of the connection points since two of the conductor tracks in the areas in which none of them have a connection point are at a significantly smaller distance from one another than in the areas in which one of them has a connection point.
• the conductor tracks have the minimum distance necessary to avoid a short circuit where there is actually a risk of a short circuit, while in their areas which are not critical with regard to a short circuit, this minimum distance can be clearly undercut and only with respect to the usual on the integrated circuit the design rules that apply to the interconnect spacing must be observed.
• a larger beam diameter can be used for the laser process. Slight mispositioning of the laser system is less critical.
• the integrated circuit has at least one middle and two outer electrical connection points that can be separated by the action of energy, the middle connection point being arranged between the two outer connection points, both in the first direction and in the second direction perpendicular thereto .
• the connection points are each part of a central or an outer electrical conductor track, which are arranged parallel to one another and run essentially in the first direction.
• Each outer conductor track has an offset facing away from it at the middle connection point and an offset facing it at the level of the outer connection point of the respective other outer conductor track.
• the middle conductor track has an offset facing away from each of them at the level of the two outer connection points.
• FIGS. 1 to 3 show different exemplary embodiments of the invention in a top view
• FIG. 4 shows a cross-sectional illustration of one of the exemplary embodiments in FIGS. 1 to 3.
• FIG. 1 shows three rows of electrical connection points (fuse links) which can be separated by the action of energy.
• the connection points of this exemplary embodiment can be separated by means of a laser. In other embodiments of the invention, the separation can also be done in a different way, for example electrically, by supplying a sufficiently high current.
• the three fuse links in the middle of FIG. 1 are discussed below. It is a middle fuse link 1 and two outer fuse links 2, 3, which are each offset in the illustration in FIG. 1 in the x direction and in the y direction.
• the middle fuse link 1 is part of a middle conductor track 10 and the outer fuse links 2, 3 are parts of an outer conductor track 20, 30.
• the conductor tracks 10, 20, 30 are arranged parallel to one another and run essentially in Y. -Direction.
• the conductor tracks do not run in a straight line, but have offsets that are separated from them in the areas in which the adjacent conductor track has a fuse link. are facing and in the areas in which the adjacent conductor track has no fuse link, these are facing. In this way, there is a significantly greater distance between adjacent conductor tracks in the areas in which a fuse link is present than where two adjacent conductor tracks have no fuse link. At the latter points, the minimum distance between the conductor tracks can be based on the design rule that is generally valid for the respective integrated circuit. In the areas of the fuse links, the mutual spacing of the conductor tracks depends on the applicable minimum distance which must be maintained in order to avoid short circuits due to the breaking of a fuse link and the associated distribution of its material on the surface of the integrated circuit avoid.
• the offsets of the conductor tracks have a certain minimum length in the Y direction, so that the necessary minimum distance is ensured in a larger area around the respective fuse link.
• FIG. 1 shows that the integrated circuit of the first exemplary embodiment has a plurality of the arrangements just described, each with three fuse links 1, 2, 3 and corresponding conductor tracks 10, 20, 30, which are arranged adjacent to one another in the X direction , so that there is a regularly repeating structure. It is clear that a high packing density of the fuse links is achieved in this way.
• the conductor tracks 10, 20, 30 in FIG. 1 only have conductor track sections which represent straight lines, so that the offsets are bent at right angles. In other embodiments of the invention, however, it is also possible to assemble the conductor tracks from rounded conductor track sections.
• FIG. 2 shows a second exemplary embodiment of the invention, in which the minimum arrangement already described with reference to FIG. 1 in each case three fuse links 1, 2, 3 several times is included.
• the fuse links are not arranged in three but in four rows. This means that between each two minimum configurations of the three connecting parts 1, 2, 3 which are adjacent to one another in the X direction, there is yet another conductor track 40 with a fourth connecting point 4.
• the three fuse links 1, 2, 3 of the minimum configuration are arranged adjacent to one another in the X direction, but not immediately, but separated from one another by the further conductor track 40. This again results in an extremely dense packing density of the fuse links 1, 2, 3, 4.
• FIG. 3 shows a further exemplary embodiment of the invention with five rows of fuse links 1, 2, 3, 4, 5.
• the minimal configurations of the three fuse links 1, 2, 3, which in turn are adjacent in the X direction, are two in this case further conductor tracks 40, 50, each having a further fuse link 4, 5, separated from one another.
• FIG. 4 shows a section through the integrated circuit IC of any of the exemplary embodiments in FIGS. 1 to 3. Only a section of this cross section is shown, which shows the middle conductor track 10 and the two outer conductor tracks 20, 30 of the minimum configuration.
• FIG. 4 shows two metallization levels M1, M2 of the integrated circuit IC which are separated from one another by a dielectric insulation layer I.
• the cross section shown in FIGS. 1 to 3 runs in the X direction through the middle fuse link 1. It can be seen that the middle conductor track 10 runs in the region of the middle fuse link 1 in the first metallization level M1, while the two outer ones Conductor tracks 20, 30 run in the area of the middle fuse link 1 in the second metallization level M2. At the level of the outer fuse links 2, 3 (not shown in FIG. 4), the corresponding outer conductor track 20, 30 runs in the first metallization level M1 and the two other Its conductor tracks run in the second metallization level M2.
• all segments of the conductor tracks 10, 20, 30 run in a common metallization level.

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)

Applications Claiming Priority (3)

Publications (1)

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Family Applications (1)

Country Status (7)

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Family Cites Families (12)

• 1998
  • 1998-08-04 DE DE19835263A patent/DE19835263C2/de not_active Expired - Fee Related
• 1999
  • 1999-07-29 TW TW088112874A patent/TW445622B/zh not_active IP Right Cessation
  • 1999-08-02 KR KR10-2001-7001452A patent/KR100380784B1/ko not_active IP Right Cessation
  • 1999-08-02 WO PCT/DE1999/002398 patent/WO2000008687A1/de not_active Application Discontinuation
  • 1999-08-02 EP EP99950500A patent/EP1104583A1/de not_active Withdrawn
  • 1999-08-02 JP JP2000564235A patent/JP3682231B2/ja not_active Expired - Fee Related
• 2001
  • 2001-02-05 US US09/776,954 patent/US6302729B2/en not_active Expired - Lifetime

Non-Patent Citations (1)

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