EP1081748A2 - Ätzstops und Ausrichtungsmarkierungen für gebondete Scheiben - Google Patents
Ätzstops und Ausrichtungsmarkierungen für gebondete Scheiben Download PDFInfo
- Publication number
- EP1081748A2 EP1081748A2 EP00307164A EP00307164A EP1081748A2 EP 1081748 A2 EP1081748 A2 EP 1081748A2 EP 00307164 A EP00307164 A EP 00307164A EP 00307164 A EP00307164 A EP 00307164A EP 1081748 A2 EP1081748 A2 EP 1081748A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- wafer
- major surface
- trenches
- recited
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 235000012431 wafers Nutrition 0.000 title claims description 131
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 238000005520 cutting process Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates generally to bonded wafers, and more particularly to a method of manufacturing a bonded wafer, the bonded wafer made by the method, and integrated circuits manufactured from chips on such wafers.
- Bonded wafers are fabricated with a single crystal substrate wafer bonded to a single crystal silicon device wafer.
- the substrate wafer provides structural strength to the bonded wafer and is relatively thicker, while the device wafer in which devices are subsequently formed is relatively thinner.
- a surface of each of the substrate wafer and the device wafer are polished to be planar. The polished surfaces are placed in contact with each other and the wafers are subjected to a high temperature heat treatment which bonds the wafers together.
- Bonded wafers in which buried layers are required for device fabrication are made by bonding a device wafer to a substrate wafer as described above. Subsequent to being bonded, the device wafer is thinned by removing material from a major exposed surface until the device wafer is thinned to a predetermined thickness, such as 1 to 2 . Buried or diffused layers, of N-type or P-type, or both, are implanted into the device wafer portion of the bonded wafer. An epitaxial layer of N or P type material is grown to the desired thickness over the device wafer portion of the bonded wafer.
- any known technique including but not limited to plasma etching, ion etching, grinding or polishing, may be used to ablate a surface of the device wafer.
- plasma etching, ion etching, grinding or polishing may be used to ablate a surface of the device wafer.
- What is needed is a technique to precisely control the thickness of the device wafer portion of the bonded wafer when the device wafer is thinned. It is also desirable to have an accurate alignment feature to align subsequent device diffusions with buried layers in the device wafer.
- a method of making a bonded wafer by diffusing regions of a first wafer, first major surface. Trenches are etched a predetermined distance into the first wafer from the first major surface toward a second major surface. The first major surface and trenches are coated with oxide. The first major surface of the first wafer is bonded to a second wafer to form a bonded wafer. The second major surface of the bonded wafer which is also the second major surface of the first wafer is ablated until oxide in the trenches is detected. The bonded wafer is cut into chips which are packaged as integrated circuits.
- a cross-section of a device wafer 20 is shown prior to wafer bonding in Figure 1.
- Device wafer is a cylinder having two major circular surfaces.
- Device wafer 20 is typically polished on one major surface to form a planar first major surface 22.
- diffused regions 24 are created in selected regions of device wafer 20 such as by implanting an impurity and diffusing the impurity. Diffused regions 24 may be positive diffused regions 26 or negative diffused regions 28.
- Trenches 30 are etched in device wafer 20 from first major surface 22 and extend toward second major surface 32. Second major surface 32 is substantially parallel to first major surface 22.
- Trenches 30 are etched in device wafer 20 from first major surface 22 to a predetermined depth, such as d, which is less than the thickness, t, of device wafer 20. Trenches 30 are etched using a well-known, well-controlled process, such as but not limited to active ion etching or plasma etching.
- an oxide layer 34 is deposited on or grown on first major surface 22, forming an alternative first major surface 36.
- Trenches 30 will be partially or completely filled with oxide by this process step.
- Figure 3 illustrates partial filling of a typical trench 30 in which the inner surface of sidewalls 42 and 44 as well as end 46 are coated with oxide but the trench is not completely filled.
- an additional layer such as a polysilicon layer may be deposited over the layer of oxide.
- Polysilicon layer 48 fills the remaining cavity in trench 30. Polysilicon layer 48 may be polished and oxidized to form a planar, bondable surface.
- an alternative first major surface is produced and is substantially planar.
- the alternative first major surface will be referenced by reference numeral 36, although it is understood that it may be either surface 36 or surface 48.
- a cross section of trenches 30 have parallel sidewalls 42 and 44 and a flat end 46.
- the cross-section of an ideal trench forms a rectangular shape.
- sidewalls 42 and 44 tend to taper toward each other slightly from first major surface 22 extending toward second major surface 32 and end 46 of trench 30.
- End 46 may be slightly rounded with a rounded intersection between each of sidewalls 42 and 44 and end 46, as shown in Figure 3.
- Substrate wafer 50 having substantially planar major surface 52 is placed in contact with alternative first major surface 36, or alternative first major surface 48 when present.
- Device wafer 20 and substrate wafer 50 are subjected to a high-temperature heat treatment, as is known in the art, to bond the wafers together forming bonded wafer 54 illustrated in Figure 4.
- the diffused regions 24 and trenches 30 are internal to bonded wafer 54. Trenches 30 extend toward one of the outer major surfaces of bonded wafer 54, which is also the second major surface 32 of device wafer 20.
- second major surface 32 is ablated by a known process. Any known ablating process may be used, including but not limited to, chemical mechanical polishing, polishing, grinding or etching.
- the major surface 32 at any stage of the ablating process will be referred to as major surface 60.
- the ablating process thins bonded wafer 54, and more specifically device wafer 20 to a predetermined thickness. Device wafer 20 is thinned by ablating major surface 60 until the
- Ends 46 act as stops to the ablating process.
- the ablating process is stopped when the end 46 of trenches 30 begin to be ablated. This may be detected such as by observing a characteristic such as but not limited to opacity of a grinding solution, or optically in accordance with U.S. Patent, 4,313,732, the disclosure of which is hereby incorporated by reference.
- the remaining thickness of device wafer 20 between ablated major surface 60 and first major surface 22 is also known.
- the remaining predetermined thickness by device wafer 20 is selected so that subsequent implants from major surface 60 provides proper depth placement of implanted regions relative to diffused regions 24.
- the device wafer is thinned to a predetermined thickness, such as 1 to 2 micrometers, which is critical for device characteristics and performance.
- trenches 30 are etched in device wafer 20 to a predetermined depth as shown in Figure 5.
- trenches 30 may be etched to various predetermined depths into device wafer 20. More than one etching step may be required.
- One or more trenches or sets of trenches may be etched to various depths such that when the ablating process is reducing the thickness of device wafer 20 by ablating major surface 60, the process may be stopped and evaluated for the remaining distance to be ablated based on the predetermined depth of the various trenches 30.
- One or more trenches may be used to indicate the desired thickness has been reached, or has been passed.
- ends 46 of trenches 64 denote the desired thicknesses of device wafer 20, such that the ablating process should be terminated when surface 60 is coincident with broken line 62.
- Trenches 66 may not be as deep as trenches 64, as illustrated in Figure 6. Should the ablating process continue until ends 46 of trenches 66 are exposed, device wafer 20 has been thinned too much.
- the trenches may be placed, for example, in areas of the wafer in which devices will not be formed.
- the area density of the trenches may range from about 2% to about 15% of the area of a major surface of device wafer 20.
- the area density of the trenches can be controlled by placement of trenches in saw-grid area and other otherwise unused areas of the wafer to match control conditions to stop the ablating process.
- All trenches may have the same width between sidewalls 42 and 44, although the invention is not limited thereto. Trenches may vary in width. One advantage of trenches of uniform width is that the trenches would be filled with oxide more consistently than trenches of varying width.
- a major surface 60 has been ablated using the thickness of device wafer 20 as its predetermined depth, sidewalls 42 and 44 may be detected by separate equipment used to align subsequent implantation over the diffused regions 24 more precisely than could be achieved in the past.
- the subsequent device level making step can use the trenches as alignment marks to obtain improved alignment between the device level implants and the buried diffused regions 24. Alignment may rely for example on a sidewall 42 or 44. The more precise alignment assures that doping in a subsequent processing step is placed in the proximity of buried diffused regions 24 such that the buried diffused regions 24 can interact with doped regions created in the subsequent processing step.
- bonded wafer 54 is cut into chips. Chips are wire bonded and packaged as integrated circuits as is known in the art.
- the substrate wafer could be made of other materials known in the art including but not limited to polysilicon or silicon carbide.
- the device wafer could be made of other semiconductor materials known in the art including but not limited to indium phosphide, gallium arsenide, indium gallium phosphide and silicon carbide.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US385735 | 1999-08-30 | ||
US09/385,735 US6372600B1 (en) | 1999-08-30 | 1999-08-30 | Etch stops and alignment marks for bonded wafers |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1081748A2 true EP1081748A2 (de) | 2001-03-07 |
Family
ID=23522657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00307164A Withdrawn EP1081748A2 (de) | 1999-08-30 | 2000-08-21 | Ätzstops und Ausrichtungsmarkierungen für gebondete Scheiben |
Country Status (4)
Country | Link |
---|---|
US (1) | US6372600B1 (de) |
EP (1) | EP1081748A2 (de) |
JP (1) | JP2001111014A (de) |
KR (1) | KR20010021466A (de) |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003036699A2 (en) * | 2001-10-23 | 2003-05-01 | Cambridge Semiconductor Limited | Lateral semiconductor-on-insulator structure and corresponding manufacturing methods |
EP1469355A1 (de) * | 2002-12-20 | 2004-10-20 | ASML Netherlands B.V. | Verfahren zur Herstellung einer Vorrichtung |
US6844244B2 (en) | 2002-12-20 | 2005-01-18 | Asml Netherlands B.V. | Dual sided lithographic substrate imaging |
FR2925223A1 (fr) * | 2007-12-18 | 2009-06-19 | Soitec Silicon On Insulator | Procede d'assemblage avec marques enterrees |
EP2161742A1 (de) * | 2008-09-03 | 2010-03-10 | S.O.I.TEC. Silicon on Insulator Technologies S.A. | Verfahren zur Herstellung eines lokal passivierten Germanium-on-Insulator-Substrats |
EP2375442A1 (de) * | 2010-04-06 | 2011-10-12 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zur Herstellung eines Halbleitersubstrats |
US8223582B2 (en) | 2010-04-02 | 2012-07-17 | Soitec | Pseudo-inverter circuit on SeOI |
US8305803B2 (en) | 2010-01-14 | 2012-11-06 | Soitec | DRAM memory cell having a vertical bipolar injector |
US8304833B2 (en) | 2010-01-14 | 2012-11-06 | Soitec | Memory cell with a channel buried beneath a dielectric layer |
US8325506B2 (en) | 2010-01-14 | 2012-12-04 | Soitec | Devices and methods for comparing data in a content-addressable memory |
US8358552B2 (en) | 2010-03-11 | 2013-01-22 | Soitec | Nano-sense amplifier |
US8384425B2 (en) | 2009-12-08 | 2013-02-26 | Soitec | Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate |
US8432216B2 (en) | 2010-03-03 | 2013-04-30 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
US8455938B2 (en) | 2010-04-22 | 2013-06-04 | Soitec | Device comprising a field-effect transistor in a silicon-on-insulator |
US8508289B2 (en) | 2009-12-08 | 2013-08-13 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
US8575697B2 (en) | 2010-03-08 | 2013-11-05 | Soitec | SRAM-type memory cell |
US8664712B2 (en) | 2009-12-08 | 2014-03-04 | Soitec | Flash memory cell on SeOI having a second control gate buried under the insulating layer |
WO2016149113A1 (en) * | 2015-03-17 | 2016-09-22 | Sunedison Semiconductor Limited | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
US9490264B2 (en) | 2010-01-14 | 2016-11-08 | Soitec | Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device |
US10304722B2 (en) | 2015-06-01 | 2019-05-28 | Globalwafers Co., Ltd. | Method of manufacturing semiconductor-on-insulator |
US10332782B2 (en) | 2015-06-01 | 2019-06-25 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
US10546771B2 (en) | 2016-10-26 | 2020-01-28 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2876219B1 (fr) * | 2004-10-06 | 2006-11-24 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
US7723178B2 (en) * | 2008-07-18 | 2010-05-25 | International Business Machines Corporation | Shallow and deep trench isolation structures in semiconductor integrated circuits |
JP5182143B2 (ja) * | 2009-02-19 | 2013-04-10 | ソニー株式会社 | 半導体装置の製造方法 |
JP2011044667A (ja) * | 2009-08-24 | 2011-03-03 | Shin Etsu Handotai Co Ltd | 半導体装置の製造方法 |
EP2320454A1 (de) * | 2009-11-05 | 2011-05-11 | S.O.I.Tec Silicon on Insulator Technologies | Substrathalter und Klammervorrichtung |
FR2953636B1 (fr) * | 2009-12-08 | 2012-02-10 | Soitec Silicon On Insulator | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
US8710629B2 (en) * | 2009-12-17 | 2014-04-29 | Qualcomm Incorporated | Apparatus and method for controlling semiconductor die warpage |
US8546961B2 (en) | 2011-01-10 | 2013-10-01 | International Business Machines Corporation | Alignment marks to enable 3D integration |
WO2018237379A2 (en) | 2017-06-23 | 2018-12-27 | Enzo Biochem, Inc. | COMPOUNDS MODULATING THE PATH OF SPHINGOSINE FOR THE TREATMENT OF CANCERS |
US11694968B2 (en) | 2020-11-13 | 2023-07-04 | Samsung Electronics Co., Ltd | Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate |
Family Cites Families (17)
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US5091330A (en) * | 1990-12-28 | 1992-02-25 | Motorola, Inc. | Method of fabricating a dielectric isolated area |
JPH04266047A (ja) * | 1991-02-20 | 1992-09-22 | Fujitsu Ltd | 埋め込み層形成に相当するsoi型半導体装置の製造方法及び半導体装置 |
US5258318A (en) * | 1992-05-15 | 1993-11-02 | International Business Machines Corporation | Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon |
JPH0834261B2 (ja) * | 1992-06-17 | 1996-03-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Bicmos集積回路用のsoi構造体およびその製造方法 |
US5382541A (en) * | 1992-08-26 | 1995-01-17 | Harris Corporation | Method for forming recessed oxide isolation containing deep and shallow trenches |
US5459104A (en) * | 1993-01-18 | 1995-10-17 | Mitsubishi Materials Silicon Corporation | Process for production of semiconductor substrate |
US5433650A (en) * | 1993-05-03 | 1995-07-18 | Motorola, Inc. | Method for polishing a substrate |
US5536675A (en) * | 1993-12-30 | 1996-07-16 | Intel Corporation | Isolation structure formation for semiconductor circuit fabrication |
US5413941A (en) * | 1994-01-06 | 1995-05-09 | Micron Technology, Inc. | Optical end point detection methods in semiconductor planarizing polishing processes |
US5439551A (en) * | 1994-03-02 | 1995-08-08 | Micron Technology, Inc. | Chemical-mechanical polishing techniques and methods of end point detection in chemical-mechanical polishing processes |
EP0698284B1 (de) * | 1994-03-15 | 2000-05-10 | National Semiconductor Corporation | Planarisierter isolationsgraben und feldoxid-isolationsstruktur |
US5872043A (en) * | 1996-07-25 | 1999-02-16 | Industrial Technology Research Institute | Method of planarizing wafers with shallow trench isolation |
JP3863624B2 (ja) * | 1997-03-24 | 2006-12-27 | 不二越機械工業株式会社 | ウェーハの研磨装置及びウェーハの研磨方法 |
US5728621A (en) * | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
JPH11158225A (ja) * | 1997-11-26 | 1999-06-15 | Mitsubishi Chemical Corp | 環状オレフィン系重合体の精製方法 |
JPH11177517A (ja) * | 1997-12-09 | 1999-07-02 | Hitachi Cable Ltd | 多重伝送装置 |
WO2001027350A1 (en) * | 1999-10-08 | 2001-04-19 | Speedfam-Ipec Corporation | Optimal offset, pad size and pad shape for cmp buffing and polishing |
-
1999
- 1999-08-30 US US09/385,735 patent/US6372600B1/en not_active Expired - Lifetime
-
2000
- 2000-08-21 EP EP00307164A patent/EP1081748A2/de not_active Withdrawn
- 2000-08-30 KR KR1020000050706A patent/KR20010021466A/ko not_active Application Discontinuation
- 2000-08-30 JP JP2000260173A patent/JP2001111014A/ja active Pending
Cited By (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003036699A2 (en) * | 2001-10-23 | 2003-05-01 | Cambridge Semiconductor Limited | Lateral semiconductor-on-insulator structure and corresponding manufacturing methods |
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Also Published As
Publication number | Publication date |
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JP2001111014A (ja) | 2001-04-20 |
KR20010021466A (ko) | 2001-03-15 |
US6372600B1 (en) | 2002-04-16 |
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