WO2009077538A2 - Process of assembly with buried marks - Google Patents

Process of assembly with buried marks Download PDF

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Publication number
WO2009077538A2
WO2009077538A2 PCT/EP2008/067652 EP2008067652W WO2009077538A2 WO 2009077538 A2 WO2009077538 A2 WO 2009077538A2 EP 2008067652 W EP2008067652 W EP 2008067652W WO 2009077538 A2 WO2009077538 A2 WO 2009077538A2
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WIPO (PCT)
Prior art keywords
substrate
process according
layer
thinning
marks
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PCT/EP2008/067652
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French (fr)
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WO2009077538A3 (en
Inventor
Bernard Aspar
Chrystelle Lagahe
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S.O.I.Tec Silicon On Insulator Technologies
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Publication of WO2009077538A2 publication Critical patent/WO2009077538A2/en
Publication of WO2009077538A3 publication Critical patent/WO2009077538A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/002—Aligning microparts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/05—Aligning components to be assembled
    • B81C2203/051—Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to the realisation of a multilayer structure comprising a structured buried layer as well as patterns, called alignment marks, making it possible to position elements on the surface of the structure, relatively to the buried layer.
  • Structures comprising a structured buried layer, for example:
  • patterned an SOI substrate structure, referred to as "patterned", for which the buried insulation layer can have variable thicknesses in different zones of the substrate, and can even be discontinuous (in this case the substrate has SOI zones and non — SOI zones)
  • - a substrate structure comprising a buried layer formed, entirely or partially, of components, - semiconductor structures having CMOS applications, in memories, 3D structures, optical, logical, analogue circuits, microsystems, sensors, etc.
  • the multilayer structures with a structured buried layer are realised by assembling a first substrate with a second substrate, one or the other of the substrates (or both of them) having, on its surface, the structured layer intended to be buried. One or the other of these substrates can then be thinned.
  • the manufacture, on these structures, of devices or of electronic, or microelectronic, or optoelectronic components requires a precise positioning of these devices or components, with regards to the buried structure, in order to allow to obtain the sought functions.
  • Document WO 2005/067054 presents a process for manufacturing electronic chips using semiconductor wafers, an active layer and conductive or insulation layers being transferred by molecular bonding on a substrate support.
  • this document proposes to etch trenches in a donor substrate and to fill them with a material, for example Si02.
  • An active layer, resulting from the support substrate, is then formed on a transfer substrate, by bonding and thinning of the donor substrate; the trenches, very deep within this active layer, can then be detected or are made visible subsequent to a step of thinning.
  • the invention first relates to a process of forming an assembly of at least two substrates, of which at least one comprises at least one alignment mark, this process comprising the following steps: a) a step of forming at least one alignment mark on or in a first substrate or a layer formed on this substrate, b) a first assembling step or bonding step, for example via molecular bonding, of this first substrate, or of the surface of a layer formed on this first substrate, with a second substrate or a layer formed on this second substrate, c) a step of thinning of at least a peripheral portion of at least one of the two substrates, in order to reveal at least one of said alignment marks.
  • thinning is meant a thinning on all or a portion of the outside edge of the substrate, i.e. a routing.
  • specific marks are formed at least on one of the two substrates (donor and/or receiving) . These specific marks are then made visible by a thinning process on the periphery or a routing process.
  • a removal of material is applied to multilayer structures, or comprising a stack of layers or of substrates. Via this removal of material, alignment patterns are made to appear, which were made hidden, not visible or detectable after various steps of assembly of wafer or of stacking of layers.
  • a process according to the invention makes it possible to find again all or a portion of the alignment patterns buried during the manufacture of said structure.
  • the invention also relates to the structure obtained from this process.
  • the invention can make it possible to combine, in a single and same step, a routing making it possible to eliminate zones that are weakly bonded on the periphery of the substrates and a removal of material making it possible to have alignment patterns or patterns appear, which are hidden but which are to be found again.
  • the patterns or alignment marks can then be used as reference marks, for example in the manufacture of semiconductor structures.
  • a layer of silicon oxide, or of silicon nitride, or of polysilicon can be formed on the first substrate and/or on the second substrate.
  • the marks can be formed in or on a layer present on the surface of at least one of these two substrates, for example a layer of silicon oxide, or of silicon nitride, or of polysilicon or a metal layer, present on at least one of the two receiving or donor substrates .
  • the mark(s) can be realised by direct chemical etching of the first substrate and/or of a layer formed on this first substrate, or through a layer formed on the first substrate.
  • the marks can be located at the edge of wafers, at a distance from this edge less than, for example, 3 mm.
  • the alignment marks are local, more particularly at the substrate edge.
  • the marks can be for example alignment crosses.
  • marks specifically realised within the structure are considered as alignment patterns, but also are all or a portion of a component, of which is used in order to assist with the alignment.
  • This can also be cavities etched in the support wafer (with the thin layer on top) of which the structure will be used for the alignment.
  • the step c) can be a step of peripheral thinning, or of routing, of the first substrate and/or of the second substrate.
  • the first substrate can be, after step c) , subjected to a step of thinning, or even a portion of this substrate can be cut apart sideways, for example via splitting or fracture of this substrate.
  • the step c) comprises a first sub-step of peripheral thinning or of routing (for example mechanical), which leaves the marks buried, then a second sub-step of peripheral thinning (or of routing) (for example chemical), which reveals the alignment mark(s) .
  • a sub-step of chemical etching is more preferably selective in relation to the material of the alignment mark(s) or to the material of the first substrate and/or to the material of a layer wherein the pattern (s) or marks are formed and/or to the material of a layer formed on the first or the second substrate.
  • the first sub-step of thinning makes it possible to leave a substrate thickness of between 100 ⁇ m and 10 ⁇ m, the second sub-step of thinning making it possible to leave a thickness smaller than 10 ⁇ m or 20 ⁇ m.
  • the step c) can be carried out in the strongly bonded zones, in order to suppress the weakly bonded peripheral zones, in addition to having the alignment marks appear.
  • This step c) can be a step of removing material, locally and/or over the entire periphery of one of the substrates, such as the thinned substrate, and possibly a layer deposited on this substrate.
  • This step c) makes it possible to suppress all or a portion of the thickness of a portion at least of the first and/or of the second substrate and/or of a layer, for example transparent, formed on one of these substrates, and to possibly leave only a sufficiently thin thickness of a transparent layer, which leaves the marks visible.
  • a layer, transparent or not transparent, can be inserted between the two substrates, on one and/or the other between them, before assembling.
  • This layer can be an etch-stop layer, in order to specifically stop a step of thinning and/or of routing on this layer.
  • the invention also relates to a manufacturing process for a stack of at least three layers or substrates, provided with at least one alignment mark, comprising: - a process of forming an assembly of at least two substrates with at least one alignment mark, such as described hereinabove, the assembly of these at least two substrates with at least one third substrate.
  • the assembly with at least one third substrate can be of the type by molecular bonding.
  • FIG. 3A to 3E show an alternative of the first embodiment of the invention
  • figures 4A to 4G show yet another embodiment of the invention and an alternative of this embodiment
  • figures 5A - 5G show yet another embodiment of the invention and an alternative of this embodiment
  • - figures 6A - 6B show two configurations of marks, with various kinds of material removal, local and/or over the entire periphery
  • figures 7A - 7C show three assemblies, each of two substrates of which one comprises a weakened zone
  • a donor substrate 2 and a support substrate 4 are described.
  • the latter can be of the semi-conductor type, for example of silicon, or of SiC, or of p-SiC, or of Ge, or of GaN or of a semi-conductor of the III V, II VI kind; it may be of the piezoelectric, or pyroelectric or ferroelectric kind.
  • the substrate 2 it can be of Si, or of glass, or of quartz, or of sapphire, or of a material of the III V or II VI kind, or of ceramic, etc.
  • the structures with stacked layers can be the result for example of a layer transfer from a donor substrate to a receiving substrate (support substrate) .
  • the donor substrate is either thinned according to the conventional techniques (mechanical rectification, polishing, chemical attack) or detached, for example according to a process of the "Smart CutTM" type, or process by fracturing the substrate.
  • a weakened plane may have been realised during an implantation step, prior to the step of bonding with the receiving substrate.
  • the layer thus transferred can in particular be too thick to enable the visualisation and/or the detection, by standard microelectronic equipment, of alignment marks. However, the latter will make it possible to carry out the rest of the process on the substrate .
  • This invention also applies to wafers that do not involve a layer transfer, in situations wherein it is desired to make visible patterns that are useful for the alignment.
  • certain substrates are assembled by adhesive contact, in particular via molecular bonding.
  • the assembly technique via adhesive like contact for example via molecular adhesion or via gluing, described in particular by Q. Y. Tong in "Silicon Wafer Bonding Technology for VLSI and MEMS applications", Edited by S.S.Iyer and A.J. Auberton - Herve, 2002, INSPEC, London, Chapter 1, pages 1 - 20.
  • steps of preparing surfaces before bonding can be carried out, such as polishing, and/or cleaning and/or plasma treatment, in order to allow for proper bonding with high bonding energy.
  • a heat treatment can then be applied in order to reinforce the bonding interface.
  • the heat treatment can be carried out between 200 0 C and 1200 0 C for around ten minutes to a few hours, according to, also, the compatibility of the buried layers.
  • a first embodiment shall be described in liaison with figures IA - IE. According to this first embodiment a donor substrate 2 (figure IA) and a support substrate 4 (figure IB) are selected.
  • the substrate 4 comprises some alignment patterns 10, they are located preferentially at approximately a distance d, d' preferentially comprised between 1 mm and 5 mm from the edge of this substrate, for example between 1.5 mm and 2 mm.
  • the two substrates are then assembled for example via molecular bonding.
  • the patterns 10 then disappear under the substrate 2.
  • the receiving wafer or substrate 4 or the layer 50' that covers it (case in figure 2C) , functionalised or not functionalised, comprising the pattern (s) 10, is assembled, for example via adhesive contact, in particular via molecular bonding, with the donor substrate 2.
  • adhesive contact in particular via molecular bonding
  • a removal of material from the donor substrate 2 is then carried out in order to have the alignment marks 10 appear: for example, the substrate 2 first undergoes a mechanical thinning (figure ID) then a chemical thinning (figure IE) , as is explained further on.
  • the step of removing material (figures ID and IE) , which enables to make the marks appear, is performed after bringing into contact the two substrates.
  • This step makes it possible to remove the material located locally and/or in the peripheral zone of the donor substrate 2, previously bonded to the support substrate 4 and located directly above the buried marks or patterns 10 of this support, in order to have these marks or patterns appear.
  • the removal of material makes it possible to eliminate either the entire periphery of the substrate 2, or only a portion of this periphery, until the hidden marks appear.
  • the eliminated width L is for example between 1 mm and 5 mm. It is adapted in such a way that the alignment marks can be made visible. More preferably, it is also sought to minimise the removal of material, in order to avoid needlessly losing any of it. It is also possible to carry out a partial removal of material from the substrate 2 before it is assembled with the substrate 4 wherein the marks are carried out. This prior removal is carried out by taking into account the marks 10, 10' of the support 4. Then there is an assembly with the substrate 4 and continuation of the thinning, possibly in two steps as already indicated hereinabove, this as such makes it possible to a have a zone that is not bonded on the marks .
  • a mask is applied to the surface 5 of the substrate 4, then a step of etching (such as is generally used in microelectronics) is applied, for example via dry or wet etching (for example with potash, or TMAH (Tetramethylammonium hydroxide) ) , making it possible to etch the substrate 4 on a depth varying from a few hundred nm to a few micrometers.
  • etching such as is generally used in microelectronics
  • TMAH Tetramethylammonium hydroxide
  • FIG. 2A and 2B Another process, shown in figures 2A and 2B, consists in making an oxide layer 50 via an oxidation of the surface 5 of the substrate 4, the latter being for example of silicon, then masking, via a resin, this oxide layer thus formed. After photoetching the resin, and attacking the silicon oxide 50 in the unmasked zones, then eliminating the mask, the silicon is etched according to processs of dry or wet etching selectively in the zones 10' (figure 2B), that are not protected by the oxide in order to form the desired patterns 10. The oxide 50 is then eliminated. In both cases the patterns 10 are made in the thickness of the substrate 4 and show on its surface 5.
  • the marks 10 are formed, by masking and etching, in a surface layer 50', which is not eliminated subsequently, and they may be extended in the substrate 4.
  • the patterns are made at least in the thickness of the layer 50' and show on the surface of this layer.
  • the size or width 1 of the patterns (the width 1 of figure IB) , in the plane of the substrate or of the layer wherein they are formed depends on the equipment used to recognise alignment marks. Typically 1 is between around ten to a few hundred micrometers, for example between 50 ⁇ m and 500 ⁇ m. The depth of the patterns is for example between 200 nm and 5 ⁇ m.
  • These patterns 10 can then be filled with a material, for example of the kind that can be eliminated selectively in relation to material of the substrate 4 or of the layer 50' wherein they were formed (in the case where the material of the pattern could hinder the later manufacture of components) .
  • a material for example of the kind that can be eliminated selectively in relation to material of the substrate 4 or of the layer 50' wherein they were formed (in the case where the material of the pattern could hinder the later manufacture of components) .
  • silicon oxide, or polysilicon in particular in the case of a substrate 4 of silicon
  • silicon for example in the case of a substrate 4 of polysilicon
  • SiC silicon
  • polySiC silicon
  • Ge or of silica
  • Various combinations can be considered according to the kind of substrate, each combination having for purpose to form marks that withstand the standard process used for forming the structures but also the process according to the invention (chemical etching and/or various thinnings) .
  • the marks can remain in the form of cavities or be filled.
  • the depositing techniques implemented in order to fill the patterns 10 and/or to cover the surface 5 of the wafer 4 are the techniques such as for example PECVD, or LPCVD.
  • Figure 1C shows the case of the substrate 4 of the figure IB, but this figure and the following ones can be adapted without difficulty to the case of the substrate 4 in figure 2B or 2C) .
  • the mechanical step makes it possible to remove a substantial fraction of the periphery of the substrate 2, according to its thickness, the chemical thinning making it possible to eliminate a residual thickness 12 of this substrate that covers the marks 10 (figure ID) .
  • a thickness for example between 300 ⁇ m or 400 ⁇ m and 625 ⁇ m or lmm is first eliminated mechanically in order that a thickness 12 remains for example between 50 ⁇ m and 500 ⁇ m, for example of a order of magnitude of 100 micrometers, of the donor substrate 2, above the pattern (s) 10.
  • This step can be carried out by mechanical means, such as those implemented by the technique of mechanical rectification of the wafer edge such as the mechanical routing technique (“Etch Grinder”) .
  • the second sub-step of thinning makes it possible to etch the residual thickness, for example between 50 ⁇ m and 500 ⁇ m such as indicated hereinabove, of the donor substrate 2 until the pattern (s) 10 are reached and made to appear. It can also make it possible to enlarge the width L whereon the mechanical etching has made it possible to eliminate the material.
  • This second sub-step makes it possible to find again the pattern (s) 10 which had been hidden subsequent to the bonding with the donor substrate 2. These patterns 10 appear then on the surface 5 of the substrate 4, in the portion of this surface that had been cleared during the step of thinning.
  • a chemical attack can be implemented.
  • the chemistry applied is more preferably selective between the nature of the substrate 2 to be etched and those of the material of the sought pattern 10 and of the material of the substrate 4.
  • this chemical step makes it possible to attack the material of the substrate 2, but without attacking, or by attacking much less, the material of the pattern 10 and the material of the substrate 4 (the ratios (etching rate of the material of the substrate 2/etching rate of the material of the pattern 10) and (etching rate of the material of the substrate 2/etching rate of the material of the substrate 4) are each for example greater than 10, typically of a magnitude of 1000) .
  • the etching is for example carried out by a chemical TMAH-based treatment. For example in the case of the selective attack of the silicon, this etching rate ratio will be greater than 3000 in relation to the oxide.
  • the thinning is carried out in a single step, by a selective chemical thinning (without mechanical thinning) over the entire thickness of the substrate 2.
  • the substrate 4 comprises on the surface an intermediary layer 8 intended to be assembled with the other substrate.
  • This layer 8 can be an etch-stop layer, transparent or not transparent.
  • the examples of material of substrates 2, 4 and of dimensions d, d' , 1, L as well as the depth of the marks can be those already given hereinabove.
  • Figure 3B thus shows the case of a substrate 4 whereon such an intermediary layer 8 is formed, after forming of marks 10 as already explained hereinabove.
  • the two substrates are then assembled, via molecular bonding as already explained hereinabove.
  • the structure in figure 3C is then obtained: the layer 8 is imbedded between the two substrates 2, 4.
  • a removal of material from the donor substrate 2 is then carried out in order to have the alignment marks 10 appear: for example, the substrate 2 first undergoes a mechanical thinning as already explained hereinabove in liaison with figure ID.
  • the layer 8 may be transparent. The transparency properties depend on the type of material of this layer and its thickness.
  • the layer 8 is not transparent, it must also be eliminated above marks 10. If the thinning takes place in two steps, according to the thickness of this layer 8, it will begin to be eliminated during the step of mechanical thinning or only during the step of chemical thinning.
  • the step of chemical thinning is such that it eliminates at least one portion of the layer 8, but by not attacking, or very little, the material of the patterns 10 and the material of the substrate 4.
  • This layer can be an etch-stop layer; its selectivity is such that it alone will be etched. The final structure is then that of figure
  • the layer 8 is transparent, it makes it possible to visually have access to the position of the marks 10. In this case, as indicated hereinabove, it is not necessary to eliminate it.
  • the step of chemical etching attacks the substrate 2 but is selective in relation to the material of this layer 8. The final structure is then that of figure 3D.
  • a second embodiment shall be described in liaison with figures 4A - 4E.
  • the alignment marks 20 are this time located in the donor substrate 2, and are then transferred to the support substrate 4. They are made visible after this transfer.
  • the pattern (s) formed in the donor substrate 2 are located preferentially at the edge of this substrate, for example at a distance d, d' of I S
  • the alignment mark is a trench made in the donor substrate 2 itself; this first case will be treated hereinbelow in liaison with figures 4A - 4G, or the alignment mark is made within a layer present on the surface of the donor substrate 2, as for example a layer of silicon oxide, or of silicon nitride, or of polysilicon or a metal layer; this first case shall be treated hereinbelow in liaison with figures 5A - 5G,
  • the alignment marks 20 are made in the substrate 2 (figure 4A) according to the same principle as that described in the first embodiment: forming of patterns which are then filled in by the same materials as in the first embodiment (figure 4B) .
  • the step of removing material in order to have the marks appear is performed after bringing into contact and assembling the two substrates (figure 4C) , for example via molecular bonding.
  • the removal of material is more preferably performed including in the strongly bonded zones, in order to properly suppress the weakly bonded peripheral zones but also the material in the zones wherein the patterns are located.
  • the step of routing is performed in order to eliminate the weakly bonded peripheral zones.
  • a thickness h is thus removed in such a way that between 10 ⁇ m and 100 ⁇ m remains on the edge of the donor substrate 2, either locally or over the entire periphery of the wafer. It is also possible to carry out a local removal, combined with a removal over the entire periphery of the wafer, as explained further on, in liaison with figures 6A - 6C.
  • This step can be carried out mechanically, examples of mechanical treatment that can be used have already been given hereinabove.
  • a second sub-step of thinning, makes it possible to remove the remaining thickness 12 of the donor substrate 2, until the pattern (s) 20 are reached and made to appear. This step makes it possible to find the patterns 20 again that had been hidden subsequent to the bonding of the donor substrate 2 with the substrate 4. The patterns then appear in relief in relation to the open surface 5 of the substrate 4.
  • a chemical attack can be implemented.
  • the chemistry applied is more preferably selective between on the one hand the material of the donor substrate 2 to be etched and on the other hand the material on the surface of the underlying substrate 4 as well as that of the pattern 20 sought.
  • this chemical sub-step makes it possible to attack the material of the substrate 2, but without attacking, or by attacking much less, the materials of the pattern 20 (the ratio of the etching rate of the material of the substrate 2/etching rate of the material of the pattern 20 is for example greater than 10, typically a magnitude of 1000) and of the substrate 4 (the ratio of the etching rate of the material of the substrate 2/etching rate of the material of the substrate 4 is for example greater than 10, typically of a magnitude of 1000) .
  • the chemical etching is for example carried out via a dry or wet etching treatment (for example TMAH or KOH for the attack of the silicon; these treatments are highly selective in relation to materials of the SiO2 or SiN type, etc . ) .
  • TMAH TMAH
  • KOH for the attack of the silicon
  • the substrate 2 comprises in fact a transparent surface layer 2' wherein the marks 20 are going to be made. After assembly with the substrate 4 and elimination of the portion of the substrate 2 located above the transparent layer and above the marks 20, the structure in figure 4G is obtained.
  • the transparent nature of the layer 2' makes it possible to locate or to visualise the marks, without there being a need to remove the transparent layer 2' .
  • the alignment mark(s) 60 are made in an intermediary layer 6, which may be transparent, present on the surface of the donor substrate 2, as for example a layer of silicon oxide, or of silicon nitride, or of polysilicon .
  • the alignment marks 60 are made in the layer
  • the patterns 60 can be filled with a material, for which examples have already been given hereinabove .
  • the material removal step is applied after bringing into contact (figure 5C) the two substrates, or rather the layer 6 and of the substrate 4.
  • a removal of material is performed in the substrate 2, more preferably above the strongly bonded zones, in order to properly suppress the weakly bonded peripheral zones, for the same reasons as those already mentioned hereinabove.
  • a certain thickness h' is removed (for example in order to leave a remaining thickness between 10 ⁇ m and 100 ⁇ m) from the edge of the donor substrate 2, either locally, or over the entire periphery of the substrate. It is also possible to performe a local removal, combined with a removal over the entire periphery of the substrate.
  • a chemical attack can be implemented.
  • the chemistry applied is more preferably selective between on the one hand the material of the donor substrate 2 to be etched and on the other hand the material of the layer 6 and that of the marks 60.
  • this chemical steps makes it possible to attack the material of the substrate 2, but without attacking, or by attacking much less, the materials of the layer 6 and of the marks 60 (the ratio (etching rate of the material of the substrate 2/etching rate of the material of the layer 6) is for example greater than 10, typically of a magnitude of 1000; and the same for the ratio (etching rate of the material of the substrate 2/etching rate of the material of the marks 60)) .
  • the chemical etching is for example a dry or wet etching (for example TMAH or KOH) . According to an alternative of this case
  • the substrate 2 comprises in fact a transparent surface layer 2' whereon the layer 6 is made: it is in the latter that the marks 60 shall be made.
  • the structure in figure 5G is obtained.
  • the transparent nature of the layer 2' makes it possible to locate the marks.
  • a surface layer 2' would not be transparent is in fact that which is already described hereinabove in liaison with figures 5A - 5E : the portion of the layer 2' that masks the marks must then be eliminated.
  • the removal of material can be carried out over the entire periphery of a substrate and/or locally.
  • figures 6A and 6B show, as a top view, two different configurations, with marks 100, 100' : - figure 6A corresponds to the case of a removal of material over the entire periphery of the wafer; the thinning is then a routing,
  • the material removal process can be performed either before, or after the step of thinning, intended to reduce the thickness of the donor substrate 2.
  • the peripheral material is removed before the step of thinning of the rest of the wafer to the desired thickness in order to avoid creating weakly bonded zones.
  • the multilayer structure can be used such as for the manufacture of electronic, and/or optical and/or other components.
  • the donor substrate 2 can be thinned according to the conventional techniques (polishing, and/or chemical attack) .
  • a weakened plane was formed, for example by a step of atomic or ionic implantation (helium and/or hydrogen for example) . This results, after assembling with the substrate 4 and revealing of the marks 10, 20, 60, in one of the structures shown in figures 7A, 7B, 7C, respectively for the first embodiment and for the two cases considered for the second embodiment.
  • the reference 18 designates the weakened plane (or defect plane) resulting from the implantation carried out in the donor substrate 2.
  • One (or several) new layer (s) 100, 100', 200, 200', 600, 600' can also, or as an alternative be transferred on this thinned substrate 2', for example via molecular adhesion and separation using a donor substrate, for example also by "Smart CutTM” technique or substrate splitting.
  • the marks 10, 20, 60 remain visible and make an alignment possible of the realised components and/or of the new transferred layer.
  • the support substrate 4 can also be the object of various treatments, for example it can be thinned via different techniques (mechanical rectification, and/or polishing and/or chemical attack and/or substrate splitting) .

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Abstract

The invention relates to a process of forming an assembly of at least two substrates with at least one alignment mark, comprising the following steps: a) a step of forming of at least one alignment mark (10) on or in a first substrate (4) or a layer formed on this substrate, b) a first step of assembly of this first substrate, or of a layer formed on this first substrate, with a second substrate (2) or a layer formed on this second substrate, c) a step of thinning of at least a peripheral portion of at least one of the two substrates, in order to have at least one of said alignment marks appear.

Description

PROCESS OF ASSEMBLY WITH BURIED MARKS
TECHNICAL FIELD AND PRIOR ART
The invention relates to the realisation of a multilayer structure comprising a structured buried layer as well as patterns, called alignment marks, making it possible to position elements on the surface of the structure, relatively to the buried layer.
Structures are known comprising a structured buried layer, for example:
- an SOI substrate structure, referred to as "patterned", for which the buried insulation layer can have variable thicknesses in different zones of the substrate, and can even be discontinuous (in this case the substrate has SOI zones and non — SOI zones)
- a substrate structure comprising a buried layer formed, entirely or partially, of components, - semiconductor structures having CMOS applications, in memories, 3D structures, optical, logical, analogue circuits, microsystems, sensors, etc.
Advantageously, the multilayer structures with a structured buried layer are realised by assembling a first substrate with a second substrate, one or the other of the substrates (or both of them) having, on its surface, the structured layer intended to be buried. One or the other of these substrates can then be thinned. The manufacture, on these structures, of devices or of electronic, or microelectronic, or optoelectronic components requires a precise positioning of these devices or components, with regards to the buried structure, in order to allow to obtain the sought functions.
It is known, in order to ease the proper positioning of these devices in relation to one another, to have patterns (or alignment marks) on this surface. These patterns can be formed for example by dry or wet etching, by lithography, in or on the surface of the substrate . However these marks can be buried, especially during the manufacture of structures comprising a stack of several layers, when this stack is obtained by the assembly of at least two thick structures. As such, for relatively thick layers and/or for some of the materials used, these marks are no longer visible or even detectable.
There then arises the problem of positioning components on the surface of the wafer.
Document WO 2005/067054 presents a process for manufacturing electronic chips using semiconductor wafers, an active layer and conductive or insulation layers being transferred by molecular bonding on a substrate support.
In order to overcome the problems of aligning the patterns, this document proposes to etch trenches in a donor substrate and to fill them with a material, for example Si02. An active layer, resulting from the support substrate, is then formed on a transfer substrate, by bonding and thinning of the donor substrate; the trenches, very deep within this active layer, can then be detected or are made visible subsequent to a step of thinning.
There is the problem of finding a new process for realising positioning marks, in particular in the case of a multilayer structure. More preferably, this new process does not have the limitations mentioned hereinabove for the known processs.
DESCRIPTION OF THE INVENTION
The invention first relates to a process of forming an assembly of at least two substrates, of which at least one comprises at least one alignment mark, this process comprising the following steps: a) a step of forming at least one alignment mark on or in a first substrate or a layer formed on this substrate, b) a first assembling step or bonding step, for example via molecular bonding, of this first substrate, or of the surface of a layer formed on this first substrate, with a second substrate or a layer formed on this second substrate, c) a step of thinning of at least a peripheral portion of at least one of the two substrates, in order to reveal at least one of said alignment marks.
By thinning is meant a thinning on all or a portion of the outside edge of the substrate, i.e. a routing.
According to the invention, specific marks are formed at least on one of the two substrates (donor and/or receiving) . These specific marks are then made visible by a thinning process on the periphery or a routing process.
According to this invention a removal of material is applied to multilayer structures, or comprising a stack of layers or of substrates. Via this removal of material, alignment patterns are made to appear, which were made hidden, not visible or detectable after various steps of assembly of wafer or of stacking of layers. In particular, a process according to the invention makes it possible to find again all or a portion of the alignment patterns buried during the manufacture of said structure. The invention also relates to the structure obtained from this process. The invention can make it possible to combine, in a single and same step, a routing making it possible to eliminate zones that are weakly bonded on the periphery of the substrates and a removal of material making it possible to have alignment patterns or patterns appear, which are hidden but which are to be found again.
The patterns or alignment marks can then be used as reference marks, for example in the manufacture of semiconductor structures. A layer of silicon oxide, or of silicon nitride, or of polysilicon can be formed on the first substrate and/or on the second substrate.
The marks can be formed in or on a layer present on the surface of at least one of these two substrates, for example a layer of silicon oxide, or of silicon nitride, or of polysilicon or a metal layer, present on at least one of the two receiving or donor substrates .
The mark(s) can be realised by direct chemical etching of the first substrate and/or of a layer formed on this first substrate, or through a layer formed on the first substrate.
The marks can be located at the edge of wafers, at a distance from this edge less than, for example, 3 mm. Preferably, the alignment marks are local, more particularly at the substrate edge.
The marks can be for example alignment crosses. Generally, marks specifically realised within the structure are considered as alignment patterns, but also are all or a portion of a component, of which is used in order to assist with the alignment. This can also be cavities etched in the support wafer (with the thin layer on top) of which the structure will be used for the alignment.
The nature of the marks created, with this purpose, within the stack, can be adapted according to used process used for material removal.
The step c) can be a step of peripheral thinning, or of routing, of the first substrate and/or of the second substrate. The first substrate can be, after step c) , subjected to a step of thinning, or even a portion of this substrate can be cut apart sideways, for example via splitting or fracture of this substrate.
According to an embodiment, the step c) comprises a first sub-step of peripheral thinning or of routing (for example mechanical), which leaves the marks buried, then a second sub-step of peripheral thinning (or of routing) (for example chemical), which reveals the alignment mark(s) . A sub-step of chemical etching is more preferably selective in relation to the material of the alignment mark(s) or to the material of the first substrate and/or to the material of a layer wherein the pattern (s) or marks are formed and/or to the material of a layer formed on the first or the second substrate. The first sub-step of thinning makes it possible to leave a substrate thickness of between 100 μm and 10 μm, the second sub-step of thinning making it possible to leave a thickness smaller than 10 μm or 20 μm. The step c) can be carried out in the strongly bonded zones, in order to suppress the weakly bonded peripheral zones, in addition to having the alignment marks appear.
This step c) can be a step of removing material, locally and/or over the entire periphery of one of the substrates, such as the thinned substrate, and possibly a layer deposited on this substrate.
This step c) makes it possible to suppress all or a portion of the thickness of a portion at least of the first and/or of the second substrate and/or of a layer, for example transparent, formed on one of these substrates, and to possibly leave only a sufficiently thin thickness of a transparent layer, which leaves the marks visible. A layer, transparent or not transparent, can be inserted between the two substrates, on one and/or the other between them, before assembling. This layer can be an etch-stop layer, in order to specifically stop a step of thinning and/or of routing on this layer.
If it is transparent, it can play the role of an etch- stop layer while leaving the marks visible.
The invention also relates to a manufacturing process for a stack of at least three layers or substrates, provided with at least one alignment mark, comprising: - a process of forming an assembly of at least two substrates with at least one alignment mark, such as described hereinabove, the assembly of these at least two substrates with at least one third substrate. The assembly with at least one third substrate can be of the type by molecular bonding.
BRIEF DESCRIPTION OF THE DRAWINGS
- Figures IA to IE show a first embodiment of the invention,
- figures 2A to 2C show the steps in order to form marks in a substrate,
- figures 3A to 3E show an alternative of the first embodiment of the invention, figures 4A to 4G show yet another embodiment of the invention and an alternative of this embodiment, figures 5A - 5G show yet another embodiment of the invention and an alternative of this embodiment, - figures 6A - 6B show two configurations of marks, with various kinds of material removal, local and/or over the entire periphery, figures 7A - 7C show three assemblies, each of two substrates of which one comprises a weakened zone,
- figures 8A - 8C show three stacks, each of two substrates of which one is thinned,
- figures 9A - 9C show three stacks, each of the substrates of which two were transferred on one of the previous stacks.
DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS
In this description the term substrate is used, but the term "wafer" could be used in place of the first. In what follows, the invention in the case of the assembly of two substrates, a donor substrate 2 and a support substrate 4 is described. The latter can be of the semi-conductor type, for example of silicon, or of SiC, or of p-SiC, or of Ge, or of GaN or of a semi-conductor of the III V, II VI kind; it may be of the piezoelectric, or pyroelectric or ferroelectric kind. With regards to the substrate 2, it can be of Si, or of glass, or of quartz, or of sapphire, or of a material of the III V or II VI kind, or of ceramic, etc. Indeed, the structures with stacked layers can be the result for example of a layer transfer from a donor substrate to a receiving substrate (support substrate) . In this case, the donor substrate is either thinned according to the conventional techniques (mechanical rectification, polishing, chemical attack) or detached, for example according to a process of the "Smart Cut™" type, or process by fracturing the substrate. A weakened plane may have been realised during an implantation step, prior to the step of bonding with the receiving substrate.
The layer thus transferred can in particular be too thick to enable the visualisation and/or the detection, by standard microelectronic equipment, of alignment marks. However, the latter will make it possible to carry out the rest of the process on the substrate . This invention also applies to wafers that do not involve a layer transfer, in situations wherein it is desired to make visible patterns that are useful for the alignment.
In what follows, certain substrates are assembled by adhesive contact, in particular via molecular bonding. The assembly technique via adhesive like contact, for example via molecular adhesion or via gluing, described in particular by Q. Y. Tong in "Silicon Wafer Bonding Technology for VLSI and MEMS applications", Edited by S.S.Iyer and A.J. Auberton - Herve, 2002, INSPEC, London, Chapter 1, pages 1 - 20.
Prior to such an assembly, steps of preparing surfaces before bonding can be carried out, such as polishing, and/or cleaning and/or plasma treatment, in order to allow for proper bonding with high bonding energy. A heat treatment can then be applied in order to reinforce the bonding interface. According to the kind of the substrates present, the heat treatment can be carried out between 2000C and 12000C for around ten minutes to a few hours, according to, also, the compatibility of the buried layers.
The Smart Cut® process is also mentioned in this description. It is for example described in the article of B.Aspar and A.J. Auberton - Herve in "Silicon Wafer Bonding Technology for VLSI and MEMS applications", edited by S.S.Iyer and A.J. Auberton - Herve, 2002, INSPEC, London, Chapter 3, pages 35 - 52.
A first embodiment shall be described in liaison with figures IA - IE. According to this first embodiment a donor substrate 2 (figure IA) and a support substrate 4 (figure IB) are selected.
The substrate 4 comprises some alignment patterns 10, they are located preferentially at approximately a distance d, d' preferentially comprised between 1 mm and 5 mm from the edge of this substrate, for example between 1.5 mm and 2 mm.
The two substrates (figure 1C) are then assembled for example via molecular bonding. The patterns 10 then disappear under the substrate 2.
In other words, the receiving wafer or substrate 4 or the layer 50' that covers it (case in figure 2C) , functionalised or not functionalised, comprising the pattern (s) 10, is assembled, for example via adhesive contact, in particular via molecular bonding, with the donor substrate 2. For these assembly techniques, indications have already been given hereinabove .
A removal of material from the donor substrate 2 is then carried out in order to have the alignment marks 10 appear: for example, the substrate 2 first undergoes a mechanical thinning (figure ID) then a chemical thinning (figure IE) , as is explained further on.
Except for a possible preliminary thinning before assembly (as is explained further on) the step of removing material (figures ID and IE) , which enables to make the marks appear, is performed after bringing into contact the two substrates.
This step makes it possible to remove the material located locally and/or in the peripheral zone of the donor substrate 2, previously bonded to the support substrate 4 and located directly above the buried marks or patterns 10 of this support, in order to have these marks or patterns appear. The removal of material makes it possible to eliminate either the entire periphery of the substrate 2, or only a portion of this periphery, until the hidden marks appear.
The eliminated width L (figure ID) is for example between 1 mm and 5 mm. It is adapted in such a way that the alignment marks can be made visible. More preferably, it is also sought to minimise the removal of material, in order to avoid needlessly losing any of it. It is also possible to carry out a partial removal of material from the substrate 2 before it is assembled with the substrate 4 wherein the marks are carried out. This prior removal is carried out by taking into account the marks 10, 10' of the support 4. Then there is an assembly with the substrate 4 and continuation of the thinning, possibly in two steps as already indicated hereinabove, this as such makes it possible to a have a zone that is not bonded on the marks .
The forming of the marks 10 shall now be explained.
According to a first process, a mask is applied to the surface 5 of the substrate 4, then a step of etching (such as is generally used in microelectronics) is applied, for example via dry or wet etching (for example with potash, or TMAH (Tetramethylammonium hydroxide) ) , making it possible to etch the substrate 4 on a depth varying from a few hundred nm to a few micrometers.
Another process, shown in figures 2A and 2B, consists in making an oxide layer 50 via an oxidation of the surface 5 of the substrate 4, the latter being for example of silicon, then masking, via a resin, this oxide layer thus formed. After photoetching the resin, and attacking the silicon oxide 50 in the unmasked zones, then eliminating the mask, the silicon is etched according to processs of dry or wet etching selectively in the zones 10' (figure 2B), that are not protected by the oxide in order to form the desired patterns 10. The oxide 50 is then eliminated. In both cases the patterns 10 are made in the thickness of the substrate 4 and show on its surface 5.
According to another alternative (figure 2C) the marks 10 are formed, by masking and etching, in a surface layer 50', which is not eliminated subsequently, and they may be extended in the substrate 4. In this case, the patterns are made at least in the thickness of the layer 50' and show on the surface of this layer. Regardless of their embodiment, the size or width 1 of the patterns (the width 1 of figure IB) , in the plane of the substrate or of the layer wherein they are formed depends on the equipment used to recognise alignment marks. Typically 1 is between around ten to a few hundred micrometers, for example between 50 μm and 500 μm. The depth of the patterns is for example between 200 nm and 5 μm.
These patterns 10 can then be filled with a material, for example of the kind that can be eliminated selectively in relation to material of the substrate 4 or of the layer 50' wherein they were formed (in the case where the material of the pattern could hinder the later manufacture of components) . For a further example, silicon oxide, or polysilicon (in particular in the case of a substrate 4 of silicon) , or silicon (for example in the case of a substrate 4 of polysilicon) or of SiC, or of polySiC, or of Ge, or of silica can thus be deposited in these patterns 10. Various combinations can be considered according to the kind of substrate, each combination having for purpose to form marks that withstand the standard process used for forming the structures but also the process according to the invention (chemical etching and/or various thinnings) .
The marks can remain in the form of cavities or be filled. The depositing techniques implemented in order to fill the patterns 10 and/or to cover the surface 5 of the wafer 4 are the techniques such as for example PECVD, or LPCVD.
Whether the substrate 4 is that of figure IB or 2B or 2C, the two substrates 2, 4 are then brought into contact (step in figure 1C) . Figure 1C shows the case of the substrate 4 of the figure IB, but this figure and the following ones can be adapted without difficulty to the case of the substrate 4 in figure 2B or 2C) .
The example of the thinning carried out in two steps, one mechanical and the other chemical, shall now be developed.
The mechanical step makes it possible to remove a substantial fraction of the periphery of the substrate 2, according to its thickness, the chemical thinning making it possible to eliminate a residual thickness 12 of this substrate that covers the marks 10 (figure ID) . A thickness for example between 300 μm or 400 μm and 625 μm or lmm is first eliminated mechanically in order that a thickness 12 remains for example between 50 μm and 500 μm, for example of a order of magnitude of 100 micrometers, of the donor substrate 2, above the pattern (s) 10. This step can be carried out by mechanical means, such as those implemented by the technique of mechanical rectification of the wafer edge such as the mechanical routing technique ("Etch Grinder") .
The second sub-step of thinning makes it possible to etch the residual thickness, for example between 50 μm and 500 μm such as indicated hereinabove, of the donor substrate 2 until the pattern (s) 10 are reached and made to appear. It can also make it possible to enlarge the width L whereon the mechanical etching has made it possible to eliminate the material. This second sub-step makes it possible to find again the pattern (s) 10 which had been hidden subsequent to the bonding with the donor substrate 2. These patterns 10 appear then on the surface 5 of the substrate 4, in the portion of this surface that had been cleared during the step of thinning.
For this second sub-step, a chemical attack can be implemented. In this case, the chemistry applied is more preferably selective between the nature of the substrate 2 to be etched and those of the material of the sought pattern 10 and of the material of the substrate 4. In other words, this chemical step makes it possible to attack the material of the substrate 2, but without attacking, or by attacking much less, the material of the pattern 10 and the material of the substrate 4 (the ratios (etching rate of the material of the substrate 2/etching rate of the material of the pattern 10) and (etching rate of the material of the substrate 2/etching rate of the material of the substrate 4) are each for example greater than 10, typically of a magnitude of 1000) . The etching is for example carried out by a chemical TMAH-based treatment. For example in the case of the selective attack of the silicon, this etching rate ratio will be greater than 3000 in relation to the oxide.
According to an alternative, the thinning is carried out in a single step, by a selective chemical thinning (without mechanical thinning) over the entire thickness of the substrate 2.
An alternative of the first embodiment shall be explained in liaison with figures 3A - 3E . At least one of the two substrates 2, 4
(here: the substrate 4 by way of example) comprises on the surface an intermediary layer 8 intended to be assembled with the other substrate. This layer 8 can be an etch-stop layer, transparent or not transparent. The examples of material of substrates 2, 4 and of dimensions d, d' , 1, L as well as the depth of the marks can be those already given hereinabove.
Figure 3B thus shows the case of a substrate 4 whereon such an intermediary layer 8 is formed, after forming of marks 10 as already explained hereinabove.
The two substrates are then assembled, via molecular bonding as already explained hereinabove. The structure in figure 3C is then obtained: the layer 8 is imbedded between the two substrates 2, 4. A removal of material from the donor substrate 2 is then carried out in order to have the alignment marks 10 appear: for example, the substrate 2 first undergoes a mechanical thinning as already explained hereinabove in liaison with figure ID. The layer 8 may be transparent. The transparency properties depend on the type of material of this layer and its thickness.
If the layer 8 is not transparent, it must also be eliminated above marks 10. If the thinning takes place in two steps, according to the thickness of this layer 8, it will begin to be eliminated during the step of mechanical thinning or only during the step of chemical thinning. The step of chemical thinning is such that it eliminates at least one portion of the layer 8, but by not attacking, or very little, the material of the patterns 10 and the material of the substrate 4. This layer can be an etch-stop layer; its selectivity is such that it alone will be etched. The final structure is then that of figure
3E.
If the layer 8 is transparent, it makes it possible to visually have access to the position of the marks 10. In this case, as indicated hereinabove, it is not necessary to eliminate it. The step of chemical etching attacks the substrate 2 but is selective in relation to the material of this layer 8. The final structure is then that of figure 3D.
A second embodiment shall be described in liaison with figures 4A - 4E. The alignment marks 20 are this time located in the donor substrate 2, and are then transferred to the support substrate 4. They are made visible after this transfer.
The pattern (s) formed in the donor substrate 2 are located preferentially at the edge of this substrate, for example at a distance d, d' of I S
approximately 1 to 5 mm from its edge, preferentially 1.5 to 3 mm. This distance depends on the bonding zone at the edge because the marks are in the donor: it is sought that the marks be in a strongly bonded zone in order to be found again since, otherwise, they risk being eliminated during the routing, which aims among other things to eliminate the weakly bonded zone. The latter is lateral, d and d' are therefore chosen in such a way that the pattern (s) are beyond this weakly bonded zone.
Two cases or alternatives can be carried out, according to the forming of the alignment marks:
- either the alignment mark is a trench made in the donor substrate 2 itself; this first case will be treated hereinbelow in liaison with figures 4A - 4G, or the alignment mark is made within a layer present on the surface of the donor substrate 2, as for example a layer of silicon oxide, or of silicon nitride, or of polysilicon or a metal layer; this first case shall be treated hereinbelow in liaison with figures 5A - 5G,
In the first case (shown in figures 4A - 4E), the alignment marks 20 are made in the substrate 2 (figure 4A) according to the same principle as that described in the first embodiment: forming of patterns which are then filled in by the same materials as in the first embodiment (figure 4B) .
The step of removing material in order to have the marks appear is performed after bringing into contact and assembling the two substrates (figure 4C) , for example via molecular bonding. The removal of material is more preferably performed including in the strongly bonded zones, in order to properly suppress the weakly bonded peripheral zones but also the material in the zones wherein the patterns are located. Normally, the step of routing is performed in order to eliminate the weakly bonded peripheral zones. Within the framework of the invention, one is careful to form the marks beyond this zone, as explained hereinabove; the step of routing then aims to eliminate the weakly bonded peripheral zone(s) but also to remove more material in the zones where the bonding is stronger, where the marks are located.
In a first sub-step of thinning, a thickness h is thus removed in such a way that between 10 μm and 100 μm remains on the edge of the donor substrate 2, either locally or over the entire periphery of the wafer. It is also possible to carry out a local removal, combined with a removal over the entire periphery of the wafer, as explained further on, in liaison with figures 6A - 6C. This step can be carried out mechanically, examples of mechanical treatment that can be used have already been given hereinabove.
After this step (figure 4D) , the edges 12 of the substrate 2 remain. The marks 20 are still positioned hidden under these edges.
A second sub-step of thinning, (figure 4E) makes it possible to remove the remaining thickness 12 of the donor substrate 2, until the pattern (s) 20 are reached and made to appear. This step makes it possible to find the patterns 20 again that had been hidden subsequent to the bonding of the donor substrate 2 with the substrate 4. The patterns then appear in relief in relation to the open surface 5 of the substrate 4.
For this sub-step, a chemical attack can be implemented. In this case, the chemistry applied is more preferably selective between on the one hand the material of the donor substrate 2 to be etched and on the other hand the material on the surface of the underlying substrate 4 as well as that of the pattern 20 sought. In other words, this chemical sub-step makes it possible to attack the material of the substrate 2, but without attacking, or by attacking much less, the materials of the pattern 20 (the ratio of the etching rate of the material of the substrate 2/etching rate of the material of the pattern 20 is for example greater than 10, typically a magnitude of 1000) and of the substrate 4 (the ratio of the etching rate of the material of the substrate 2/etching rate of the material of the substrate 4 is for example greater than 10, typically of a magnitude of 1000) . The chemical etching is for example carried out via a dry or wet etching treatment (for example TMAH or KOH for the attack of the silicon; these treatments are highly selective in relation to materials of the SiO2 or SiN type, etc . ) . According to an alternative of this case
(figures 4F and 4G) , the substrate 2 comprises in fact a transparent surface layer 2' wherein the marks 20 are going to be made. After assembly with the substrate 4 and elimination of the portion of the substrate 2 located above the transparent layer and above the marks 20, the structure in figure 4G is obtained. The transparent nature of the layer 2' makes it possible to locate or to visualise the marks, without there being a need to remove the transparent layer 2' .
In the case where a surface layer 2' would not be transparent is in fact that which is already described hereinabove in liaison with figures 4A - 4E: the portion of the layer 2' that masks the marks must then be eliminated.
In the second case (shown in figures 5A - 5E), the alignment mark(s) 60 are made in an intermediary layer 6, which may be transparent, present on the surface of the donor substrate 2, as for example a layer of silicon oxide, or of silicon nitride, or of polysilicon . The alignment marks 60 are made in the layer
6 according to the same techniques as those described in the first embodiment (figures IA - IE and figures 2A - 2B) .
The patterns 60 can be filled with a material, for which examples have already been given hereinabove .
Here again, the material removal step is applied after bringing into contact (figure 5C) the two substrates, or rather the layer 6 and of the substrate 4. A removal of material is performed in the substrate 2, more preferably above the strongly bonded zones, in order to properly suppress the weakly bonded peripheral zones, for the same reasons as those already mentioned hereinabove. If two sub-steps are used, in a first sub- step of thinning, a certain thickness h' is removed (for example in order to leave a remaining thickness between 10 μm and 100 μm) from the edge of the donor substrate 2, either locally, or over the entire periphery of the substrate. It is also possible to performe a local removal, combined with a removal over the entire periphery of the substrate.
After this sub-step, there remains the edges 12 of the substrate 2. The marks 60 are positioned in the layer 6, under these edges. A second sub-step of thinning or of routing
(figure 5E) makes it possible to suppress the remaining thickness 12 of the donor substrate 2, until the layer 6 and the pattern (s) 60 are reached and made to appear. This step makes it possible to find the patterns 60 again that have been hidden subsequent to the bonding of the donor substrate 2 with the substrate 4. The patterns 60 then appear in the layer 6 formed on the substrate 4.
For this second sub-step, a chemical attack can be implemented. In this case, the chemistry applied is more preferably selective between on the one hand the material of the donor substrate 2 to be etched and on the other hand the material of the layer 6 and that of the marks 60. In other words, this chemical steps makes it possible to attack the material of the substrate 2, but without attacking, or by attacking much less, the materials of the layer 6 and of the marks 60 (the ratio (etching rate of the material of the substrate 2/etching rate of the material of the layer 6) is for example greater than 10, typically of a magnitude of 1000; and the same for the ratio (etching rate of the material of the substrate 2/etching rate of the material of the marks 60)) . The chemical etching is for example a dry or wet etching (for example TMAH or KOH) . According to an alternative of this case
(figures 5F and 5G) , the substrate 2 comprises in fact a transparent surface layer 2' whereon the layer 6 is made: it is in the latter that the marks 60 shall be made. After assembly with the substrate 4 and elimination of the portion of the substrate 2 located on top of the transparent layer and on top of the marks 60, the structure in figure 5G is obtained. The transparent nature of the layer 2' makes it possible to locate the marks. In the case where a surface layer 2' would not be transparent is in fact that which is already described hereinabove in liaison with figures 5A - 5E : the portion of the layer 2' that masks the marks must then be eliminated. Regardless of the embodiment of the invention, the removal of material can be carried out over the entire periphery of a substrate and/or locally.
Thus, figures 6A and 6B show, as a top view, two different configurations, with marks 100, 100' : - figure 6A corresponds to the case of a removal of material over the entire periphery of the wafer; the thinning is then a routing,
- figure 6B corresponds to the case of a removal of material, local as well as over the entire periphery (routing) of the wafer, More specifically, the material removal process can be performed either before, or after the step of thinning, intended to reduce the thickness of the donor substrate 2. According to a preferred embodiment, the peripheral material is removed before the step of thinning of the rest of the wafer to the desired thickness in order to avoid creating weakly bonded zones.
It is also possible to carry out a partial removal of material from the substrate 2, along its thickness, before assembling with the substrate 4. If this prior partial removal is not carried out over the entire outside edge of the substrate 2, it can be sought, during the putting into contact of the two substrates 2, 4 to align the zones of the substrate 2 which are thinned beforehand with the marks of the substrate 4.
Regardless of the embodiment considered, several uses of the multilayer substrate obtained are possible.
As such, after the step making it possible to have the marks or the patterns 10, 20, 60 appear, the multilayer structure can be used such as for the manufacture of electronic, and/or optical and/or other components.
According to another application, the donor substrate 2 can be thinned according to the conventional techniques (polishing, and/or chemical attack) . According to yet another application, in the donor substrate 2, prior to its assembly or bonding with the substrate 4, a weakened plane was formed, for example by a step of atomic or ionic implantation (helium and/or hydrogen for example) . This results, after assembling with the substrate 4 and revealing of the marks 10, 20, 60, in one of the structures shown in figures 7A, 7B, 7C, respectively for the first embodiment and for the two cases considered for the second embodiment. In these 3 figures, the reference 18 designates the weakened plane (or defect plane) resulting from the implantation carried out in the donor substrate 2.
By a process of the "Smart CutTM" type a splitting can then be carried out along this weakened plane. This results in a thinned donor substrate 2' (figures 8A, 8B, 8C) .
In this thinned substrate, electronic, and/or optical and/or other components can for example be made .
One (or several) new layer (s) 100, 100', 200, 200', 600, 600' (figures 9A, 9B, 9C) can also, or as an alternative be transferred on this thinned substrate 2', for example via molecular adhesion and separation using a donor substrate, for example also by "Smart CutTM" technique or substrate splitting. During these steps, the marks 10, 20, 60 remain visible and make an alignment possible of the realised components and/or of the new transferred layer.
These processes can also be applied to the other substrates obtained in the case of alternatives of the various processs described, in particular to the substrates of figures 3D, 3E, 4G, 5G with intermediary layer 8, 2', transparent or not transparent.
The support substrate 4 can also be the object of various treatments, for example it can be thinned via different techniques (mechanical rectification, and/or polishing and/or chemical attack and/or substrate splitting) .

Claims

1. Process of forming an assembly of at least two substrates with at least one alignment mark, comprising the following steps: a) a step of forming of at least one alignment mark (10, 20, 60) on or in a first substrate (2, 4) or on or in a layer (50', 6) formed on this substrate, b) a first assembling step of assembling said first substrate, or of a layer (50', 6, 8) formed on said first substrate, with a second substrate (4, 2) or a layer formed on said second substrate, c) a step of thinning at least one peripheral portion of at least one of the two substrates, in order to reveal at least one of said alignment marks.
2. Process according to claim 1, the step c) comprising a step of thinning of at least one peripheral portion of the first substrate.
3. Process according to claim 1, the step c) comprising a step of thinning of at least one peripheral portion of the second substrate.
4. Process according to one of claims 1 to 3, at least one transparent layer (2', 8) being formed on the first and/or the second substrate, before the step b) . 2 \
5. Process according to one of claims 1 to 3, a layer (6) of silicon oxide, or of silicon nitride, or of polysilicon being formed on the first substrate.
6. Process according to one of claims 1 to 5, the two substrates being assembled by molecular adhesion .
7. Process according to one of claims 1 to 6, the mark(s) being made via direct chemical etching of the first substrate and/or of a layer (50', 6) formed on this first substrate, or through a layer (50) formed on the first substrate.
8. Process according to one of claims 1 to 7, the first substrate being, after step c) , subjected to a thinning step.
9. Process according to one of claims 1 to 7, the first substrate being, after step c) , detached by substrate splitting or fracture.
10. Process according to one of claims 1 to 9, the step c) comprising a first sub-step of thinning, that leaves the marks buried, then a second sub-step of thinning, that reveals the alignment mark(s) .
11. Process according to claim 10, the first sub-step being performed mechanically.
12. Process according to claim 10 or 11, the second sub-step being performed chemically.
13. Process according to claim 12, the sub- step of chemical thinning being selective in relation to material of the alignment mark(s) and/or to the material of the first substrate and/or to the material of a layer (50', 6, 2') formed on the first substrate.
14. Process according to one of claims 10 to
13, the first sub-step of thinning enabling to leave a substrate thickness between 100 μm and 10 μm, the second sub-step of thinning enabling to leave a thickness smaller than 10 μm or 20 μm.
15. Process according to one of claims 1 to
14, the step c) being carried out in order to suppress the peripheral zones that are weakly assembled and to eliminate a portion of the strongly assembled zones.
16. Process according to one of claims 1 to
15, the step c) being a step of material removing, locally and/or over the entire periphery of the thinned substrate .
17. Process according to one of claims 1 to
16, the first or the second substrate being made of semiconductor, for example of silicon, or of SiC, or of p-SiC, or of Ge, or of GaN or of a semiconductor of the III V, II VI kind, or being made of piezoelectric, or pyroelectric or ferroelectric material, the other substrate being made of Si, or of glass, or of quartz, or of sapphire, or of a material of the III V or II VI kind, or of a ceramic.
18. Process according to one of claims 1 to
17, the alignment mark(s) being located at a distance d, d' from the first substrate comprised between 1 mm and 5 mm of the edge of said substrate.
19. Process according to one of claims 1 to
18, the alignment mark(s) having a width 1, in the plane of the substrate or of the layer wherein they are formed, between 10 μm or 50 μm and 500 μm or 1 mm.
20. Process of manufacturing a stack of at least three layers or substrates, provided with at least one alignment mark, comprising: a process of forming an assembly of at least two substrates with at least one alignment mark, according to one of claims 1 to 19,
- assembling these at least two substrates with at least one third substrate (200, 200', 300, 300', 600, 600' ) .
21. Process according to claim 20, the assembly with at least one third substrate (200, 200', 300, 300', 600, 600') being an assembly via molecular bonding.
PCT/EP2008/067652 2007-12-18 2008-12-16 Process of assembly with buried marks WO2009077538A2 (en)

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FR0759944A FR2925223B1 (en) 2007-12-18 2007-12-18 METHOD FOR ASSEMBLING WITH ENTERED LABELS
FR0759944 2007-12-18

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WO2009077538A2 true WO2009077538A2 (en) 2009-06-25
WO2009077538A3 WO2009077538A3 (en) 2009-08-27

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102214594A (en) * 2010-04-06 2011-10-12 硅绝缘体技术有限公司 Method for manufacturing a semiconductor substrate
US8223582B2 (en) 2010-04-02 2012-07-17 Soitec Pseudo-inverter circuit on SeOI
US8304833B2 (en) 2010-01-14 2012-11-06 Soitec Memory cell with a channel buried beneath a dielectric layer
US8305803B2 (en) 2010-01-14 2012-11-06 Soitec DRAM memory cell having a vertical bipolar injector
US8325506B2 (en) 2010-01-14 2012-12-04 Soitec Devices and methods for comparing data in a content-addressable memory
US8358552B2 (en) 2010-03-11 2013-01-22 Soitec Nano-sense amplifier
US8384425B2 (en) 2009-12-08 2013-02-26 Soitec Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate
US8432216B2 (en) 2010-03-03 2013-04-30 Soitec Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
US8455938B2 (en) 2010-04-22 2013-06-04 Soitec Device comprising a field-effect transistor in a silicon-on-insulator
US8508289B2 (en) 2009-12-08 2013-08-13 Soitec Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
US8575697B2 (en) 2010-03-08 2013-11-05 Soitec SRAM-type memory cell
US8664712B2 (en) 2009-12-08 2014-03-04 Soitec Flash memory cell on SeOI having a second control gate buried under the insulating layer
US9490264B2 (en) 2010-01-14 2016-11-08 Soitec Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device
US9640621B2 (en) 2012-06-29 2017-05-02 Corning Incorporated Glass-ceramic substrates for semiconductor processing

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
EP1081748A2 (en) * 1999-08-30 2001-03-07 Lucent Technologies Inc. Etch stops and alignment marks for bonded wafers
FR2848725A1 (en) * 2002-12-17 2004-06-18 Commissariat Energie Atomique Formation of patterns aligned either side of thin film, for production of three-dimensional components and micro-systems such as memory numeric circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
EP1081748A2 (en) * 1999-08-30 2001-03-07 Lucent Technologies Inc. Etch stops and alignment marks for bonded wafers
FR2848725A1 (en) * 2002-12-17 2004-06-18 Commissariat Energie Atomique Formation of patterns aligned either side of thin film, for production of three-dimensional components and micro-systems such as memory numeric circuits

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384425B2 (en) 2009-12-08 2013-02-26 Soitec Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate
US8664712B2 (en) 2009-12-08 2014-03-04 Soitec Flash memory cell on SeOI having a second control gate buried under the insulating layer
US8508289B2 (en) 2009-12-08 2013-08-13 Soitec Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
US9490264B2 (en) 2010-01-14 2016-11-08 Soitec Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device
US8304833B2 (en) 2010-01-14 2012-11-06 Soitec Memory cell with a channel buried beneath a dielectric layer
US8305803B2 (en) 2010-01-14 2012-11-06 Soitec DRAM memory cell having a vertical bipolar injector
US8325506B2 (en) 2010-01-14 2012-12-04 Soitec Devices and methods for comparing data in a content-addressable memory
US8432216B2 (en) 2010-03-03 2013-04-30 Soitec Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
US8575697B2 (en) 2010-03-08 2013-11-05 Soitec SRAM-type memory cell
US8625374B2 (en) 2010-03-11 2014-01-07 Soitec Nano-sense amplifier
US8358552B2 (en) 2010-03-11 2013-01-22 Soitec Nano-sense amplifier
US8654602B2 (en) 2010-04-02 2014-02-18 Soitec Pseudo-inverter circuit on SeOI
US8223582B2 (en) 2010-04-02 2012-07-17 Soitec Pseudo-inverter circuit on SeOI
CN102214594A (en) * 2010-04-06 2011-10-12 硅绝缘体技术有限公司 Method for manufacturing a semiconductor substrate
US9035474B2 (en) 2010-04-06 2015-05-19 Soitec Method for manufacturing a semiconductor substrate
CN102214594B (en) * 2010-04-06 2015-11-18 硅绝缘体技术有限公司 For the manufacture of the method for Semiconductor substrate
US8455938B2 (en) 2010-04-22 2013-06-04 Soitec Device comprising a field-effect transistor in a silicon-on-insulator
US9640621B2 (en) 2012-06-29 2017-05-02 Corning Incorporated Glass-ceramic substrates for semiconductor processing

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WO2009077538A3 (en) 2009-08-27
FR2925223B1 (en) 2010-02-19

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