WO2009077538A3 - Process of assembly with buried marks - Google Patents
Process of assembly with buried marks Download PDFInfo
- Publication number
- WO2009077538A3 WO2009077538A3 PCT/EP2008/067652 EP2008067652W WO2009077538A3 WO 2009077538 A3 WO2009077538 A3 WO 2009077538A3 EP 2008067652 W EP2008067652 W EP 2008067652W WO 2009077538 A3 WO2009077538 A3 WO 2009077538A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- assembly
- layer formed
- buried
- marks
- Prior art date
Links
- 239000000758 substrate Substances 0.000 abstract 8
- 230000002093 peripheral effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/002—Aligning microparts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/05—Aligning components to be assembled
- B81C2203/051—Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention relates to a process of forming an assembly of at least two substrates with at least one alignment mark, comprising the following steps: a) a step of forming of at least one alignment mark (10) on or in a first substrate (4) or a layer formed on this substrate, b) a first step of assembly of this first substrate, or of a layer formed on this first substrate, with a second substrate (2) or a layer formed on this second substrate, c) a step of thinning of at least a peripheral portion of at least one of the two substrates, in order to have at least one of said alignment marks appear.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0759944A FR2925223B1 (en) | 2007-12-18 | 2007-12-18 | METHOD FOR ASSEMBLING WITH ENTERED LABELS |
FR0759944 | 2007-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009077538A2 WO2009077538A2 (en) | 2009-06-25 |
WO2009077538A3 true WO2009077538A3 (en) | 2009-08-27 |
Family
ID=39616549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2008/067652 WO2009077538A2 (en) | 2007-12-18 | 2008-12-16 | Process of assembly with buried marks |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2925223B1 (en) |
WO (1) | WO2009077538A2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8508289B2 (en) | 2009-12-08 | 2013-08-13 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
FR2957193B1 (en) | 2010-03-03 | 2012-04-20 | Soitec Silicon On Insulator | SEOI SUBSTRATE DATA PATH CELL WITH REAR CONTROL GRID BURED UNDER THE INSULATING LAYER |
FR2953641B1 (en) | 2009-12-08 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | HOMOGENEOUS TRANSISTOR CIRCUIT ON SEOI WITH REAR CONTROL CHANNEL BURED UNDER THE INSULATING LAYER |
FR2953643B1 (en) | 2009-12-08 | 2012-07-27 | Soitec Silicon On Insulator | MEMORY CELL FLASH ON SEOI HAVING A SECOND CHECK GRID ENTERREE UNDER THE INSULATING LAYER |
FR2955195B1 (en) | 2010-01-14 | 2012-03-09 | Soitec Silicon On Insulator | DEVICE FOR COMPARING DATA IN A MEMORY ADDRESSABLE BY CONTENT ON SEOI |
FR2955204B1 (en) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR |
FR2955203B1 (en) | 2010-01-14 | 2012-03-23 | Soitec Silicon On Insulator | MEMORY CELL WITH THE CHANNEL CROSSING A DIELECTRIC LAYER ENTERREE |
FR2955200B1 (en) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | DEVICE AND MANUFACTURING METHOD HAVING CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH AN INSULATED INSULATED LAYER |
FR2957186B1 (en) | 2010-03-08 | 2012-09-28 | Soitec Silicon On Insulator | MEMORY CELL OF SRAM TYPE |
FR2957449B1 (en) | 2010-03-11 | 2022-07-15 | S O I Tec Silicon On Insulator Tech | READOUT MICRO-AMPLIFIER FOR MEMORY |
FR2958441B1 (en) | 2010-04-02 | 2012-07-13 | Soitec Silicon On Insulator | PSEUDO-INVERTER CIRCUIT ON SEOI |
EP2375442A1 (en) * | 2010-04-06 | 2011-10-12 | S.O.I.Tec Silicon on Insulator Technologies | Method for manufacturing a semiconductor substrate |
EP2381470B1 (en) | 2010-04-22 | 2012-08-22 | Soitec | Semiconductor device comprising a field-effect transistor in a silicon-on-insulator structure |
EP2867177A1 (en) | 2012-06-29 | 2015-05-06 | Corning Incorporated | Glass-ceramic substrates for semiconductor processing |
FR3028257A1 (en) | 2014-11-10 | 2016-05-13 | Tronic's Microsystems | METHOD FOR MANUFACTURING AN ELECTROMECHANICAL DEVICE AND CORRESPONDING DEVICE |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5869386A (en) * | 1995-09-28 | 1999-02-09 | Nec Corporation | Method of fabricating a composite silicon-on-insulator substrate |
EP1081748A2 (en) * | 1999-08-30 | 2001-03-07 | Lucent Technologies Inc. | Etch stops and alignment marks for bonded wafers |
FR2848725A1 (en) * | 2002-12-17 | 2004-06-18 | Commissariat Energie Atomique | Formation of patterns aligned either side of thin film, for production of three-dimensional components and micro-systems such as memory numeric circuits |
-
2007
- 2007-12-18 FR FR0759944A patent/FR2925223B1/en not_active Expired - Fee Related
-
2008
- 2008-12-16 WO PCT/EP2008/067652 patent/WO2009077538A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5869386A (en) * | 1995-09-28 | 1999-02-09 | Nec Corporation | Method of fabricating a composite silicon-on-insulator substrate |
EP1081748A2 (en) * | 1999-08-30 | 2001-03-07 | Lucent Technologies Inc. | Etch stops and alignment marks for bonded wafers |
FR2848725A1 (en) * | 2002-12-17 | 2004-06-18 | Commissariat Energie Atomique | Formation of patterns aligned either side of thin film, for production of three-dimensional components and micro-systems such as memory numeric circuits |
Also Published As
Publication number | Publication date |
---|---|
FR2925223B1 (en) | 2010-02-19 |
FR2925223A1 (en) | 2009-06-19 |
WO2009077538A2 (en) | 2009-06-25 |
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