EP1060518A1 - Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effa ables electriquement, et son procede de production - Google Patents

Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effa ables electriquement, et son procede de production

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Publication number
EP1060518A1
EP1060518A1 EP99911574A EP99911574A EP1060518A1 EP 1060518 A1 EP1060518 A1 EP 1060518A1 EP 99911574 A EP99911574 A EP 99911574A EP 99911574 A EP99911574 A EP 99911574A EP 1060518 A1 EP1060518 A1 EP 1060518A1
Authority
EP
European Patent Office
Prior art keywords
source
trench
drain region
mos transistor
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99911574A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Josef Willer
Wolfgang Krautschneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1060518A1 publication Critical patent/EP1060518A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the invention relates to a MOS transistor that is suitable for integration in a circuit arrangement with transistors of another technology, so-called embedded MOS transistor, and a method for its production.
  • transistors with very different properties are required at the same time, which can be produced in different technologies.
  • An example of this are EEPROM applications in which MOS transistors with floating gate and control gate, which are operated with voltages of a maximum of 5 volts, are used as storage transistors and in which so-called high-voltage transistors, which have higher voltages, are used for programming the storage transistors , in particular 10 to 20 volts, switch. Smart power circuits are further examples of such applications.
  • the invention is based on the object of specifying a MOS transistor which can be produced simultaneously with transistors of another technology without adversely affecting the properties of the transistors of the other technology. rivers.
  • a method for producing such a MOS transistor is also to be specified.
  • the MOS transistor comprises a first source / dram device and a second source / dram device which are arranged in a semiconductor substrate.
  • a monocrystalline silicon substrate or the monocrystalline silicon layer of an SOI substrate are particularly suitable as the semiconductor substrate.
  • a trench is arranged between the first source / dram area and the second source / dram area, the depth of which is greater than the depth of the first source / dram area and the second source / dram area.
  • the surface of the trench is provided with a gate dielectric.
  • a gate electrode is arranged in the trench, the extent of which in the direction of the depth of the trench is at most equal to the depth of the trench.
  • the MOS transistor has a channel region which is arranged between the first source / dram region and the second source / dram region and runs in the semiconductor substrate along the surface of the trench. When the transistor is switched, a current path along the surface of the trench is therefore closed or interrupted.
  • An isolation trench is provided which surrounds the MOS transistor.
  • the isolation trench is provided with an insulating filling and has a depth which essentially corresponds to the depth of the trench.
  • the isolation trench is preferably opened at the same time as the trench. No additional photo technology is therefore required for the trench etching.
  • the gate oxide and the gate electrode are arranged completely in the trench and the channel region arranged along the surface of the trench, this MOS transistor can be produced before the production of transistors of other technology. It is within the scope of the invention that the gate electrode completely fills the trench or that a planing structure fills the trench above the gate electrode. After the production of the MOS transistor, the semiconductor substrate has a flat surface and is suitable for the production of the other transistors in a different technology.
  • the MOS transistor is particularly suitable as a high-voltage transistor for an EEPROM arrangement. Since the channel area runs along the surface of the trench, the space requirement of the MOS transistor is reduced in comparison with a pianar MOS transistor. The higher thickness of the gate dielectric required for high-voltage transistors in comparison to the memory transistors has no effect on the memory transistors, since the gate dielectric is only arranged on the surface of the trench. The channel implantation for the high-voltage transistor also only affects the trench surface.
  • the MOS transistor can be designed both as an n-channel MOS transistor and as a p-channel MOS transistor.
  • the MOS transistor as an n-channel MOS transistor is an n + -doped gate electrode and as a p-channel MOS transistor is a p + -dot ⁇ erte Has gate electrode.
  • both the n-channel MOS transistor and the p-channel MOS transistor are so-called surface-channel transistors, with which a conductive channel is formed on the interface of the substrate to the gate dielectric .
  • the MOS transistor As a high-voltage MOS transistor, it is advantageous to provide a first diffusion region which is arranged between the first source / dram device and the channel region and which is connected to the first source / Drain area and adjacent to the channel area.
  • the first diffusion region is doped with the same conductivity type as the first source / drain region, it has a lower dopant concentration than the first source / drain region.
  • a portion of the voltage present between the first source / drain region and the second source / drain region drops across the first diffusion region, so that only a lower voltage has to be switched across the channel region.
  • the first diffusion region at least partially below the first source / drain region. In this way, the space requirement parallel to the surface of the semiconductor substrate is reduced.
  • the MOS transistor is preferably designed such that the first source / drain region does not directly adjoin the surface of the trench. This increases the dielectric strength between the gate electrode and the first source / drain region. In particular, voltage peaks and a band-to-band tunnel at the edge of the gate electrode are avoided.
  • This configuration of the MOS transistor can be realized in that the first diffusion region is arranged at least partially between the surface of the trench and the first source / drain region. In this way, since the first diffusion region acts as a resistance, over which part of the voltage drops, the voltage effective at the edge of the trench is reduced.
  • this embodiment is realized in that a first insulation structure is provided, which is arranged between the gate electrode and the first source / drain region.
  • the first insulation structure thus adjoins the surface of the semiconductor substrate and has a depth that is greater than the depth of the first source / drain Area. In this way, the insulation between the gate electrode and the first source / dram device, to which high voltage is applied, is improved.
  • a second diffusion region which is doped with the same conductivity type as the second source / drain region, but which has a lower dopant concentration than the second source / dram region, and that is arranged between the second source / dram Geb ⁇ et and the channel area.
  • the second diffusion area borders both on the second source / dram area and on the channel area.
  • the second diffusion area is constructed analogously to the first diffusion area.
  • the MOS transistor has a symmetrical structure. Both the first source / dram device and the second source / dram device can be connected as a drain in a circuit. This facilitates the circuit design.
  • FIG. 1 shows a section through a MOS transistor with a gate electrode arranged in a trench.
  • FIG. 2 shows a section through a MOS transistor with a gate electrode arranged in a trench and a first source / dram device and a second source / dram device, under each of which a first diffusion area or a second diffusion area is arranged.
  • FIG. 3 shows a section through a MOS transistor with a gate electrode arranged in a trench and a first source / dram device and a second one
  • Source / Dram Geb ⁇ et each by a first Diffusion area or a second diffusion area are separated from the surface of the trench.
  • FIG. 4 shows a section through a MOS transistor with a gate electrode arranged in a trench, a first insulation structure being provided between the gate electrode and a first source / drain region and between the gate electrode and a second source / drain - Area is arranged.
  • MOS transistor with a first insulation structure which is arranged between a first source / drain region or a second source / drain region and a gate electrode.
  • MOS transistor with a gate electrode arranged in a trench and a first source / drain region and a second source / drain region which are spaced apart from the surface of the trench.
  • FIGS. 13 to 16 show steps for producing a MOS transistor with a gate electrode arranged in the trench and a first source / drain region and a second source / drain region, each through a first diffusion region and a second diffusion region are spaced from the surface of the trench.
  • a substrate 11 of monocrystalline p-doped silicon with a basic doping of 10 ⁇ 5 cm -3 j_ s -j- e i ne p-doped well 12 is disposed (see Figure 1).
  • the p-doped well 12 has a dopant concentration of 10 17 cm ⁇ 3.
  • the p-doped well 12 is surrounded by an isolation trench 13, which has an SiO 2 layer 131 and an SiO 2 layer Filling 132 is filled.
  • the isolation structure 13 is produced using the shallow trench isolation technique.
  • a trench 14 is arranged within the area surrounded by the insulation structure 13 and extends to the p-doped well 12 up to m.
  • the depth of the trench 14 is 400 nm.
  • the depth of the isolation trench 13 is also 400 nm.
  • the surface of the trench 14 is provided with a gate dielectric 15.
  • the gate dielectric 15 contains S1O2 and has a thickness of 20 n.
  • the trench 14 is filled with a gate electrode 16 made of n + -doped polysilicon.
  • the trench 14 filled with the gate dielectric 15 and the gate electrode 16 forms a flat surface with the substrate 11.
  • a first source / dram unit 171 and a second source / dram unit 172 are provided, each of which adjoins the isolation trench 13.
  • the first source / dram unit 171 and the second source / dram unit 172 are n + -doped with a dopant concentration of 10 ⁇ 1 cm " ⁇ .
  • the first source / dram unit 171 and the second source / Dram area 172 has a depth of approximately 200 nm.
  • a first diffusion region 181 is arranged between the first source / drain area 171 and the surface of the trench 14. Between the second source / drain area 172 and the surface of the A second diffusion region 182 is arranged in trench 14.
  • the first diffusion region 181 and the second diffusion region 182 are each n ⁇ -doped and have a dopant concentration of 2 ⁇ 10 18 cm -3 .
  • the channel region acts on the surface of the trench below part of the p-doped well 12 of the first diffusion region 181 and the second diffusion region 182.
  • contacts 120 to the first source / dram device 171, the second Source / Dram Geb ⁇ et 172 and the gate electrode 16 are provided.
  • the contacts 120 contain aluminum and / or tungsten.
  • a p-doped well 22 having a dopant concentration of 10 17 cm -3 (see Figure 2).
  • An active area for a MOS transistor is defined by an isolation trench 23, which is annular.
  • the isolation trench 23 is filled with a layer 231 and a layer 232 232 in the sense of shallow trench insulation.
  • the depth of the isolation trench 23 is 600 nm.
  • a trench 24, the depth of which is also 600 nm, is arranged in the active region.
  • the surface of the trench 24 is provided with a gate dielectric 25.
  • the gate dielectric 25 contains S1O2 and has a thickness of 25 nm.
  • the trench 24 is filled with a gate electrode 26.
  • the gate electrode 26 contains n + -doped polysilicon with a dopant concentration of 10 ⁇ 1 cm -3
  • a first source / drain device 271 and a second source / dram device 272 are arranged, each of which adjoins the surface of the substrate.
  • the first source / dram region 271 and the second source / dram region 272 are n + -doped with a dopant concentration of 10 ⁇ ° cm -3.
  • the first source / dram region 272 and the second source / Dram-Geb ⁇ et 272 each have a depth of 200 nm.
  • a first diffusion region 281 is arranged below the first source / dram region 271, which is n ⁇ -doped with a dopant concentration of 10 ⁇ - 8 cm -3 and which has a depth of 500 nm measured from the surface of the substrate 21 .
  • the first source / dram device 271 is connected as a drain in the MOS transistor. A portion of the voltage applied to the first source / dram region 271 then drops across the first diffusion region 281. A lower voltage then drops across the channel region, which is formed by that part of the p-dot well 22 which adjoins the surface of the trench 24.
  • An insulation layer 29 made of doped glass is arranged on the surface of the structure, in which contacts 220 are provided to the first source / dram region 271, the second source / drain region 272 and the gate electrode 26 (see FIG. 2).
  • a p-doped well 32 is disposed with a dopant concentration of 10 17 cm -3 (see Figure 3).
  • An active region for a MOS transistor is defined in the p-doped well 32 by an annular isolation trench 33.
  • the isolation trench 33 is filled with a Si2 layer 331 and a Si2 filling 332.
  • the depth of the isolation trench 31 is 800 nm.
  • a trench 34 is arranged within the active region.
  • the surface of the trench 34 is provided with a gate dielectric 35 which
  • the trench 34 is filled with a gate electrode 36 made of n + -doped polysilicon with a dopant concentration of l ⁇ 21 C m ⁇ 3 .
  • first source / drain unit 371 There are a first source / drain unit 371 and a second one
  • Source / Dram Geb ⁇ et 372 provided, each adjoining the surface of the isolation trench 33 and the 10
  • the source / drain regions 371, 372 are n + -doped and have a dopant concentration of 10 ⁇ 1 cm -3 . They have a depth of 200 nm. They are spaced from the surface of the trench 34 by a first diffusion region 381 or a second diffusion region 382. The first diffusion region 381 and the second diffusion region 382 also extend below the first source / dram region 371 and the second source / dram region 372. The first diffusion region 381 and the second diffusion region 382 are each n ⁇ - dyes with a dopant concentration of 10 ⁇ cm "" 3 . The diffusion regions 381, 382 have a depth of 400 nm measured from the surface of the semiconductor substrate. The part of the p-doped well 32 which adjoins the surface of the trench 34 acts as the channel region in the MOS transistor.
  • the structure is also provided with an insulation layer 39 made of doped glass, in which contacts 320 are provided to the first source / dram region 371, the second source / dram region 372 and the gate electrode 36.
  • a p-doped trough 42 with a dopant concentration of 10 17 cm -3 is arranged in a substrate 41 with a basic doping of 10 ⁇ cm -3 boron (see FIG. 4).
  • Trench insulation is filled with a Si2 layer 431 and a S1O2 filling 432, defines an active area for a MOS transistor.
  • the depth of the isolation trench 43 is 800 nm.
  • a trench 44 is arranged in the active area, the depth of which is also 800 nm.
  • the trench 44 has an expansion which is provided with an insulation structure 441.
  • the insulation structure 441 which contains S1O2
  • the surface of the trench 44 is provided with a gate dielectric 45.
  • the gate dielectric 45 contains S1O2 and has one 11
  • the trench 44 is filled with a gate electrode 46 made of n + -doped polysilicon with a dopant concentration of 10 21 cm -3 .
  • the gate electrode 46 terminates at the height with the substrate 41.
  • a first source / drain device 471 and a second source / drain device 472 are arranged between the insulation structure 441 and the Si2 filling 432 of the isolation trench 43.
  • the source / dram units 471, 472 are n + -doped and have a dopant concentration of 10 2 1 cm -3 . They have a depth of 200 nm.
  • a first diffusion region 481 and a second diffusion region 482 are arranged below the first source / drain region 471 and the second source / drain region 472.
  • the first diffusion region 481 and the second diffusion region 482 are each n ⁇ -doped and have a dopant concentration of 10 ⁇ 8 cm -3 . Measured from the surface of the substrate 41, they have a depth of 500 nm.
  • the isolation structure 441 has a depth of 300 nm.
  • the width of the insulation structure 441 is dimensioned such that the distance of the first source / drain device 471 or the second source / dram device 472 from the gate electrode 46 is 100 nm parallel to the surface of the substrate 41. This improves the dielectric strength of the MOS transistor.
  • the part of the p-doped well 42 adjacent to the surface of the trench 44 acts as the channel region.
  • the structure also has an insulation layer 49 made of doped glass, in which contacts 420 are provided to the first source / dram device 471, the second source / dram device 472 and the gate electrode 46.
  • a substrate 51 made of monolithic silicon with a basic doping of 10 ⁇ cm ⁇ 3 boron is replaced by a number of 12
  • Implantations with boron with 3 x 10 ⁇ cm -2 , 500 keV or 5 x 10 12 cm -2 , 200 keV formed a p-doped well 52 with a dopant concentration of 10 ⁇ - 7 cm -3 and a depth of 1000 nm (see Figure 5).
  • a photolithographically generated resist mask (not shown) is used.
  • a diffusion region 53 which has a dopant concentration of 10 18 cm -3 and a depth of 500 nm, is subsequently produced by implantations with phosphorus with an energy of 100 keV, 200 keV and a dose of 8 ⁇ 10 ⁇ 2 cm -2 each having.
  • a first layer 54 is applied with a thickness of 20 nm and a silicon nitride layer 55 m with a thickness of 100 nm.
  • First trenches 56 are etched using a photolithographically generated mask (not shown).
  • the first trenches 56 have a depth of 300 nm.
  • the first trenches 56 have an annular part and a web that connects opposite sides of the annular part to one another.
  • CHF3, 02 of the first silicon layer 54 is used CHF3, O2 and the silicon HBr, He, O2, NF3 is used.
  • the first trenches 56 are filled with a first SiO 2 filling 57.
  • a layer of SiO 2 is deposited and planed by chemical-mechanical polishing.
  • second trenches are etched using a photoresist mask (not shown).
  • the second trenches comprise a trench 58 and an isolation trench 59 (see FIG. 6). Both the trench 58 and the isolation trench 59 are arranged parallel to the surface of the substrate 51 within the cross section of the first trench 56.
  • the cross section of the trench 58 and the isolation trench 59 is in each case smaller than the cross section of the corresponding part of the first trench 56.
  • the depth of the trench 58 and the isolation trench 59 is greater than that of the first trench 13
  • the depth of the trench 58 and the isolation trench 59 is approximately 800 nm.
  • the trench 58 structures the first fill 57, so that a first insulation structure 571 is formed, which is arranged in the upper region of the trench 58 on both sides of the trench 58 (see FIG. 6).
  • the dimension of the first insulation structure 571 perpendicular to the wall of the trench 58 is 100 nm.
  • a gate dielectric 5101 made of S1O2 m with a layer thickness of 25 nm is formed on the surface of the trench 58 by thermal oxidation.
  • a second SiO 2 layer 5102 m with a layer thickness of likewise 25 nm is formed on the surface of the isolation trench 59.
  • a gate electrode 5111 is formed in the trench 58 and a polysilicon fill 5112 is formed in the isolation trench 59.
  • the gate electrode 5111 is n + -doped with a dopant concentration of 10 21 cm "" 3 .
  • the doped polysilicon layer is formed by in situ doped deposition or by undoped deposition and subsequent implantation.
  • the doped polysilicon layer is etched back to the extent that the gate electrode
  • 5111 is flush with the surface of the substrate 51.
  • the polysilicon filling is made with the aid of He, HBr, CI2, C2Fg
  • the insulation trench 59 is filled with a second SiO 2 filling 513 by depositing an SiO 2 layer and chemical-mechanical polishing (see FIG. 8). The silicon nitride layer 55 and the first SiO 2 layer 54 are then removed. This creates a flat surface of the structure.
  • the MOS transistor is formed by forming a first source / drain region 5141 and a second source / drain region 5142 with the aid of a masked implantation of arsenic at an energy of 60 keV and a dose of 5 ⁇ 10 ⁇ - cm - 2 completed.
  • the depth of the source / drain regions 5141, 5142 is 200 nm. It is therefore less than the depth of the first insulation structure 571.
  • the less doped diffusion regions 52 are arranged below the source / drain regions 5141, 5142. Parts of the p-doped well 52 adjacent to the surface of the trench 58 form the channel region.
  • the process for manufacturing the memory transistors and peripheral transistors is carried out before the implantation to form the source / drain regions 5141, 5142. Since both the gate electrode 5111 and the gate dielectric 5101 are buried in the trench 58 and the structure has a flat surface, these structures do not influence the process flow for the memory transistors and the peripheral transistors.
  • a p-doped well 62 with a dopant concentration of 10 ⁇ 7 cm -3 is formed by masked implantation with boron in a substrate 61 made of monocrystalline silicon with a basic doping of l ⁇ l5 C m -3 boron.
  • the depth of the p-doped well 62 is 1000 nm (see FIG. 9).
  • a first S1O2 layer 63 m with a layer thickness of 20 nm and a silicon nitride layer 64 m with a layer thickness of 100 nm are applied to the surface of the substrate 61.
  • the silicon nitride layer 64, the first silicon layer 63 and the substrate 61 are structured such that a trench 65 and an isolation trench 66 with a depth of 600 nm are formed.
  • CHF3, O2, S1O2, CHF3, O2 and S1I1- zium HBr, He, O2, NF3 are used for the etching of silicon nitride.
  • the isolation trench 66 surrounds an active area in a ring shape.
  • the trench 65 has a web-shaped cross section and extends from one side of the isolation trench 66 to the opposite side.
  • the dopant concentration of the p-doped well 62 along the surface of the trench 65 is set to 10 1 7 cm -3 . This determines the threshold voltage of the MOS transistor to be manufactured.
  • the implantation is carried out with an energy of 50 keV and a dose of 2 x 10 12 cm -2 .
  • a gate dielectric 67 made of S1O2 m with a layer thickness of 25 nm is formed on the surface of the trench 65 by thermal oxidation.
  • a second layer 68 is formed on the surface of the isolation trench in a layer thickness of likewise 25 nm (see FIG. 10).
  • a gate electrode 691 and a polysilicon fill 692 are subsequently formed by forming a doped polysilicon layer and scratching the doped polysilicon layer with CF4, O2, N2.
  • the doped polysilicon layer is formed by in situ doped deposition or by undoped deposition and subsequent implantation. The jerking is continued until the surface of the gate electrode 691 is flush with the surface of the substrate 61. O 99/43029
  • the polysilicon fill 692 is removed from the isolation trench 66 by etching with He, HBr, CI2, C2F.
  • the isolation trench 66 is provided with an SiO 2 filling 610 by depositing an SiO 2 layer and chemical mechanical polishing (see FIG. 11).
  • the silicon nitride layer 64 is subsequently removed.
  • a first diffusion region 6111 with a dopant concentration of 10 18 cm "" 3 is formed by implantation with phosphorus with a dose of 4 ⁇ 10 ⁇ 2 cm -2 and an energy of 45 keV.
  • the first diffusion region 6111 has a depth of 300 nm. It is arranged on one side of the trench 65.
  • a second diffusion region 6112 is created on the opposite side of the trench 65 by implantation of phosphorus with a dose of 4 ⁇ 10 ⁇ 2 cm -2 and an energy formed by 90 keV (see Figure 12).
  • the depth of the second diffusion region 6112 is 500 nm.
  • the dopant concentration of the second diffusion region 6112 is 10 ⁇ 8 cm -3 .
  • a first source / drain region 6121 is formed within the first diffusion region 6111 and a second source / drain region 6122 is formed within the second diffusion region.
  • an implantation with arsenic is carried out at an energy of 60 keV and a dose of 5 x 10 ⁇ cm "" 2 .
  • the source / drain region 6121 and the second source / drain region 6122 each adjoin the surface of the isolation trench 66. They do not adjoin the surface of the trench 65.
  • the first source / drain region 6121 is spaced from the surface of the trench 65 by a part of the first diffusion region 6111 and the second source / drain region 6122 is spaced by a part of the second diffusion region 6112.
  • the 17 part of the p-doped well 62 adjoining the surface of the trench 65 acts as a channel region.
  • the processes for manufacturing memory transistors and peripheral transistors are carried out before the implantations to form the first diffusion region 6111.
  • tempering steps which are necessary for activating implanted dopant can be carried out simultaneously for the buried MOS transistor as well as for memory transistors and peripheral transistors.
  • a first SiO 2 layer 72 and a silicon nitride layer 73 are applied to the surface of a substrate 71
  • the substrate 71 contains monocrystalline silicon with a basic doping of 10 ⁇ cm -3 boron.
  • the first SiO 2 layer 72 is applied in a layer thickness of 20 nm and the silicon nitride layer 73 is applied in a layer thickness of 100 nm.
  • a trench 74 and an isolation trench 75 are produced by structuring the silicon nitride layer 73, the first SiO 2 layer 72 and the substrate 71.
  • anisotropic etching is used, HBr, He, O2, NF3 being used to etch the silicon nitride layer 73 CHF3, O2, the SiO2 layer 72 CHF3, O2 and the substrate 71.
  • the depth of the trench 74 measured from the surface of the substrate 71 is 400 nm.
  • the isolation trench 75 surrounds an active area for a MOS transistor in a ring shape.
  • the trench 74 is located within the active area. It has a web-shaped cross section and extends from one side of the isolation trench 75 to the opposite side.
  • transistors in another technology in particular of memory transistors of an EEPROM arrangement, can take place both before the formation of the source / drain regions and diffusion regions and after the formation of the source / drain regions and diffusion regions.
  • the threshold voltage of the MOS transistor can also be set by diffusion out of a doped layer, in particular a layer of appropriately doped glass, which is arranged on the surface of the trench.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

Selon l'invention, dans un substrat semi-conducteur (41), une tranchée (44) est placée entre une première région de source/drain (471) et une seconde région de source/drain (472). La surface de la tranchée (44) est pourvue d'un diélectrique de grille (45). Dans la tranchée (44) est disposée une électrode de grille (46) qui s'étend, dans le sens de la profondeur de la tranchée (44), au maximum sur toute cette profondeur. Le diélectrique de grille (45) et l'électrode de grille (46) sont donc enterrés dans la tranchée (44), de telle sorte que le transistor MOS peut être utilisé en tant que transistor MOS intégré, en particulier dans des systèmes de mémoires mortes programmables effaçables électriquement.
EP99911574A 1998-02-20 1999-01-27 Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effa ables electriquement, et son procede de production Withdrawn EP1060518A1 (fr)

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DE19807213 1998-02-20
DE19807213 1998-02-20
PCT/DE1999/000215 WO1999043029A1 (fr) 1998-02-20 1999-01-27 Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effaçables electriquement, et son procede de production

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EP1060518A1 true EP1060518A1 (fr) 2000-12-20

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Publication number Priority date Publication date Assignee Title
DE19957303B4 (de) * 1999-11-29 2006-05-11 Infineon Technologies Ag MOS-Transistor und Verfahren zu dessen Herstellung
GB0010041D0 (en) * 2000-04-26 2000-06-14 Koninkl Philips Electronics Nv Trench semiconductor device manufacture
GB0012138D0 (en) * 2000-05-20 2000-07-12 Koninkl Philips Electronics Nv A semiconductor device
DE10219329B4 (de) * 2002-04-30 2014-01-23 Infineon Technologies Ag Halbleiterschaltungsanordnung
DE10229065A1 (de) 2002-06-28 2004-01-29 Infineon Technologies Ag Verfahren zur Herstellung eines NROM-Speicherzellenfeldes
DE10231966A1 (de) 2002-07-15 2004-02-12 Infineon Technologies Ag Feldeffekttransistor, zugehörige Verwendung und zugehöriges Herstellungsverfahren
GB0314392D0 (en) 2003-06-20 2003-07-23 Koninkl Philips Electronics Nv Trench mos structure
EP1742270A1 (fr) 2005-07-06 2007-01-10 STMicroelectronics S.r.l. Transistor à électrode de grille en tranchée et méthode de fabrication correspondante
US7952138B2 (en) * 2007-07-05 2011-05-31 Qimonda Ag Memory circuit with field effect transistor and method for manufacturing a memory circuit with field effect transistor
FR3038774B1 (fr) * 2015-07-08 2018-03-02 Stmicroelectronics (Rousset) Sas Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant
CN109037337A (zh) * 2018-06-28 2018-12-18 华为技术有限公司 一种功率半导体器件及制造方法

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US4243997A (en) * 1976-03-25 1981-01-06 Tokyo Shibaura Electric Co., Ltd. Semiconductor device
JPS6042866A (ja) * 1983-08-19 1985-03-07 Toshiba Corp 半導体装置及びその製造方法
JPH0640583B2 (ja) * 1987-07-16 1994-05-25 株式会社東芝 半導体装置の製造方法
JPH02142140A (ja) * 1988-11-22 1990-05-31 Fujitsu Ltd 半導体装置の製造方法
JPH03129775A (ja) * 1989-07-11 1991-06-03 Seiko Epson Corp 半導体装置およびその製造方法
US5108937A (en) * 1991-02-01 1992-04-28 Taiwan Semiconductor Manufacturing Company Method of making a recessed gate MOSFET device structure
KR940002400B1 (ko) * 1991-05-15 1994-03-24 금성일렉트론 주식회사 리세스 게이트를 갖는 반도체장치의 제조방법

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TW442949B (en) 2001-06-23

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