EP1051740A1 - Procede de production d'une couche monocristalline sur un substrat sans adaptation de reseau, et composant comportant au moins une telle couche - Google Patents

Procede de production d'une couche monocristalline sur un substrat sans adaptation de reseau, et composant comportant au moins une telle couche

Info

Publication number
EP1051740A1
EP1051740A1 EP99907288A EP99907288A EP1051740A1 EP 1051740 A1 EP1051740 A1 EP 1051740A1 EP 99907288 A EP99907288 A EP 99907288A EP 99907288 A EP99907288 A EP 99907288A EP 1051740 A1 EP1051740 A1 EP 1051740A1
Authority
EP
European Patent Office
Prior art keywords
substrate
layer
implantation
defect
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99907288A
Other languages
German (de)
English (en)
Inventor
Siegfried Mantl
Bernhard HOLLÄNDER
Ralf Liedtke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Publication of EP1051740A1 publication Critical patent/EP1051740A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds

Definitions

  • the invention relates to a method for producing a single-crystalline layer on a non-lattice-matched substrate. Furthermore, the invention relates to a component containing one or more such layers according to the preamble of claim 10.
  • dislocations are built in at the interface between the layer formed and the substrate, as a result of this relaxation, - 2 - but also with a disadvantageous number of dislocations, from the interface to the layer surface (so-called threading dislocations). Since most of these dislocations continue through newly grown layers, they significantly degrade the electrical and optical properties of the layer material.
  • the object of the invention is to provide a method of the type described at the outset and a component in which the disadvantages specified above are avoided, in particular the formation of thread mg dislocations is avoided.
  • the object is achieved by a method according to the entirety of the features according to claim 1.
  • the task is further solved by a component according to the entirety of the features according to claim 10. Further expedient or advantageous embodiments or variants can be found on each of these Claims jerk-related subclaims.
  • the object is achieved according to claim 1 in that a buried, defect-rich layer is formed in the single-crystal substrate. It was recognized that the layer formed on the substrate surface is then relaxed and the formation of thread mg dislocations is prevented. It was also recognized that in this way the lattice parameter of the layer thus formed comes closer to the own lattice structure than the originally strained layer, in such a way that the quality of the deposited film does not deteriorate according to the invention through the incorporation of crystal defects. In the method according to the invention, it is also advantageously achieved that the surface roughness of the layer formed is significantly lower compared to conventionally produced layers. Finally, the degree of stress relaxation in the layer according to the invention is significantly increased in an advantageous manner. It can be advantageous to form the buried layer as close as possible to this surface without disturbing the surface structure of the substrate.
  • defect-rich layer buried beneath the substrate surface can be - 4 - implantation.
  • hydrogen can be used as the type of ion.
  • the method claimed in claim 4 provides for an advantageous, dislocation-free formation of the layer formed on the substrate surface at an implantation dose in the range from 1 * 10 14 cm “" 2 to 1 * 10 17 cm “2.
  • the ion implantation can either be before the deposition of the crystalline film or else after the deposition of the crystalline film to form the layer.
  • an ion type for implantation that is matched to the choice of substrate and film material.
  • Light ions or noble gas ions can be particularly suitable for this.
  • the method according to the invention is designed very advantageously in that the defect structure, for example in depth, can be optimized by further implantations.
  • a second implantation by means of a second type of ion favors the increase in the defect density or the increase in the gas bubble density.
  • the method according to the invention is very advantageously supplemented by an annealing treatment for the purpose of thermally induced relaxation and defect reduction.
  • the method according to the invention is not limited to the use of silicon substrates to form a buried, defect-rich layer. Rather, it may be advantageous to use one of the substrate materials listed in claim 9.
  • the component according to the invention as claimed in claim 10, 11 or 12 has the advantage that the microelectronic or optoelectronic properties required by a component can be optimally formed in the layers formed without being adversely affected or disturbed by threading dislocations.
  • the layer produced according to the invention can already be the desired end product.
  • this layer formed according to the invention forms a suitable base, for example as a buffer layer for the growth of a further layer. In this way, it forms a seed layer for the further growth of a single-crystalline film.
  • the method according to the invention for producing a relaxed, single-crystalline layer with a low dislocation density also advantageously includes the production of a buried, defect-rich layer in the substrate by means of hydrogen implantation. This light type of ion allows a precise, defined defect formation within the substrate at the desired depth.
  • Fig. 1 Schematic representation of a according to the previous Ver ⁇ drive by heteroepitaxy on non gittertationange- p motherboardtem substrate layer formed with a plurality of through the surface layer extending threading dislocations; - 6 -
  • Fig. 2 manufactured by the inventive method
  • FIG. 1 shows a layer which was produced by the previous method using heteroepitaxy on a substrate which was not matched to the lattice, with many threading dislocations running through the surface layer.
  • FIG. 2 shows a side view of the layer produced by the method according to the invention.
  • the threading dislocations shown here, which run into the substrate, do not necessarily have to arise.
  • the single-crystalline substrate which has a buried defect-rich layer, is such that the threading dislocations run into the defect-rich layer of the substrate and do not pass through the single-crystalline surface layer (the film).
  • An Si wafer was used as the substrate. Hydrogen with a dose of 1 * 10 16 cm “2 and the energy of approx. 1 keV is implanted into this substrate using a commercially available implantation system, so that a buried defect layer is formed close to the surface without defects in the uppermost atomic layers of the Si substrate.
  • the defect layer thus produced is stable up to approximately 700 ° C., ie the defects are scarcely healed up to this temperature, which enables the subsequent deposition of silicon (Si) and germanium (Ge) in a ratio of 80:20 by means of molecular steel epitaxy (MBE ) at approximately 500 ° C.
  • MBE molecular steel epitaxy
  • Si wafer was used as the substrate.
  • This commercially available substrate was cleaned - as is usual in Si epitaxy - in order to obtain a perfect and clean surface.
  • Si and Ge were then deposited at 500 ° C. in a ratio of 80:20 by means of molecular steel epitaxy (MBE).
  • MBE molecular steel epitaxy
  • the single-crystalline, only 200 nm thick surface layer thus obtained is under mechanical tension.
  • hydrogen is implanted with an implantation device with a dose of 1 • 10 16 cm ⁇ 2 .
  • the implantation energy of the H + ions is selected, for example 20 keV H + , so that the buried, defect-rich layer is formed just below the interface between the surface layer and the Si substrate.
  • Si-Ge layers thus produced can be either directly ver ⁇ turns or serve as an intermediate layer for further epitaxial growth of heterostructures and superlattices.
  • FIG. 3 shows the course of a conventionally produced layer which has surface levels in the range from 1 to 5 nm (nanometer).
  • the course of a layer produced according to the invention shown in FIG. 4 shows a significantly smoother surface without significant surface steps.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de production de couches monocristallines sur des substrats sans adaptation de réseau. On utilise à cet effet un substrat monocristallin comportant une couche enterrée riche en défauts sur laquelle est réalisée une couche monocristalline. La couche enterrée riche en défauts peut être produite par implantation d'hydrogène.
EP99907288A 1998-01-27 1999-01-27 Procede de production d'une couche monocristalline sur un substrat sans adaptation de reseau, et composant comportant au moins une telle couche Withdrawn EP1051740A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19802977A DE19802977A1 (de) 1998-01-27 1998-01-27 Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
DE19802977 1998-01-27
PCT/DE1999/000203 WO1999038201A1 (fr) 1998-01-27 1999-01-27 Procede de production d'une couche monocristalline sur un substrat sans adaptation de reseau, et composant comportant au moins une telle couche

Publications (1)

Publication Number Publication Date
EP1051740A1 true EP1051740A1 (fr) 2000-11-15

Family

ID=7855757

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99907288A Withdrawn EP1051740A1 (fr) 1998-01-27 1999-01-27 Procede de production d'une couche monocristalline sur un substrat sans adaptation de reseau, et composant comportant au moins une telle couche

Country Status (4)

Country Link
US (1) US6464780B1 (fr)
EP (1) EP1051740A1 (fr)
DE (1) DE19802977A1 (fr)
WO (1) WO1999038201A1 (fr)

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CN100465356C (zh) * 2001-06-08 2009-03-04 克利公司 高表面质量的GaN晶片及其生产方法

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Also Published As

Publication number Publication date
US6464780B1 (en) 2002-10-15
DE19802977A1 (de) 1999-07-29
WO1999038201A1 (fr) 1999-07-29

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