EP1616345A2 - Procede de production d'une couche contrainte sur un substrat, et structure en couches - Google Patents

Procede de production d'une couche contrainte sur un substrat, et structure en couches

Info

Publication number
EP1616345A2
EP1616345A2 EP04726422A EP04726422A EP1616345A2 EP 1616345 A2 EP1616345 A2 EP 1616345A2 EP 04726422 A EP04726422 A EP 04726422A EP 04726422 A EP04726422 A EP 04726422A EP 1616345 A2 EP1616345 A2 EP 1616345A2
Authority
EP
European Patent Office
Prior art keywords
layer
strained
substrate
layers
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04726422A
Other languages
German (de)
English (en)
Inventor
Siegfried Mantl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Publication of EP1616345A2 publication Critical patent/EP1616345A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Definitions

  • the invention relates to a method for producing a strained layer on a substrate, and a layer structure.
  • MOSFETs metal oxide field effect transistors
  • SOI substrates are increasingly being used.
  • Si0 2 silicon dioxide
  • MOSFETs metal oxide silicon field effect transistors
  • SOI substrates are commercially available and are either by ion implantation of oxygen in silicon and annealing (so-called SIMOX process; SIMOX wafer) or by connecting (bonding) two oxidized wafers and cleaving or etching back part of the second wafer (so-called wafer bonding process). Wafers produced in this way are referred to as BESOI wafers (bonded and back-SOI).
  • strained silicon, strained silicon-germanium alloys (Si-Ge) or silicon-carbon (Si-C) and silicon-germanium-carbon (Si-Ge-C) is also suitable.
  • silicon or Si-Ge, Si-C or Si-Ge-C in a certain elastic distortion state improves the material properties, in particular the charge carrier mobility of the electrons and holes, which is extremely important for components.
  • the use of these and other high-quality materials allows a significant increase in performance of Si-based high-performance components, such as MOSFETs and MODFETs, without having to reduce the critical structure sizes of the components.
  • Dislocations and in the relaxed layer thread dislocations that run from the surface to the interface. Misfit dislocations are required for stress relaxation, but do not degrade those above
  • the thread dislocation density becomes so high that such layers are unsuitable for components. In general, this thread dislocation density can be somewhat reduced by a temperature treatment.
  • the term dislocation density or defect density is understood here to mean the thread dislocation density. Since most of these dislocations continue through newly grown layers, they significantly degrade the electrical and optical properties of these layers. Since the silicon germanium (Si-Ge) material system is thermodynamically a completely miscible system, the connection can be made in any concentration. Silicon and germanium are characterized by the same crystal structures, but differ in the lattice parameter by 4.2%, ie that an Si-Ge layer or a pure Ge layer grows strained on silicon. Carbon can be incorporated in silicon up to approx. 2 atom% substitution part in order to reduce the lattice parameter.
  • graded layers are Si-Ge layers, the Ge concentration of which increases continuously or stepwise towards the surface until the desired Ge content is reached. Since only an increase in the Ge content of approx. 10 atom% per ⁇ m can be used to maintain the layer quality, such layers are up to 10 micrometers thick, depending on the Ge concentration reached.
  • the layer growth of this graded layer is described in E. A. Fitzgerald et al. (Thin Solid Films, 294 (1997) 3-10).
  • the interface state density at the Si / Si0 2 interface should preferably be in the range of 10 10 cm "2. Technologically, this can only be achieved with ultrapure interfaces. Whether this wafer bond -Procedure to accomplish this at all is not shown yet.
  • Layers can be created by installing a very thin (e.g. 10 nanometer) Si-C layer with a sufficiently high carbon content in a Si-Ge layer (e.g. 170 nanometer Si-Ge with 22 atom% Ge). During tempering at high temperatures of approx. 1000 ° C, the carbon present in supersaturation is eliminated. This creates defects that promote the relaxation of a Si-Ge layer.
  • the disadvantage is that this also means that no strained layer can be produced on an insulator.
  • the Surface roughness usually requires polishing.
  • a high temperature is required for relaxation, since this is determined by the excretion of the carbon and cannot be significantly reduced.
  • a method is known from WO 99/38201 which allows the production of thin stress-relieved Si-Ge powder layers by means of ion implantation and temperature treatment.
  • a disadvantage of this method is that it does not directly cover a strained layer
  • Substrate can be produced. In addition, two separate epitaxial deposits and wafer cleaning are required.
  • the object of the invention is therefore to provide a simple method for producing a tensioned layer of high quality on a substrate without wafer bonding and / or wafer polishing.
  • strained silicon is to be produced directly on an SOI wafer over the whole area or locally, in any form.
  • planarity between the braced and non-braced areas should also be ensured without the formation of steps for the further processing of components.
  • the following steps are carried out to produce a strained layer on a substrate:
  • the layer structure is subjected to at least one thermal treatment and / or an oxidation, so that dislocations are formed starting from the defects, which lead to relaxation of a layer adjacent to the straining layer.
  • the layer to be strained advantageously tensions.
  • defect includes crystal defects, that is, atomic and extensive defects, e.g. B. understand clusters, bubbles, voids and so on. Based on such generated defect areas, dislocations are formed that lead to a relaxation tion of a layer adjacent to the bracing layer.
  • Relaxation is the reduction of the elastic tension within a layer.
  • An adjacent layer is to be understood as a layer which is arranged directly or separately from the layer to be strained by one or more further layers, provided that it is ensured that the dislocations lead to relaxation of a layer immediately adjacent to the layer to be strained.
  • substrate is to be understood as a layer on which the layer to be strained is arranged.
  • At least one first layer can be applied epitaxially to the free surface of the layer to be strained, this first layer having a different degree of tension than the layer to be strained. Defects can then be generated in the first layer.
  • the layer structure is subjected to at least one temperature treatment so that dislocations are formed starting from the defects, which lead to relaxation of the first layer. As a result, the layer to be strained arranged underneath stretches. The defects can also be generated in the layer to be strained itself.
  • a graded layer is also understood as a first layer, the region of the graded layer arranged on the layer to be strained having a different degree of tension than the layer to be strained. A defect region is then created in the graded layer.
  • the layer structure is subjected to a temperature treatment, so that, starting from the defect area, dislocations are formed which lead to
  • the layer to be strained is transformed into an elastically strained layer.
  • a layer adjacent to the layer to be tensioned relaxes, which advantageously has the effect that the layer to be tensioned changes into the desired tensioned state.
  • the layer region of the graded layer which adjoins the layer to be strained relaxes, so that the layer to be strained again changes into the desired strained state.
  • the layer arranged on the layer to be strained has a different degree of tension than the layer to be strained itself. In the course of the process it is possible to arrange further layers.
  • At least a first and a second layer of different lattice structure are applied epitaxially to a layer to be tensioned on a substrate, the first layer having a different degree of tension than the layer to be tensioned,
  • a defect area is generated in the second layer and / or in a further layer
  • the layer structure is subjected to a temperature treatment so that, starting from the defect area, dislocations are formed which lead to relaxation of the first layer.
  • the first, relaxing layer is adjacent to the layer to be strained, and as a result, the layer to be strained in turn strains.
  • a different lattice structure means layers which have differences in the lattice parameters and / or in the crystal structure.
  • a further layer which is also relaxing in the course of the method can be arranged between a layer to be tensioned and the substrate. the.
  • a relaxing layer is thus obtained on a substrate, on which a layer to be strained is arranged.
  • a layer relaxing in the course of the method can in turn be arranged on this.
  • a layer to be tensioned can in turn be arranged on this relaxing layer.
  • Additional layers can be arranged.
  • the relaxing layers have a different degree of tension than the adjacent layers to be tensioned. After relaxation of the layers, the layers to be strained tension in one process step during the heat treatment or during the oxidation.
  • the defect area can also be created in the substrate.
  • the defect area is generated so that the dislocations lead to relaxation of a layer adjacent to the layer to be strained.
  • Such an epitaxial layer structure or wafer can advantageously be produced in a deposition process.
  • the wafer can particularly advantageously be left in the reactor and deposited without complex polishing and cleaning.
  • the resulting tension is selected for the layer to be tensioned.
  • the layer structure is advantageously subjected to at least one temperature treatment.
  • oxidation can accordingly be used as treatment, or a combination of oxidation and thermal treatment. This also increases the concentration of elements that are important for the functioning of the component within the layer structure (e.g. Ge enrichment in Si-Ge).
  • substrate is meant in particular an SOI substrate, the silicon surface of which is clamped.
  • An amorphous layer in particular an insulator, is generally also meant as substrate.
  • substrate it can just as well be understood as a material with any electrical properties that permits thermally induced tensioning of the layer to be tensioned with the aid of the method according to the invention.
  • a crystalline hetero-boundary surface with a sufficiently large lattice mismatch (eg 1%) or with a different crystal structure can be suitable if the layer thickness of the layer d 3 to be strained is chosen to be small enough (eg 5-50 nanometers) ter) and the substrate is sufficiently thick, e.g. B. 10 - 100 times as thick as the layer to be strained.
  • These conditions are e.g. B. met by the single-crystal SOI substrate Silicon on Sapphires.
  • Si0 2 silicon dioxide
  • Si0 2 can already be made viscoelastic at approx. 800 ° C.
  • Such substrates can be made by wafer bonding, similar to commercial BESOI substrates where a thin Si layer is bonded to silicon dioxide.
  • the layer to be strained can be applied to any glass or other suitable, temperature-resistant substrate. With a corresponding thickness of these materials, they can also have the function of a suitable mechanical base for the layer structure. Even a certain flexibility of the substrate would be desirable in view of the development of "flexible electronics".
  • An advantage of this method is that only an epitaxial deposition and no complex and time-consuming process steps such as wafer bonding and polishing (CMP) are required to produce a strained layer.
  • CMP wafer bonding and polishing
  • SIMOX wafers with a thin silicon surface to be clamped can be used as the basic structure.
  • the silicon layer of these wafers is strained during the process.
  • SIMOX wafers generally have a dislocation density of approx. 10 5 cm “2 , at best 10 2 -10 3 cm “ 2 , but are characterized by very good layer homogeneity and purity, as well as by economical production.
  • the process uses process steps that are established in silicon technology.
  • the technology can thus also be applied to very large wafers, e.g. B. 300 millimeter wafer can be transferred.
  • the defect area can be created by ion implantation.
  • the defect area is also possible to generate the defect area as soon as the layers are applied to the layer to be strained, for example by lowering the temperature, for. B. to approx. 200 ° C in a molecular beam epi- Taxi system during the application of the layers or the graded layer to the layer to be strained.
  • the defect area can be implemented by installing an Si-C layer.
  • a temperature between 550 and 1200 ° C. and in particular between 700 and 950 ° C. can be selected as a suitable measure for a temperature treatment. Defects, in particular dislocations, form in the first and / or second layer, starting from the defect region, which lead to relaxation of the first layer, as a result of which the layer to be tensioned is tensioned.
  • the tension of the first layer By selecting the tension of the first layer, tensile or compressive stress, the resulting stress in the layer to be tensioned can be selected. Is the first layer pressurized before the temperature treatment, e.g. B. of choice of Si-Ge as material for the first layer (with any Ge concentration) then the layer to be strained, z. B. consisting of silicon, tensile.
  • pressure-stressed silicon can be produced, for example, by using a tensile stressed first layer of, for example, Si-C with up to approx. 1-2at% C.
  • ternary alloys, such as Si-Ge-C, and the use of doped Si layers or alloys (B, As, P, Sb, Er, S or others) is also possible.
  • the temperature treatment can be carried out in an inert atmosphere, vacuum or in an oxidizing, e.g. B. in 0 2 or H 2 0 environment or in nitriding, z. B. in NH 3 or reducing atmosphere, e.g. B. in forming gas. Very good results are achieved with temperature treatment in nitrogen.
  • the strained layer produced in this way is exposed, for example by wet chemical removal first of the second and then at least partially of the first layer.
  • This layer structure serves more complex purposes
  • SOI structures, SIMOX wafers or BESOI structures can in principle be selected as starting structures.
  • the layer to be strained, the insulator and the substrate are already available as a basic structure.
  • the layer to be strained only on an amorphous layer for. B. an insulator is applied as an amorphous layer and then tensioned.
  • the insulator can be on a substrate, for. B. be made of silicon, or as mentioned itself represent the substrate.
  • the layer to be strained can advantageously be selected from silicon.
  • the layer to be strained can be selected particularly advantageously with a thickness d 3 of 1-100 nanometers, in particular of 5-30 nanometers.
  • This layer thickness d 3 should at least not exceed the critical layer thickness and it must be so small that at least a substantial part of the dislocations from the first layer can spread along the sliding planes in this layer.
  • This thickness depends in particular on the degree of tension of the first layer and its layer thickness d 4 . The greater the desired tensioning of the layer, the smaller d 3 must be.
  • a large layer thickness ratio of d 4 / d 3 advantageously appears in particular a layer thickness ratio of d 4 / d 3 of greater than or equal to 10.
  • the first layer on the layer to be strained can be, for. B. an epitaxial Si-Ge or Si-Ge-C or Si-C layer with a thickness that is advantageously close to the critical layer thickness can be deposited.
  • the critical layer thickness defines the maximum layer thickness for this first layer, at which a defect-free growth is still possible on the layer that is not to be matched to the grid. With a layer thickness below this critical layer thickness, strictly pseudomorphic, ie. H. completely defect-free growth can be achieved. The critical layer thickness should not be exceeded so far that the layer is already noticeably relaxed.
  • a graded layer can also be arranged. That means the composition rises or falls within the graded layer.
  • the Ge concentration can be increased slowly or in steps, or growth can also be started with a higher Ge concentration or even with pure germanium (Ge) over just a few nanometers.
  • the Ge concentration can then drop quickly (e.g. to 25at%).
  • the layer thickness can still be around 80 nanometers. The area with the high Ge concentration enables high degrees of relaxation over 80%.
  • a U concentration profile can also be advantageous in order to achieve a specific Ge concentration of e.g. B. 20-40at% to achieve the greatest possible degree of relaxation of the first layer and thus a high degree of bracing for the layer to be braced.
  • the second epitaxial silicon layer to be deposited can be selected. This layer then serves to form a defect area.
  • the layer thickness d 5 this layer can be optimized for the formation of the defect area. It is not limited by growth criteria. d 5 can thus be varied freely (e.g. 0-1000 nanometers). A thickness of approx. 200-500 nanometers appears to be advantageous for hydrogen and
  • a layer that is as thin as possible enables implantation with small energies (e.g. 10 keV) and thus with a sharper distribution of the implanted ions, which is advantageous for the formation of a thin defect area and also saves costs.
  • small energies e.g. 10 keV
  • a further layer e.g. B. to avoid surface roughening by blistering after hydrogen or helium implantation on the second layer.
  • This layer can be amorphous or polycrystalline.
  • This layer can before or after the creation of the defect area z. B. deposited by ion implantation.
  • the layer thickness of this optional layer only has to be coordinated with the implantation parameters.
  • a locally limited defect area is generated by arranging a mask on the second or further optional layers. This has the particularly advantageous effect that locally strained and unstressed areas are planer, that is to say in a plane directly next to one another, without straining further step formation as previously known from the prior art can be generated.
  • the defect area or areas can be particularly advantageously by ion implantation, preferably with light ions such as hydrogen (H + , H 2 + ), helium, fluorine, boron, carbon, nitrogen, sulfur and so on, or by ions of the layer or substrate material itself, that is z.
  • light ions such as hydrogen (H + , H 2 + ), helium, fluorine, boron, carbon, nitrogen, sulfur and so on, or by ions of the layer or substrate material itself, that is z.
  • noble gas ions are also z. B. Ne, Ar, Kr and so on.
  • a dose of approximately 3 ⁇ 10 15 to 3.5 ⁇ 10 16 cm “2 , but in particular for helium of 0.4-2.5 ⁇ 10 16 cm “ 2 is used.
  • a combination of two implantations, e.g. B. first hydrogen and then helium or only boron and then hydrogen are suitable.
  • a boron implantation in connection with a hydrogen implantation allows the dose of the hydrogen implantation to be reduced.
  • a temperature treatment between the implantations can also be advantageous in order to generate nucleation nuclei for the formation of defects.
  • the defect area is advantageously generated at a distance of 50 to 500 nanometers from the layer to be relaxed.
  • the energy of the ions and thus the average range of the ions is chosen such that they are implanted at a distance d e from the interface of the first to the second layer.
  • This distance d 6 is z. B. in the range of about 50 to 300 nanometers.
  • the implantation depth is adapted to the layer thickness of the second layer and possibly also other optional layers and the mass of the selected ion.
  • the maximum damage is generated within the second layer, in particular at a distance d 6 from the first layer and not in the first layer itself.
  • ions that lead to the formation of bubbles or cracks such as e.g. B. hydrogen, helium, fluorine, neon, argon, etc.
  • the defect formation in the first layer and in the second layer can also be set independently of one another by means of two or more implantations.
  • An advantageous procedure is also first to carry out one or more implantations with different energy, possibly also with different ions in the first layer with a low dose, and to build up the defect region in the second layer with a second implantation.
  • the generation of point defects in the first layer to be relaxed leads to accelerated diffusion and to greater relaxation.
  • the ion implantation can be carried out over the entire surface or by using an implantation mask, e.g. B. Photoresist can be performed anywhere on the wafer.
  • the wafer for the ion implantation is not tilted at an angle of 7 °, as is known from the prior art. Rather, the wafer is tilted from the normal at an angle of greater than 7 °, in particular at an angle of 30-60 °.
  • the first layer is advantageously hardly or not damaged by the implantation carried out in this way.
  • the optimal dose and energy and type of ions do not depend on the composition and layer thickness of the first layer to be relaxed and can therefore be optimized more easily if the second layer is implanted.
  • the desired strained layer or regions of this layer that are not strained at the non-implanted sites are obtained with the same layer thickness while maintaining the planarity.
  • the first layer applied thereon is advantageously selectively removed by wet chemical means, at least in the last removal phase.
  • the transition areas in the areas between the tensioned and unstressed areas are advantageously designed as insulation areas between the components.
  • Silicon dioxide is again particularly advantageously selected as the insulation material.
  • a layer system consisting of several layers is used instead of an exclusively first layer.
  • Further epitaxial layers can be deposited on generated strained areas in order to e.g. B. increase the layer thickness of the strained areas or adapt locally to the wafer or new layers z. B. for more complex electronic or optoelectronic components.
  • a strained layer can be produced which advantageously has an extremely low surface roughness of regularly less than 1 nanometer and only a low defect density of less than 10 7 cm “2 , in particular less than 10 5 cm “ 2 .
  • the low roughness is particularly advantageous in the manufacture of MOSFETs where a thermal oxide or other dielectric, e.g. B. a high-k dielectric, that is, a material with a high dielectric constant must be generated on the strained layer.
  • a thermal oxide or other dielectric e.g. B. a high-k dielectric, that is, a material with a high dielectric constant must be generated on the strained layer.
  • the surface roughness has a very sensitive influence on the electrical quality of the dielectric, which is the heart of a transistor.
  • the mobility of the charge carriers in a very thin layer is also largely determined by the interfaces.
  • the surface roughness of, for example, braced Silicon can be further reduced by growing a thermal oxide. This oxide thus produced can then be removed prior to the growth or deposition of the gate dielectric.
  • the method offers the potential for a further reduction in the dislocation density in the relaxed and the tensioned layer.
  • etching trenches in the layers with micrometer intervals for example from 1 to 100 micrometers or more advantageously, by etching trenches which are matched to the component structures and subsequent annealing at temperatures above 500 ° C. Thread dislocations in the layer slide to the edge of these areas and are thus healed.
  • These etched trenches can also be used to produce shallow trench insulation.
  • the trenches are filled with an insulator material and the components are thus electrically separated from one another.
  • Another suitable method for reducing the dislocation density is the application on an oppositely tensioned layer to the relaxed first layer after the latter has been partially relaxed by implantation and temperature treatment.
  • a Si-Ge layer is a compressed layer z.
  • a subsequent one Heat treatment e.g. B. by tempering in an inert or reactive atmosphere, leads to a higher relaxation of the Si-Ge layer and thus to a higher tension of the Si layer to be strained.
  • the dislocation density is reduced. This procedure can also be used on previously structured surfaces.
  • the second layer e.g. B. a strained Si-Ge layer in the non-implanted areas for the production of special components such. B. can be used particularly advantageously for p-MOSFET, since these layers have particularly high hole mobility, depending on the Ge content, z. B. increased by a factor of 2-3 compared to silicon.
  • the strained Si layers produced in this way can be used to some extent, since the electron and hole mobility in the tetragonal lattice of the strained silicon is increased by approx. 100% and approx. 30% compared to unstrained silicon if the grating tension is> 1%. You are not tied to specific transistor types or components. MODFETs, resonant tunnel diodes, photodetectors and quantum cascade lasers can also be implemented.
  • FIG. 1 Schematic layer system comprising an SOI substrate 1, 2, 3 and a first and a second layer 4, 5 applied epitaxially thereon.
  • Figure 2 Schematic layer system comprising an SOI substrate 1, 2, 3 and an epitaxially applied layer structure with implantation mask 6 and defect area 7 in the second layer 5.
  • Figure 3 Schematic layer system comprising a
  • FIG. 4 Schematic layer system comprising an SOI substrate 1, 2, 3 with a braced area 9 next to a non-braced area 3 on an insulator layer 2.
  • Figure 5 Schematic layer system with additional epitaxial layer 10, which was applied epitaxially on the tensioned and non-tensioned areas 9 and 3.
  • Figure 6 Alternative schematic layer structure with three layers 11, 12, 13 applied to the layer 3 to be strained.
  • Layer 11 serves as an additional buried layer to be strained or as an etching stop layer.
  • FIG. 7 Schematic layer system with isolation areas 14 (shallow trench isolations) between braced areas 9 and non-braced areas 3.
  • FIG. 8 Schematic layer system as in FIG. 1 with etched trenches 15.
  • Figure 9 Schematic representation of a MOSFET on a strained Si layer with gate stack and raised source and drain and silicide contacts on an insulator.
  • An unstressed Si layer 3 can be seen to the right of the transistor and a strained Si-Ge layer 11 on an unstressed Si layer 3 on the left.
  • a gas surface epitaxy or molecular beam epitaxy on a SOI substrate 1, 2, 3 (SIMOX or BESOI) on a 20 nanometer thick (d 3 ) Si surface layer 3 to be strained is used first epitaxial Si-Ge layer 4 with 22 at% Ge and a layer thickness d 4 of 220 nanometers deposited defect-free or almost defect-free. Subsequently, single-crystal silicon with a thickness d 5 of 500 nanometers is applied as the second layer 5.
  • the layer structure 1, 2, 3, 4, 5 is implanted after applying a mask 6 (FIG. 2) with helium ions with an energy of 20 keV and a dose of 1.5 ⁇ 10 16 cm 2 , and then at 850 ° C annealed for 10 min.
  • the structure can also be implanted with hydrogen ions at a dose of 2 ⁇ 10 16 cm “2 .
  • the implantation in layer 5 creates a defect region 7 close to the interface (d 6 is approximately 200 nm) with the Si-Ge layer 4, which leads to relaxation of the Si-Ge layer 4 in this region during the annealing the state of tension of the non-implanted areas does not change or does not change significantly.
  • the degree of relaxation of the Si-Ge layer after annealing is approximately 75%.
  • layer 8 of silicon dioxide with a thickness of e.g. B. 500 nanometers before or after the implantation advantageously has the effect that blistering of the surface due to the formation of hydrogen or helium bubbles is avoided during the temperature treatment (FIG. 3).
  • layer 5 or layer 8 and a silicon nitride (SiN x ) layer under pressure can be removed with a thickness, starting from the layer structure in FIG. 3 of about 100 nanometers are deposited on the partially relaxed Si-Ge layer 4 (not shown).
  • This SiN x layer can be deposited by means of PE-CVD (plasma enhanced chemical vapor deposition).
  • PE-CVD plasma enhanced chemical vapor deposition
  • a second tempering of the layer structure at 900 ° C. for 10 minutes increases the degree of relaxation at the implanted sites to over 80% and the Si layer 9 is further tensioned.
  • layer 4 Further etching of layer 4 exposes Si layer 3 (FIG. 4) and can be used for the production of high-speed components. Layer 9 is stretched under the implanted areas. The thread dislocation density is less than 10 7 cm "2 .
  • a layer 10 (FIG. 5), e.g. B. Si with a thickness that does not or does not significantly exceed the critical layer thickness epitaxially deposited. Care must be taken to ensure that the tension state changes along the layer 10, as indicated by the different hatching of the layer 10. This depends on the document. Silicon 10 will grow strained on strained silicon 9 up to the critical layer thickness. Instead of a Si layer, any other layer or layer sequence can also be applied.
  • Second embodiment Production of a strained Si layer on Si0 2 with high tension
  • the layer production largely follows the first exemplary embodiment, starting from FIG. 1.
  • a graded layer 4 with a strongly inhomogeneous concentration profile is applied.
  • the second layer 5 is applied only optionally. It is advantageous to start the growth of layer 4 with a higher Ge concentration (eg 40at% Ge), possibly even with a few nanometers thick pure germanium, and then the concentration up to z. B. 20 at%, so as to achieve a layer thickness of 150 nanometers without the formation of dislocations in disruptive density during growth.
  • the ge concentration can be reduced gradually or in steps to basically zero over a substantially larger layer thickness range (e.g. 600 nanometers), so that no second layer 5 has to be deposited at all.
  • a U-shaped concentration curve that is to say only a decreasing then increasing Ge content in the growth direction, can also be used.
  • a layer with an inhomogeneous concentration leads to higher relaxation rates and smaller defect densities than equivalent homogeneous layers.
  • the layer thickness d 4 should be as large as possible, but in all cases be below the critical layer thickness, so that no noticeable relaxation occurs during growth.
  • Third embodiment Si implantation instead of implantation with light ions
  • an Si implantation can take place, for example, with an energy of approximately 150 keV and a dose of approximately 1 ⁇ 10 14 cm 2 in a 500 nanometer thick Si layer 5 (FIG. 2).
  • the implanted Si -Ions generate crystal defects in the second layer 5 and in the Si-Ge layer 4, which promote the relaxation of the Si-Ge layer 4 and thus the tensioning of an Si layer 3 of an SOI substrate 1, 2, 3.
  • a thermal treatment at 900 ° C. in an inert nitrogen atmosphere or in a vacuum for a few minutes.
  • the implant energy and dose are optimized by measuring the degree of relaxation and the defect density.
  • two or more implantations can also be carried out with other ions in order to generate the defect area in layer 5 and point defects in layer 4 to be relaxed.
  • Another inert gas e.g. argon
  • a gas suitable for the purposes of the invention during the thermal treatment can also be used (e.g. 0 2 or forming gas).
  • thin silicon layers can also be arranged in the Si-Ge.
  • an implantation mask e.g. B. applied photoresist 6 and structured lithographically, so that the following ion implantation takes place only in the uncovered areas.
  • the layer is then implanted with hydrogen (3 ⁇ 10 16 cm “2 ) or helium ions (2 ⁇ 10 16 cm “ 2 ) in order to produce a defect region approximately in the middle of the 400 nanometer thick Si layer 5 (not shown).
  • the temperature treatment is carried out at 825 ° C in nitrogen.
  • the following layer structure is obtained after implantation and temperature treatment.
  • a relaxed region of the layer 13 is arranged on a strained region of the layer 12 below the silicon layer 5.
  • This area of layer 12 is in turn arranged on a relaxed area of layer 11 and this in turn is arranged on a tensioned area of layer 3 (FIG. 6).
  • Layer 3 represents the surface of the SOI substrate.
  • the implanted areas are obtained a strained Si layer 12 (10 nanometers thick) on a here relaxed 25 Nanometer thick Si-Ge layer 11 (no longer shown in the right part of the picture, since removed after etching) and a second strained Si layer 9 on the Si0 2 - Layer 2 of the SOI substrate 1, 2, 3 (see FIGS. 6 and 7).
  • Layer 3 and layer 12 still represent cubic silicon and the Si-Ge layer 11 is tetragonally strained (FIG. 7).
  • This layer structure can already be used for the production of components or further layers are deposited.
  • An oppositely braced area of the same layer material is arranged planar in one plane of one of the layers mentioned, without step formation.
  • the 10 nanometer thick Si layer 12 can also serve as an etch stop layer, in order to reduce the surface roughness after the etching to ⁇ 1 nanometer. This is particularly important for the strained Si layer 9 on the Si0 2, since the gate dielectric is applied to this layer for MOSFETs or is generated thermally. Purity and interface properties decisively determine the quality of the dielectric.
  • Isolation areas 14 in the braced area 9 can be produced by etching and filling with insulation material.
  • one or two or more strained layers are produced.
  • Etching trenches 15 (FIG. 8 or FIG. 7 before the manufacture of the shalow trench 14) are then produced in this layer structure.
  • These trenches 15 are generally etched as far as the insulator layer 2 in order to be able to easily generate isolation regions (shallow trench isolation) between the components by filling them with an insulator 14 (as in FIG. 7).
  • an annealing is carried out at above 450 ° C., advantageously above 650 ° C. This tempering causes thread dislocations in layer 4, an Si-Ge layer and in the strained layer 9 to run to the trenches 15 and thus heal.
  • the temperature treatment can also be carried out later during the component production, e.g. can also be used to heal defects after ion implantation or to grow the gate dielectric.
  • strained Si on Si0 2 almost in one plane with strained Si-Ge layer and n- and p-MOSFET components.
  • a layer structure according to FIG. 6 is used in order to produce the strained layers first.
  • the layers 12 and 11 can be selectively, e.g. B. on the implanted areas can be removed by wet chemistry.
  • the step height between these areas is only determined by the thickness of layers 11 and layer 12 (a total of 35 nanometers). This step height is smaller than the depth of field of the lithography, so that further lithography steps can be carried out without any problems.
  • the areas can be electrically and structurally separated by insulation areas 14 (FIG. 7).
  • Ultrafast n- and p-channel MOSFETs can be produced in the regions with strained silicon 9, since the electron and hole mobility in the tetragonal lattice of the strained silicon is approx - Tensioned silicon is increased if the lattice strain is> 1%.
  • P-channel MOSFETs can advantageously be produced on the strained Si-Ge layer 11 of FIG. 7 or on the silicon layer 12, since the Si-Ge layer 11 is characterized by greatly increased hole mobility.
  • the small total thickness of layers 3, 11 and 12 of approximately 45 nanometers (FIG. 7) allows the production of fully depleted MOSFETs.
  • the thin Si layer 12 can advantageously be used for the production of the gate dielectric, since a high-quality thermal oxide or oxynitride can be formed thereon as the gate dielectric. It is also advantageous that the gate dielectric can be generated thermally or by deposition in the different areas at the same time.
  • Si-based components can be implemented on the non-implanted areas after selective removal of the Si-Ge layer 11.
  • the thin Si layer 12 of FIG. 7 can be used as a template for a further, preferably selective, epitaxy of silicon. This creates optimal conditions for the implementation of very different components on a chip (system on a chip).
  • a defect area is created in the middle layer of Si-C during the subsequent temperature treatment at 1000 ° C. fen, which causes the relaxation of the underlying and the overlying Si-Ge layer.
  • the carbon is built into the thin Si-C layer in sufficient concentration.
  • the Si-C layer becomes a defect area, which favors the relaxation of the Si-Ge layer underneath and above.
  • the Si-Ge layers relax to 90%. Accordingly, the thin Si layer of the SOI substrate is elastically strained and a strained Si layer on Si0 2 is generated.
  • a layer system that consists of a thin layer, a layer 11 with a different composition (for example a Si-C or Si-Ge layer with a different concentration) and a further silicon layer 12 and a layer 13 (Si-C or Si-Ge) exist (Figure 6).
  • Layer 12 can either be transformed into a strained layer or simply used as an etch stop layer.
  • the use of an additional etch stop layer can largely prevent surface roughening during the etching back, since then only a very small layer thickness (layer 11) has to be removed in the last etching step before layer 3 or 9 is exposed in order to minimize relaxation and defect density.
  • the method offers the potential for further reductions in the dislocation density in the relaxed and the tensioned layer.
  • Another suitable method for reducing the dislocation density is to apply it to a strained layer on layer 4 after it has been largely relaxed by implantation and temperature treatment.
  • a pressure-stressed layer is suitable, for. B. a silicon nitride layer (z. B. 100 nanometers) that has been deposited in a PE-CVD reactor.
  • a subsequent temperature treatment (tempering in an inert or reactive atmosphere) leads to a higher relaxation of the Si-Ge layer and thus to a higher tension of the Si layer.
  • the dislocation density is reduced.
  • This method can also be used on previously structured surfaces (FIG. 7).
  • FIG. 9 shows a MOSFET with silicided contact 16 (e.g. source), gate dielectric 17, gate contact 18, e.g. B. poly-Si or metal, gate contact 19, for example silicide, spacer insulation 20, silicided drain contact 21 and raised drain contact 22 (highly doped Si or Si-Ge).
  • silicided contact 16 e.g. source
  • gate dielectric 17 e.g. B. poly-Si or metal
  • gate contact 19 for example silicide
  • spacer insulation 20 e.g. spacer insulation
  • silicided drain contact 21 and raised drain contact 22 highly doped Si or Si-Ge
  • Epitaxial layer 5 (eg silicon) with layer thickness d 5 6 mask
  • the z. B. is generated by ion implantation.
  • the maximum of the range of the ions is at a distance d 6 from the interface of layers 4 and 5.
  • platelets, bubbles or microcracks are formed at this depth, which eject defects, such as dislocations.
  • strained layer or area e.g. B. strained silicon 10 epitaxial layer, which is deposited on the non-strained 3 or strained layer 9, z. B. from Si or Si-Ge or Si-Ge-C or Si-C. Deposition of silicon increases the layer thickness of the strained silicon.
  • 11 epitaxial layer e.g. B. Si-Ge, Si-C or Si-Ge C, which is relaxed.
  • epitaxial layer e.g. B. graded to be relaxed, e.g. Si-Ge or Si-C or Si-Ge-C.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de production d'une couche contrainte sur un substrat. Ce procédé comprend les étapes consistant : à générer une zone défectueuse dans une couche adjacente à la couche à contraindre, et ; à détendre au moins une couche adjacente à la couche à contraindre. D'autres couches peuvent être déposées par épitaxie. Les structures en couches ainsi formées sont de préférence conçues pour des composants extrêmement variés.
EP04726422A 2003-04-22 2004-04-08 Procede de production d'une couche contrainte sur un substrat, et structure en couches Withdrawn EP1616345A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10318283A DE10318283A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
PCT/DE2004/000736 WO2004095552A2 (fr) 2003-04-22 2004-04-08 Procede de production d'une couche contrainte sur un substrat, et structure en couches

Publications (1)

Publication Number Publication Date
EP1616345A2 true EP1616345A2 (fr) 2006-01-18

Family

ID=33304879

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04726422A Withdrawn EP1616345A2 (fr) 2003-04-22 2004-04-08 Procede de production d'une couche contrainte sur un substrat, et structure en couches

Country Status (5)

Country Link
US (2) US7615471B2 (fr)
EP (1) EP1616345A2 (fr)
JP (1) JP5259954B2 (fr)
DE (1) DE10318283A1 (fr)
WO (1) WO2004095552A2 (fr)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10318284A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7202145B2 (en) * 2004-06-03 2007-04-10 Taiwan Semiconductor Manufacturing Company Strained Si formed by anneal
DE102004048096A1 (de) * 2004-09-30 2006-04-27 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
US8105908B2 (en) * 2005-06-23 2012-01-31 Applied Materials, Inc. Methods for forming a transistor and modulating channel stress
KR100673020B1 (ko) 2005-12-20 2007-01-24 삼성전자주식회사 전계효과 소오스/드레인 영역을 가지는 반도체 장치
US7339230B2 (en) * 2006-01-09 2008-03-04 International Business Machines Corporation Structure and method for making high density mosfet circuits with different height contact lines
DE102006004870A1 (de) 2006-02-02 2007-08-16 Siltronic Ag Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur
DE102006010273B4 (de) * 2006-03-02 2010-04-15 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung
US7494886B2 (en) 2007-01-12 2009-02-24 International Business Machines Corporation Uniaxial strain relaxation of biaxial-strained thin films using ion implantation
US8471307B2 (en) * 2008-06-13 2013-06-25 Texas Instruments Incorporated In-situ carbon doped e-SiGeCB stack for MOS transistor
DE102008035816B4 (de) * 2008-07-31 2011-08-25 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 Leistungssteigerung in PMOS- und NMOS-Transistoren durch Verwendung eines eingebetteten verformten Halbleitermaterials
TWI430338B (zh) * 2008-10-30 2014-03-11 Corning Inc 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置
US8003491B2 (en) * 2008-10-30 2011-08-23 Corning Incorporated Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US9059201B2 (en) * 2010-04-28 2015-06-16 Acorn Technologies, Inc. Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
US8361889B2 (en) * 2010-07-06 2013-01-29 International Business Machines Corporation Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
US8822306B2 (en) * 2010-09-30 2014-09-02 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
US8404562B2 (en) 2010-09-30 2013-03-26 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
DE102010064290B3 (de) * 2010-12-28 2012-04-19 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verformungserhöhung in Transistoren mit einem eingebetteten verformungsinduzierenden Halbleitermaterial durch Kondensation der legierungsbildenden Substanz
US8859348B2 (en) 2012-07-09 2014-10-14 International Business Machines Corporation Strained silicon and strained silicon germanium on insulator
EP2741320B1 (fr) * 2012-12-05 2020-06-17 IMEC vzw Méthode de fabrication d'un dispositif finfet à deux canaux contraints
FR3003686B1 (fr) * 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
US9269714B2 (en) * 2013-06-10 2016-02-23 Globalfoundries Inc. Device including a transistor having a stressed channel region and method for the formation thereof
FR3041146B1 (fr) * 2015-09-11 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de mise en tension d'un film semi-conducteur
US9871057B2 (en) * 2016-03-03 2018-01-16 Globalfoundries Inc. Field-effect transistors with a non-relaxed strained channel
FR3050569B1 (fr) * 2016-04-26 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Fabrication amelioree de silicium contraint en tension sur isolant par amorphisation puis recristallisation
WO2018004527A1 (fr) * 2016-06-28 2018-01-04 Intel Corporation Cellule pour verrou à résistance différentielle négative (ndr) du type n
US9818875B1 (en) * 2016-10-17 2017-11-14 International Business Machines Corporation Approach to minimization of strain loss in strained fin field effect transistors
CN111785679A (zh) * 2020-07-29 2020-10-16 联合微电子中心有限责任公司 半导体器件及其制备方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3627647A (en) * 1969-05-19 1971-12-14 Cogar Corp Fabrication method for semiconductor devices
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5344785A (en) * 1992-03-13 1994-09-06 United Technologies Corporation Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate
US5847419A (en) * 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
JP3645390B2 (ja) * 1997-01-17 2005-05-11 株式会社東芝 半導体装置およびその製造方法
DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
JP3884203B2 (ja) * 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
JP4212228B2 (ja) * 1999-09-09 2009-01-21 株式会社東芝 半導体装置の製造方法
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
US6690043B1 (en) * 1999-11-26 2004-02-10 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP4226175B2 (ja) * 1999-12-10 2009-02-18 富士通株式会社 半導体装置およびその製造方法
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
EP1364411A1 (fr) * 2001-03-02 2003-11-26 Amberwave Systems Corporation Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides
JP3933405B2 (ja) * 2001-03-06 2007-06-20 シャープ株式会社 半導体基板、半導体装置及びそれらの製造方法
JP3875040B2 (ja) * 2001-05-17 2007-01-31 シャープ株式会社 半導体基板及びその製造方法ならびに半導体装置及びその製造方法
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030077882A1 (en) * 2001-07-26 2003-04-24 Taiwan Semiconductor Manfacturing Company Method of forming strained-silicon wafer for mobility-enhanced MOSFET device
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6746902B2 (en) * 2002-01-31 2004-06-08 Sharp Laboratories Of America, Inc. Method to form relaxed sige layer with high ge content
DE10218381A1 (de) * 2002-04-24 2004-02-26 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge
US6972245B2 (en) * 2002-05-15 2005-12-06 The Regents Of The University Of California Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures
US6689671B1 (en) * 2002-05-22 2004-02-10 Advanced Micro Devices, Inc. Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate
US6774015B1 (en) * 2002-12-19 2004-08-10 International Business Machines Corporation Strained silicon-on-insulator (SSOI) and method to form the same
DE10310740A1 (de) * 2003-03-10 2004-09-30 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen
US6767802B1 (en) * 2003-09-19 2004-07-27 Sharp Laboratories Of America, Inc. Methods of making relaxed silicon-germanium on insulator via layer transfer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004095552A2 *

Also Published As

Publication number Publication date
WO2004095552A3 (fr) 2004-12-02
WO2004095552A2 (fr) 2004-11-04
DE10318283A1 (de) 2004-11-25
US20090298301A1 (en) 2009-12-03
JP2006524426A (ja) 2006-10-26
US20060220127A1 (en) 2006-10-05
US7915148B2 (en) 2011-03-29
US7615471B2 (en) 2009-11-10
JP5259954B2 (ja) 2013-08-07

Similar Documents

Publication Publication Date Title
WO2004095552A2 (fr) Procede de production d'une couche contrainte sur un substrat, et structure en couches
EP1604390B1 (fr) Procede de production d'une structure lamellaire liberant la contrainte sur un substrat non adapte en grille et utilisation d'un tel systeme lamellaire dans des composants electroniques et/ou optoelectroniques
EP1616346A2 (fr) Procede pour produire une couche contrainte sur un substrat et structure en couches
DE112011106092B3 (de) Halbleiter, der durch elastische Kantenrelaxation eines Stressors in Kombination mit einer vergrabenen Isolierschicht verspannt wird
EP0838858B1 (fr) Circuit intégré CMOS et son procéde de fabrication
US7348259B2 (en) Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
KR100392166B1 (ko) 반도체 장치의 제조 방법 및 반도체 장치
JP3970011B2 (ja) 半導体装置及びその製造方法
DE102006060886B4 (de) SOI-Anordnung mit mehrfachen Kristallorientierungen sowie zugehöriger SOI-Baustein und zugehörige Herstellungsverfahren
JP2006522469A5 (fr)
DE69333173T2 (de) Verfahren zur Herstellung eines Substrates mit einer Halbleiterschicht auf einem Isolator
WO2011051499A1 (fr) Procédé de fabrication de tranches de semiconducteur de silicium avec une couche pour l'intégration de composants semiconducteurs iii-v
US6869897B2 (en) Manufacturing method for semiconductor substrate, and semiconductor device having a strained Si layer
EP1497855B1 (fr) Procede de production d'une ou plusieurs couches monocristallines dotee chacune d'une structure reticulaire differente dans un plan d'une suite de couches
DE10229003B4 (de) Ein Verfahren zur Herstellung eines SOI-Feldeffekttransistorelements mit einem Rekombinationsgebiet
JP3933405B2 (ja) 半導体基板、半導体装置及びそれらの製造方法
EP1794779A2 (fr) Procede pour realiser une couche contrainte sur un substrat et structure de couches
DE10145699A1 (de) Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
JP2001332745A (ja) 半導体装置の製造方法及び半導体装置
Chang et al. The Higher Mobility Fabrication and Study for SiGe Nanowire

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20051011

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20080212

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20150507