EP1026754B1 - Diode - Google Patents

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Publication number
EP1026754B1
EP1026754B1 EP98923079A EP98923079A EP1026754B1 EP 1026754 B1 EP1026754 B1 EP 1026754B1 EP 98923079 A EP98923079 A EP 98923079A EP 98923079 A EP98923079 A EP 98923079A EP 1026754 B1 EP1026754 B1 EP 1026754B1
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EP
European Patent Office
Prior art keywords
region
layer
main surface
life time
diode
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EP98923079A
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English (en)
French (fr)
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EP1026754A1 (de
EP1026754A4 (de
Inventor
Shinji Koga
Kazuhiro MORISHITA
Kathumi SATOH
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to EP06026235A priority Critical patent/EP1780799B9/de
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Publication of EP1026754A4 publication Critical patent/EP1026754A4/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a diode suitable for a free wheel diode to be used together with a high breakdown voltage switching element such as an IGBT (Insulated Gate Bipolar Transistor), a GCT (Gate Commutated Turn-off Thyristor) or the like, or suitable for a high breakdown voltage clamp diode or the like.
  • a high breakdown voltage switching element such as an IGBT (Insulated Gate Bipolar Transistor), a GCT (Gate Commutated Turn-off Thyristor) or the like, or suitable for a high breakdown voltage clamp diode or the like.
  • Figs. 36 and 37 are a sectional front view and a plan view which show a conventional diode as the background of the present invention, respectively.
  • Fig. 36 is a sectional view taken along the line E - E in Fig. 37 .
  • a diode 151 comprises, as a main part, a semiconductor substrate 80 using silicon as a base material.
  • the semiconductor substrate 80 has a P layer 81, an N - layer 82 and an N + layer 83 provided sequentially from an upper main surface to a lower main surface.
  • An anode electrode 84 is connected to the upper main surface of the semiconductor substrate 80, that is, an exposed surface of the P layer 81, and a cathode electrode 85 is connected to the lower main surface of the semiconductor substrate 80, that is, an exposed surface of the N + layer 83.
  • These electrodes 84 and 85 are formed of an electrically conductive metal.
  • life time killers which are crystal defects for promoting the annihilation of carriers as the recombination centers of the carriers are introduced into the semiconductor substrate 80. Thereby the life time of the carrier is controlled.
  • Fig. 38 is a graph showing a profile of a density of the life time killers introduced into the semiconductor substrate 80.
  • the conventional diode 151 two kinds of profiles have been known.
  • the life time killers are uniformly introduced over the whole semiconductor substrate 80. Accordingly, the life time of the N - layer 82 is uniformly controlled.
  • a diode corresponding to the conventional example 2 is a device which has been disclosed in the International Conference PCIM '97 (International POWER CONVERSION '97 CONFERENCE NURNBERG, GERMANY June 10 - 12, 1997 ).
  • Fig. 39 is a graph showing a waveform of a current flowing in the diode in the transient state in relation to both the conventional examples 1 and 2.
  • An increase rate of the reverse current in an initial stage that is, (an absolute value of) a current decrease rate represented by di / dt in Fig. 39 is defined by the magnitude of an inductance acting as a load in the external circuit. If the inductance is increased, the current decrease rate di / dt is increased. Correspondingly, the reverse current is rapidly increased.
  • a depletion layer is generated at a time t1.
  • the depletion layer is formed in the PN junction as shown in Fig. 40 .
  • a front 92 of a depletion layer 91 advances toward the N + layer 83 with the passage of a time. Consequently, the depletion layer 91 is enlarged to cover the whole N - layer 82 shortly.
  • a reverse voltage v is generated at the time t1 between the anode electrode 84 and the cathode electrode 85, and then the reverse voltage v is increased to shortly converge on a value of a reverse bias applied from the outside. More specifically, when the depletion layer 91 grows, a reverse voltage blocking capability which is the original function of the diode is recovered.
  • Fig. 39 typically shows only the reverse voltage v related to the conventional example 2.
  • the reverse current gradually reduces the speed of the increase, and shortly reaches a peak and is then decreased.
  • the peak is increased.
  • a value of the peak is referred to as a reverse recovery current I rr , and is one of parameters for evaluating a reverse recovery characteristic in the diode.
  • the reverse current converges on zero while continuing the decrease.
  • a transient state that is, a reverse recovery operation comes to an end, and a steady state in which the reverse voltage v is equal to the reverse bias and the reverse current does not flow is realized.
  • an attenuation rate of the reverse recovery current As the parameter for evaluating the reverse recovery characteristic, an attenuation rate of the reverse recovery current, a di / dt capability and a reverse recovery loss have been known in addition to the above-mentioned reverse recovery current I rr .
  • the attenuation rate of the reverse recovery current is defined as a rate of convergence on zero after the reverse current passes through a peak in the graph of Fig. 39 .
  • the di / dt capability is a maximum value of the current decrease rate di / dt which can be applied without causing a damage on the diode.
  • the reverse recovery loss is a magnitude of a loss caused on the diode in the process of the reverse recovery operation.
  • the reverse recovery current I rr is smaller, it is possible to resist a greater current decrease rate di / dt. Accordingly, a simple relationship is established between the reverse recovery current I rr and the current decrease rate di / dt. Moreover, the reverse recovery loss is equivalent to a time integral of a product of the reverse current and the reverse voltage v in the graph of Fig. 39 . Accordingly, if the magnitude of the reverse recovery current I rr is smaller and the attenuation of the reverse recovery current is performed more quickly, the reverse recovery loss is more reduced.
  • the magnitude of the reverse recovery current I rr should be smaller, the attenuation of the reverse recovery current should be performed more quickly and the di / dt capability should be larger. Furthermore, it is desirable that the reverse recovery loss should be as small as possible.
  • the life time killers are introduced over the whole semiconductor substrate 80. Therefore, the attenuation of the reverse recovery current is performed quickly as shown in the curve Pr1 of Fig. 39 . Consequently, there is an advantage that the reverse recovery loss is small.
  • the magnitude of the reverse recovery current I rr is large.. As a result, there has been a problem in that the di / dt capability is small. In addition, there has been a problem in that a forward voltage acting as a significant parameter for evaluating a forward characteristic is high.
  • the life time killers are locally introduced in the vicinity of the PN junction at a higher density than in the conventional example 1. Consequently, the life time of the carriers is controlled to be short in the vicinity of the PN junction. Therefore, the recombination of the excess carriers is performed quickly in the vicinity of the PN junction. For this reason, the formation of the depletion layer 91 is promoted. Thus, the magnitude of the reverse recovery current I rr is small as shown in the curve Pr2 of Fig. 39 . As a result, it is possible to obtain an advantage that the di / dt capability is high.
  • the life time killers are not introduced into a region of the N - layer 82 excluding the vicinity of the PN junction. Therefore, the forward voltage is also advantageously low. More specifically, not only the di / dt capability but also the forward characteristic is more improved in the diode according to the conventional example 2 than in the conventional example 1.
  • both the conventional examples 1 and 2 have had a common problem in that oscillation is easily caused at the last stage of the reverse recovery operation.
  • the oscillation is caused as that of the reverse voltage v in an oscillation region Osc as shown in Fig. 39 .
  • Fig. 39 illustrates only the reverse voltage v according to the conventional example 2, the oscillation is caused more remarkably in the conventional example 1.
  • the depletion layer 91 is generated and then grows as shown in Fig. 40 .
  • the diode 151 can be equivalently represented by a series circuit formed by a capacitor having a pair of electrodes opposed to each other with the depletion layer 91 interposed therebetween and a leak resistor in the depletion layer 91 as shown in Fig. 41 .
  • a series resonance circuit is equivalently constituted by the combination of a capacitance C of the capacitor, a resistance R corresponding to the leak resistor and an inductance L existing in an external circuit.
  • a Q value of the resonance circuit is expressed by an equation. An oscillating phenomenon does not occur while the Q value is small.
  • the capacitance C is defined by a thickness of the deletion layer 91 and a density of the excess carriers
  • the resistance R is defined by a leak current in the depletion layer 91 and a recombination current of the excess carrier.
  • the diodes according to the conventional examples 1 and 2 have had a problem in that the voltage oscillation is easily caused at the last stage of the reverse recovery operation. The oscillation is easily caused particularly when the magnitude of the forward current is small and that of the reverse recovery current I rr is large. When the voltage oscillation is caused, the diode acts as a noise source for peripheral circuits.
  • the present invention is directed to a diode as recited in the claims.
  • Figs. 1 and 2 are a sectional front view and a sectional plan view which show a diode according to a first embodiment, respectively.
  • a cut surface of Fig. 1 is taken along the line B - B in Fig. 2
  • a cut surface of Fig. 2 is taken along the line A - A in Fig. 1 .
  • a diode 110 comprises a diode element 101 as a main member.
  • the diode element 101 includes a semiconductor substrate 20, an anode electrode (a first main electrode) 4 and a cathode electrode (a second main electrode) 5.
  • the semiconductor substrate 20 is plate-shaped to define upper and lower main surfaces, and uses silicon as a base material, for example.
  • the semiconductor substrate 20 is sequentially provided with a P layer (a first semiconductor layer) 1, an N - layer (a second semiconductor layer) 21, and an N + layer (a third semiconductor layer) 3 from the upper main surface toward the lower main surface.
  • the P layer 1 has a P - conductivity type (a first conductivity type), and the N - layer 21 and the N + layer 3 have an N - conductivity type (a second conductivity type).
  • a higher impurity concentration is set in the N + layer 3 than in the N - layer 21.
  • All the P layer 1, the N - layer 21 and the N + layer 3 are plate-shaped and are provided integrally with each other to form the semiconductor substrate 20.
  • the anode electrode 4 is connected to the upper main surface, that is, an exposed surface of the P layer 1
  • the cathode electrode 5 is connected to the lower main surface, that is, an exposed surface of the N + layer 3.
  • These electrodes 4 and 5 are formed of electrically conductive metals.
  • life time killers are selectively introduced into the semiconductor substrate 20, thereby controlling a life time of carriers.
  • first and second regions 6 and 7 having short life times and another region, that is, a third region 2 having a long life time are defined in the N - layer 21.
  • the first region 6 occupies a region of the N - layer 21 in the vicinity of a PN junction. More specifically, the first region 6 faces the P layer 1 to form the PN junction, and is defined as a layered region apart from the N + layer 3.
  • the second region 7 and the third region 2 are defined to mutually divide a portion of the N - layer 21 excluding the first region 6, that is, a portion which faces the N + layer 3 and does not face the P layer 1.
  • Each of the second region 7 and the third region 2 is formed like a column having the same planar sectional shape through the above-mentioned portion from the first region 6 to the N + layer 3.
  • the planar shape of the second region 7, that is, the shape of the second region 7 projected on the main surface of the semiconductor substrate 20 (each of the upper and lower main surfaces will be simply referred to as "main surface") is annular along the outer peripheral end face of the N - layer 21 in examples of Figs. 1 and 2 .
  • the third region 2 is defined as a cylindrical region surrounded by the second annular region 7.
  • Plate-shaped heat buffer plates 10 and 8 are in contact with the anode electrode 4 and the cathode electrode 5, respectively. Furthermore, an anode post electrode 11 and a cathode post electrode 9 are in contact with the heat buffer plates 10 and 8, respectively.
  • the diode 110 is to be used, the diode element 101 is pressed by the anode post electrode 11 and the cathode post electrode 9 through the heat buffer plates 10 and 8, thereby realizing an electrically and thermally good contact.
  • the post electrodes 11 and 9 are formed of electrically and thermally conductive metals using copper as a base material, for example, and the heat buffer plates 10 and 8 are formed of metals having a middle coefficient of thermal expansion between the post electrodes 11 and 9 and the diode element 101 (chiefly, the semiconductor substrate 20). Consequently, a heat distortion generated between the post electrodes 11 and 9 and the diode element 101 can be relieved so that an electrical and thermal contact can be kept well.
  • Fig. 3 is a graph showing a profile of a density of the life time killers introduced into the semiconductor substrate 20.
  • the graph illustrates profiles taken along both the vertical line X1 - X1 penetrating the third region 2 and the vertical line X2 - X2 penetrating the second region 7.
  • the profile taken along the line X1 - X1 is depicted in the same curve as the curve Pr2 according to the conventional example 2 shown in Fig. 38 . More specifically, the density of the life time killers is selectively high in the first region 6 including a PN junction interface. The density in the P layer 1 is also high. The reason is that the density on the PN junction interface of the first region 6 should be increased. Therefore, the density is incidentally increased also in the P layer 1 adjacent to the first region 6 in respect of a technique in which the life time killers are selectively introduced.
  • the profile of the life time corresponds to that of the density of the life time killers. More specifically, as the density of the life time killers is increased, the life time is reduced. In the third region 2, the life time killers are not substantially introduced. In other words, an original life time ⁇ 0 of the N - layer 21 is implemented in a substantial portion of the third region 2.
  • the life time of the first region 6 is set shorter than the life time ⁇ 0, and a life time ⁇ 1 on the PN junction surface is also set shorter than the life time ⁇ 0.
  • the life time killers are also introduced into the second region 7.
  • the life time of the second region 7 is set shorter than the life time ⁇ 0.
  • the density of the life time killers in the second region 7 is set lower than the density in the first region 6 as shown by the graph of Fig. 3 .
  • a relationship of the life time among the three regions in the N - layer 21 is desirably given by the following Equation 1.
  • the life time of the second region 7 is set longer than that of the first region 6 for the following reason.
  • a forward voltage should be prevented from being raised in a state in which a density of a forward current flowing in the third region 2 is not excessively increased.
  • the life time killers for example, it is sufficient that heavy metals such as gold, platinum and the like are selectively diffused into a predetermined region.
  • radioactive rays such as electron beams may be selectively irradiated on the predetermined region.
  • the electron beams should be selectively irradiated on the second region 7.
  • a mask having a pattern shape corresponding to the planar shape of the second region 7 is used.
  • Fig. 4 is a graph showing a reverse recovery operation of the diode according to the first embodiment illustrated in Figs. 1 to 3 .
  • a curve Em1 represents a current waveform of the diode according to the first embodiment.
  • the curve Pr2 related to the diode according to the conventional example 2 is also depicted together.
  • a waveform of a reverse voltage v of the diode according to the first embodiment is shown in a dotted line.
  • the basic flow of the reverse recovery operation is the same as in the conventional examples 1 and 2. More specifically, when switching is performed from a state in which a forward current IF steadily flows to a state in which a reverse bias is applied at a time t0, a current is decreased in a negative direction. As a result, a reverse current flows. In the process in which the reverse current is increased, a depletion layer is generated on the PN junction interface at a time t1, and then grows to shortly cover the whole N - layer 21. Consequently, a reverse voltage v is generated at the time t1, and is then increased and shortly converges on a value of the reverse bias applied from the outside.
  • the reverse current gradually reduces the speed of the increase, shortly passes through a peak and is then decreased.
  • the reverse current converges on zero while continuing the decrease.
  • a transient state that is, the reverse recovery operation comes to an end so that a steady state in which the reverse voltage v is equal to the reverse bias and the reverse current does not flow can be implemented.
  • the basic flow of the reverse recovery operation is the same as in the conventional examples 1 and 2.
  • the life time of the carriers in each of the first region 6 and the second region 7 is set short in the diode according to the first embodiment, the following features are revealed in a reverse recovery characteristic thereof.
  • Fig. 6 is a graph showing the above-mentioned relationship which is obtained based on a simulation. It is understood from the graph that the effect of reducing the revere recovery loss is remarkably obtained when the area factor of the second region 7 exceeds 50 %. Accordingly, it is desirable that the area factor of the second region 7 should be set to 50 % or more.
  • a capacitance C (Em1) equivalently formed on the semiconductor substrate 20 is larger inversely at the last stage of the reverse recovery operation than the capacitance C (Pr2) according to the conventional example 2, and keeps a finite value for a longer period of time.
  • a resistance R (Em1) equivalently formed on the semiconductor substrate 20 is higher than the resistance R (Pr2) according to the conventional example 2. Accordingly, the Q value of the diode according to the first embodiment is smaller at the last stage of the reverse recovery operation than in the conventional example 2. As a result, oscillation is suppressed also at the last stage of the reverse recovery operation. Consequently, the reverse voltage smoothly converges on a steady value without large oscillation as shown in the curve v (Em1) of Fig. 4 .
  • the density of the reverse current flowing in the third region 2 is higher than in the case where the second region 7 is not provided. Therefore, the reverse recovery current I rr is a little larger as shown in the curve Em1 of Fig. 4 than in the conventional example 2. However, this does not so much affect the di / dt capability as to be reduced as compared with the conventional example 2, and the di / dt capability is kept almost equal to that of the conventional example 2.
  • the forward voltage has a little higher value than in the conventional example 2.
  • the forward voltage can have a fully smaller value than in the conventional example 1 as long as the area factor of the second region 7 is not set excessively large.
  • the third region 2 and the second region 7 have such planar shapes (which are projected on the main surface of the semiconductor substrate 20) as to be symmetrical with respect to the center of the main surface and as to cause the second annular region 7 to surround the third circular region 2. Consequently, the distribution of a heat loss caused by the forward current and the reverse current is not biased. In addition, the heat loss is effectively dispersed from the diode element 101 to the post electrodes 11 and 9 and the like provided on the outside thereof.
  • the anode electrode 4 and the cathode electrode 5 are formed to cover almost the whole main surface including a portion in the main surface of the semiconductor substrate 20 where the second region 7 is projected. Therefore, a heat loss generated in the semiconductor substrate 20 is dispersed more effectively from the diode element 101 to the post electrodes 11 and 9 and the like provided on the outside thereof.
  • Figs. 7 to 14 show various variants related to the planar shape of the second region 7.
  • Figs. 7 , 9 , 11 and 13 are sectional views taken along the line B - B in Figs. 8 , 10 , 12 and 14 , respectively.
  • Figs. 8 , 10 , 12 and 14 are sectional views taken along the line A - A in Figs. 7 , 9 , 11 and 13 , respectively.
  • the second region 7 is divided into a plurality of (five in the drawings) unit regions having circular planar shapes respectively, and is provided symmetrically with respect to the center of the semiconductor substrate 20.
  • the second region 7 has a circular planar shape, and the planar shape of the third region 2 is defined annularly to surround the second region 7. More specifically, the second region 7 and the third region 2 are arranged just reversely to those of the diode element 101 shown in Figs. 1 and 2 .
  • the second region 7, the third region 2 and the second region 7 are sequentially provided from the center of a main surface toward the outside with a concentric circles as boundaries.
  • the third region 2, the second region 7, the third region 2 and the second region 7 are sequentially provided from the center of a main surface toward the outside with concentric circles as boundaries.
  • the diode elements 101 and 101b to 101d are common in that the second region 7 and the third region 2 are alternately provided sequentially from the center of the main surface toward the outside with the concentric circles as boundaries. Furthermore, they are also common in that a distribution of a heat loss caused by a forward current and a reverse current is not biased and the heat loss is effectively dispersed from the diode element to the post electrodes 11 and 9 and the like provided on the outside thereof.
  • the heat loss is dispersed more effectively.
  • the uniformity of the heat loss is enhanced still more.
  • the diode element 101d is more excellent in the uniformity of the heat loss than the diode element 101, for example.
  • the diode element 101a is inferior to the diode element 101 and the like in respect of symmetry with respect to the center of the main surface, it is still excellent in the uniformity of the heat loss because the second region 7 is divided.
  • Figs. 15 and 16 are a sectional front view and a sectional plan view which show a diode element forming a main part of the diode according to the first example, respectively.
  • a cut surface of Fig. 15 is taken along the line B - B in Fig. 16
  • a cut surface of Fig. 16 is taken along the line C - C in Fig. 15 .
  • a diode element 102 comprises a semiconductor substrate 20, an anode electrode 4 and a cathode electrode 5.
  • the semiconductor substrate 20 has a P layer 1, an N - layer 21 and an N + layer 3 sequentially provided from an upper main surface toward a lower main surface.
  • a boundary interface between the N - layer 21 and the N + layer 3 is not a plane but has concave and convex portions. More specifically, the boundary interface between the N + layer 3 and the N - layer 21 retreats toward the N + layer 3 side (that is, in a direction of the lower main surface of the semiconductor substrate 20) in a plurality of portions 30.
  • the N + layer 3 includes thick portions 33 and thin portions 34.
  • the N - layer 21 is protruded in portions which are in contact with the thin portions 34, and retreats in portions which are in contact with the thick portions 33.
  • the planar shape of the thin portion 34 that is, a shape projected on the main surface of the semiconductor substrate 20 is desirably circular as shown in Fig. 16 .
  • the thin portions 34 should be set to have the same planar shapes and be arranged at regular intervals to be uniformly distributed along the lower main surface of the semiconductor substrate 20 as shown in Fig. 16 .
  • life time killers are selectively introduced into the semiconductor substrate 20, thereby controlling a life time of carriers.
  • three regions having different life times that is, a first region 6, a second region 31 and a third region 32 are defined in the N - layer 21.
  • the first region 6 occupies a region of the N - layer 21 in the vicinity of a PN junction in the same manner as the first region 6 according to the first embodiment. More specifically, the first region 6 faces the PN junction in the N - layer 21 between the N - layer 21 and the P layer 1 and is defined as a layered region apart from the N + layer 3.
  • the second region 31 is defined as a region adjacent to the opposite side of a PN junction interface of the first region 6. Furthermore, the third region 32 is adjacent to the opposite side of a boundary interface between the second region 31 and the first region 6, and is furthermore in contact with the N + layer 3. In other words, the first region 6, the second region 31 and the third region 32 are provided integrally with each other in this order from the PN junction interface with the P layer 1 toward the boundary interface with the N + layer 3.
  • a boundary interface between the second region 31 and the third region 32 is positioned apart from a tip of the thick portion 33 toward the P layer 1. Accordingly, only the third region 32 comes in contact with the N + layer 3 among the three regions 6, 31 and 32.
  • Fig. 17 is a graph showing a profile of a density of the life time killers introduced into the semiconductor substrate 20.
  • a profile taken along the vertical line X3 - X3 through the thin portion 34 is depicted.
  • the density of the life time killers is selectively high in the first region 6 including the PN junction interface. The reason why the density in the P layer 1 is also high has been described in the first embodiment.
  • the life time killers are also introduced into the second region 31.
  • the density of the life time killers in the second region 31 is set lower than in the first region 6.
  • the life time killers are not substantially introduced into the third region 32.
  • the profile of the life time in the N - layer 21 corresponds to that of the density of the life time killers. Accordingly, a relationship of the life time among the three regions in the N - layer 21 is given by the following Equation 2.
  • an original life time ⁇ 0 of the N - layer 21 is implemented.
  • a life time in the first region 6 is set shorter than the life time ⁇ 0, and a life time ⁇ 1 on the PN junction interface is also set shorter than the life time ⁇ 0.
  • the life time killers can be selectively introduced by the same method as in the first embodiment.
  • the distribution of the life time killers in a direction of the main surface of the semiconductor substrate 20 is uniform. Differently from the first embodiment, therefore, a mask pattern is not required.
  • a local life time control technique should be applied to the introduction of the life time killers into the second region 31.
  • charged particles such as accelerated light ions are irradiated on the semiconductor substrate 20.
  • the life time killers are locally introduced in the vicinity of a range of the charged particle which is determined by an accelerating energy.
  • Fig. 18 is a graph showing a reverse recovery operation of the diode according to the first example illustrated in Figs. 15 to 17 .
  • a curve Em2 represents a current waveform of the diode according to the first example.
  • the curve Pr2 related to the diode according to the conventional example 2 is also depicted. Since a waveform of a reverse voltage v of the diode is almost the same as in the first embodiment, it is omitted.
  • the life time of the carriers in each of the first region 6 and the second region 31 is set short. Therefore, a reverse recovery characteristic has the following features. Since the life time is set short in the first region 6, a reverse recovery current I rr is reduced in the same manner as in the conventional example 2. Furthermore, the second region 31 having a life time set short is provided. Therefore, the recombination of residual carriers is promoted also in the process in which a depletion layer is enlarged beyond the first region 6.
  • the life time killers are not introduced into the third region 32 adjacent to the N + layer 3. Therefore, excess carriers are annihilated with difficulty in the third region 32. For this reason, the carriers are annihilated with difficulty at a stage in which the depletion layer approaches the N + layer 3, that is, the last stage of the reverse recovery operation.
  • the thin portions 34 in the N + layer 3, that is, portions of the boundary interface between the N + layer 3 and the third region 32 which retreat toward the lower main surface of the semiconductor substrate 20 are present.
  • the capacitance C is larger than the capacitance C (Pr2) of the conventional example 2 at the last stage of the reverse recovery operation and keeps a finite value for a longer period of time in the same manner as the capacitance C (Em1) shown in Fig. 5 . Also at the last stage of the reverse recovery operation, accordingly, oscillation is suppressed, and a reverse voltage smoothly converges on a steady value without great oscillation in the same manner as the curve v (Em1) shown in Fig. 4 .
  • the semiconductor substrate 20 should be as thin as possible in order to reduce a forward voltage.
  • the diode according to the first example it is possible to effectively suppress the oscillation without increasing the thickness of the semiconductor substrate 20, that is, without sacrificing the forward voltage.
  • the N + layer 3 becomes thin all over, a leak current in a steady state which is obtained after the reverse recovery operation is increased.
  • the N + layer 3 is partially thin. Therefore, the oscillation can effectively be suppressed without increasing the leak current. This fact has also been confirmed by a simulation as will be described below.
  • Fig. 19 is a partially enlarged sectional view showing the N + layer 3 and the vicinity thereof which are enlarged.
  • the planar shape of the thin portion 34 is circular as described above, and has a diameter represented by w1.
  • Fig. 20 is a graph showing data obtained based on a simulation for a relationship between the diameter w1 and a leak current (leakage current) in a steady state.
  • the leak current is almost constant with the diameter w1 ranging from 0 to 50 ⁇ m, and is rarely affected by the existence of the thin portion 34.
  • the diameter w1 exceeds about 50 ⁇ m, the leak current is rapidly increased. Accordingly, it is desirable that the diameter w1 of the thin portion 34 should be set to 50 ⁇ m or less in order not to increase the leak current. In the case where the planar shape of the thin portion 34 is not circular, the increase in the leak current can similarly be prevented if a maximum diameter is set to 50 ⁇ m or less.
  • Fig. 21 is a graph showing data obtained by confirming this fact based on a simulation.
  • An area factor of the thin portions 34 means a ratio of an area occupied by a region where the thin portions 34 are projected to the lower main surface of the semiconductor substrate 20.
  • the forward voltage is rarely affected by the thin portions 34 with the area factor of the thin portions 34 ranging from 0 to 50 %.
  • the area factor of the thin portions 34 ranging from 0 to 50 %.
  • the forward voltage is remarkably increased. Accordingly, it is desirable that the area factor of the thin portions 34 should be set to 50 % or less in order not to increase the forward voltage.
  • the life time is set short in the second region 31 as well as the first region 6. Therefore, a resistance for the forward current is increased a little more than in the conventional example 2.
  • the forward voltage has a little higher value than in the conventional example 2 by the influence of the second region 31.
  • the diode according to the first example it is possible to simultaneously implement a high di / dt capability, a low reverse recovery loss and a comparatively low forward voltage. Furthermore, the voltage oscillation can be prevented in the process of the reverse recovery operation.
  • the N - layer 21 is thinner in the vicinity of the thick portions 33 than the vicinity of the thin portions 34, and a resistance component of the N - layer 21 is correspondingly reduced. Accordingly, when the forward current flows, a current density is more increased in the thick portions 33 than in the thin portions 34. When a transition to the reverse recovery operation is started in this state, the reverse current also concentrates more easily in the thick portions 33 than in the thin portions 34.
  • the thin portions 34 have the same planar shapes and are arranged at regular intervals uniformly distributed along the lower main surface of the semiconductor substrate 20. Consequently, the concentration of the reverse current can be relieved. Thus, it is possible to prevent a reduction in a blocking capability from being caused by an increase in a local loss.
  • the boundary interface between the second region 31 and the third region 32 is positioned apart from the tips of the thick portions 33 toward the P layer 1. More specifically, a space d1 between the boundary interface of the second region 31 and the third region 32 and the lower main surface of the semiconductor substrate 20 is set larger than a thickness d2 of the thick portions 33 as shown in Fig. 19 . Consequently, the capacitance C equivalently formed on the semiconductor substrate 20 keeps a finite value for a longer period of time in the last stage of the reverse recovery operation. Consequently, oscillation can be suppressed more effectively.
  • an impurity concentration of the N + layer 3 should be set to 1 ⁇ 10 18 n / cm 3 or more on an exposed surface 37 in the lower main surface of the semiconductor substrate 20 where the thick portions 33 are exposed. Consequently, a good ohmic contact can be implemented between the N + layer 3 and the cathode electrode 5. Furthermore, it is also possible to employ a simple manufacturing method in which the thick portions 33 and the thin portions 34 are formed simply by selectively introducing an N type impurities into only the exposed surface 37 in the lower main surface of the semiconductor substrate 20 and then diffusing the same N type impurities when forming the N + layer 3.
  • the thickness d3 of the thin portions 34 can also be set to 5 ⁇ m or less, for example, without increasing the leak current.
  • the thickness d3 can also be set to 0 as shown in Fig 22 .
  • the thickness d3 it is possible to bring out the effect of suppressing the oscillation at the maximum without increasing the thickness of the semiconductor substrate 20. It is desirable that the thickness d2 of the thick portion 33 should be set to 50 ⁇ m or more.
  • Fig. 23 is a partially enlarged sectional view showing a variant related to the thickness of the third region 32.
  • the second region 31 has a greater thickness than in the example of Fig. 19 . Therefore, the reverse recovery current is attenuated more quickly as shown in a curve Em2a of Fig. 24 so that a reverse recovery loss can be reduced still more.
  • the third region 32 has a larger thickness in the example illustrated in Fig. 19 . Therefore, the effect of suppressing oscillation is more excellent in the example of Fig. 19 . It is possible to widely select the space d1 depending on intended use.
  • Figs. 25 and 26 are a sectional front view and a sectional plan view which show a diode element forming a main part of the diode according to the second example, respectively.
  • a cut surface of Fig. 25 is taken along the line B - B in Fig. 26
  • a cut surface of Fig. 26 is taken along the line D - D in Fig. 25 .
  • a structure of a diode element 103 according to the present example is just similar to a structure obtained by keeping the profile of the life time killers in its entirety and replacing the shapes of the P layer 1 and the N + layer 3 with each other in the diode element 102 as will be described below.
  • the diode element 103 also comprises a semiconductor substrate 20, an anode electrode 4 and a cathode electrode 5.
  • the semiconductor substrate 20 has a P layer 1, an N - layer 21 and an N + layer 3 sequentially provided from an upper main surface toward a lower main surface.
  • a PN junction interface between the P layer 1 and the N - layer 21 is not a plane but has concave and convex portions. More specifically, a PN junction interface retreats toward the P layer 1 side (that is, in a direction of the upper main surface of the semiconductor substrate 20) in a plurality of portions 50.
  • the P layer 1 includes thin portions 51 and thick portions 52.
  • the N - layer 21 is protruded in portions which are contact with the thin portions 51, and retreats in portions which are in contact with the thick portions 52.
  • the planar shape of the thin portion 51 that is, a shape projected on the main surface of the semiconductor substrate 20 is desirably circular as shown in Fig. 26 .
  • the thin portions 51 should be set to have the same planar shapes and be arranged at regular intervals to be uniformly distributed along the upper main surface of the semiconductor substrate 20 as shown in Fig. 26 .
  • a life time killers are selectively introduced into three regions having different life times, that is, a first region 53, a second region 54 and a third region 55 are defined in the N - layer 21.
  • the first region 53 occupies a region of the N - layer 21 in the vicinity of a PN junction in the same manner as the first region 6 according to the first embodiment and first examples. More specifically, the first region 53 faces the PN junction in the N - layer 21 between the N - layer 21 and the P layer 1 and is defined as a layered region apart from the N + layer 3.
  • the second region 54 is defined as a region adjacent to the opposite side of a PN junction interface of the first region 53. Furthermore, the third region 55 is adjacent to the opposite side of a boundary interface between the second region 54 and the first region 53, and is furthermore in contact with the N + layer 3. In other words, the first region 53, the second region 54 and the third region 55 are provided integrally with each other in this order from the PN junction interface with the P layer 1 toward a boundary interface with the N + layer 3.
  • the boundary interface between the first region 53 and the second region 54 is positioned not apart from tips of the thick portions 52 toward the N + layer 3. Accordingly, both the first region 53 and the second region 54 come in contact with the P layer 1, thereby forming a PN junction interface.
  • Fig. 27 is a graph showing a profile of a density of the life time killers introduced into the semiconductor substrate 20.
  • a profile taken along the vertical line X4 - X4 through the thin portion 51 is depicted.
  • the density of the life time killers is selectively high in the first region 53 including the PN junction interface. The reason why the density in the P layer 1 is also high has been described in the first embodiment.
  • the life time killers are also introduced into the second region 54.
  • the density of the life time killers in the second region 54 is set lower than in the first region 53.
  • the life time killers are not substantially introduced into the third region 55. Accordingly, a relationship of the life time among the three regions in the N - layer 21 is given by the following Equation 3.
  • an original life time ⁇ 0 of the N - , layer 21 is implemented.
  • a life time in the first region 53 is set shorter than the life time ⁇ 0, and a life time on the PN junction interface is also set shorter than the life time ⁇ 0.
  • the life time killers can be selectively introduced by the same method as in the first example.
  • Fig. 28 is a graph showing a reverse recovery operation of the diode according to the second example illustrated in Figs. 25 to 27 .
  • a curve Em3 represents a current waveform of the diode according to the second example.
  • the curve Pr2 related to the diode according to the conventional example 2 is also depicted.
  • the PN junction interface is provided with concave and convex portions. Therefore, an area of the PN junction interface is increased. For this reason, a large quantity of carriers are injected into the N - layer 21. As a result, it is possible to obtain an advantage that a forward voltage can be reduced. On the other hand, since the quantity of the carriers is large, the annihilation of residual carriers is delayed in the reverse recovery operation. Consequently, a reverse recovery current I rr is larger than in the conventional example 2.
  • the diode can implement a low forward voltage by setting the PN junction interface between the P layer 1 and the N - layer 21 in the conventional example 1 to have the same shape as in the second example, a current waveform is represented by a curve Cm in Fig. 28 .
  • the reverse recovery current I rr is remarkably increased as shown in the curve Cm.
  • a reverse recovery loss has a large value. More specifically, a forward characteristic can be improved but fewer advantages of a reverse recovery characteristic can be gained with the PN junction interface having the concave and convex portions.
  • the PN junction interface is provided with the concave and convex portions and a life time is set short in the first region 53 adjacent to the PN junction interface so that the reverse recovery characteristic can be prevented from being deteriorated.
  • the reverse recovery current I rr can be reduced.
  • the PN junction interface is provided with the concave and convex portions so that disadvantages which are secondarily produced can be relieved or eliminated and the forward characteristic can be improved while suppressing the deterioration in the reverse recovery characteristic such as a di / dt capability.
  • the second region 54 having a life time set short is provided, the recombination of the residual carriers can be promoted also in the process in which a depletion layer is enlarged beyond the first region 53.
  • the attenuation of the reverse recovery current can be more promoted as shown in the curve Em3 than in the conventional example 2 (curve Pr2). Consequently, an increase in the reverse recovery current Irr is not exactly linked with an increase in the reverse recovery loss. In other words, the reverse recovery loss does not have a much larger value than in the conventional example 2.
  • Fig. 29 is a partially enlarged sectional view showing the P layer 1 and the vicinity thereof which are enlarged.
  • the planar shape of the thin portion 51 is circular as described above, and has a diameter represented by w2.
  • the N - layer 21 is thinner than in the vicinity of the thin portions 51 so that a resistance component of the N - layer 21 is correspondingly reduced. Accordingly, when a forward current flows, a current density is higher in the thick portions 52 than in the thin portions 51.
  • a reverse current also concentrates more easily in the thick portions 52 than in the thin portions 51.
  • the thin portions 51 have the same planar shapes and are arranged at regular intervals to be uniformly distributed along the upper main surface of the semiconductor substrate 20. Consequently, the concentration of the reverse current can be relieved. Thus, it is possible to prevent a reduction in a blocking capability from being caused by an increase in a local loss.
  • the boundary interface between the first region 53 and the second region 54 is positioned rearward apart from the tips of the thick portions 52 toward the upper main surface of the semiconductor substrate 20. More specifically, a space d4 between the boundary interface of the first region 53 and the second region 54 and the upper main surface of the semiconductor substrate 20 is set smaller than a thickness d5 of the thick portions 52 as shown in Fig. 29 . For this reason, a forward voltage can be reduced effectively. Moreover, it is desirable that the thickness d5 should be set to 50 ⁇ m or more. be set to 50 ⁇ m or more.
  • Fig. 30 is a graph showing data obtained based on a simulation for a relationship of the leak current and forward voltage to the diameter w2. As shown by the graph, the leak current is almost constant with the diameter w2 ranging from 0 to 50 ⁇ m and is rarely affected by the existence of the thin portion 51.
  • the diameter w2 of the thin portion 51 should be set to 50 ⁇ m or less in order not to increase the leak current.
  • the leak current can similarly be prevented from being increased if a maximum diameter is set to 50 ⁇ m or less.
  • the forward voltage has a minimum value.
  • the diameter w2 ranges from about 20 ⁇ m to about 40 ⁇ m, the forward voltage is rarely affected by a change in the diameter w2 but almost keeps the minimum - value. Therefore, it is desirable that the diameter w2 should be set to about 20 ⁇ m to about 40 ⁇ m in consideration of both the forward voltage and the leak current.
  • the ratio of the P layer 1 occupied by the thin portions 51 also affects the leak current and the forward voltage.
  • Fig. 31 is a graph showing data obtained by confirming this fact based on a simulation.
  • An area factor of the thin potions 51 means a ratio of an area occupied by a portion where the thin portions 51 are projected to the upper main surface of the semiconductor substrate 20.
  • the leak current is rarely affected by the thin portions 51 with the area factor of the thin portions 51 ranging from 0 to 50 %.
  • the area factor exceeds 50 %, the leak current is remarkably increased. 50 % or less in order not to increase the leak current.
  • the forward voltage has a minimum value.
  • the area factor of the thin portions 51 should be set to about 25 % to about 45 % in consideration of both the forward voltage and the leak current.
  • an impurity concentration in the P layer 1 should be set to 1 X 10 17 n / cm 3 or more on an exposed surface 57 in the upper main surface of the semiconductor substrate 20 where the thick portions 52 are exposed. Consequently, a good ohmic contact can be realized between the P layer 1 and the anode electrode 4. Furthermore, it is also possible to employ a simple manufacturing method in which the thick portions 52 and the thin portions 51 are formed simply by selectively introducing a P type impurities into only the exposed surface 57 in the upper main surface of the semiconductor substrate 20 and then diffusing the same P type impurities when forming the P layer 1.
  • the boundary interface between the second region 54 and the third region 55 may be positioned apart from the tips of the thick portion 52 toward the N + layer 3. More specifically, the space d4 may be set larger than the thickness d5 of the thick portions 52 as shown in Fig. 32 . As compared with the example of Fig. 29 , consequently, the forward voltage is somewhat deteriorated but the reverse recovery current I rr can be reduced and the di / dt capability can be improved.
  • Fig. 33 collectively shows the quality of each of parameters for evaluating the
  • Fig. 33 collectively shows the quality of each of parameters for evaluating the characteristic of the diode in the form of a table according to each of the above-mentioned embodiment and examples. For comparison, the quality of each of parameters according to the conventional examples 1 and 2 is also described.
  • items in which preferred characteristics can be obtained are shown by hatching.
  • Each of the above-mentioned embodiments can properly be carried out in combination with each other. Thereby a mean value for each parameter can be obtained. In other words, the degree of design freedom can be increased in consideration of the combination.
  • a diode element having both features of the diode elements 102 and 103 as shown in Fig. 34 .
  • a P layer 1 provided in a semiconductor substrate 20 is equivalent to the P layer 1 of the diode element 103.
  • An N - layer 21 and an N + layer 3 are formed equivalently to corresponding semiconductor layers of the diode element 102, respectively.
  • the P layer 1 includes a thin portions 51 and thick portions 52, and the N + layer 3 also includes a thick portions 33 and thin portions 34.
  • the N - layer 21 has a first region 6, a second region 31 and a third region 32 formed thereon. A profile of a life time in each of these three regions is given by Fig. 17 .
  • the diode element 104 has both the features of the diode elements 102 and 103. Therefore, it is possible to obtain a mean value for each parameter shown in Fig. 33 .
  • the diode according to the first embodiment it is also possible to employ a configuration in which the semiconductor substrate 20 does not comprise the N + layer 3.
  • the N - layer 21 is exposed to the lower main surface of the semiconductor substrate 20 and the cathode electrode 5 is directly connected to the N - having such a structure and a distribution of a density of life time killers to be introduced.
  • the distribution of the density of the life time killers on the N - layer 21 is equal to that on the N - layer 21 according to the first embodiment shown in Fig. 3 .
  • the N - layer 21 has a first region 6, a second region 7 and a third region 2 formed thereon in the same manner as the N - layer 21 of the diode element 101.
  • the device according to the first embodiment comprises the N + layer 3, it is more excellent in that a punch through can be suppressed to raise a breakdown voltage with the semiconductor substrate 20 set thin.

Claims (6)

  1. Diode, die folgendes aufweist:
    - ein Halbleitersubstrat (20), das eine obere Hauptfläche und eine untere Hauptfläche bildet;
    - eine erste Hauptelektrode (4), die mit der oberen Hauptfläche verbunden ist; und
    - eine zweite Hauptelektrode (5), die mit der unteren Hauptfläche verbunden ist,
    - wobei das Halbleitersubstrat (20) eine erste und eine zweite Halbleiterschicht (1, 21) aufweist, die nacheinander von der oberen Hauptfläche in Richtung zu der unteren Hauptfläche vorgesehen sind,
    - wobei die erste Halbleiterschicht (1) einen ersten Leitfähigkeits-Typ aufweist und zu der oberen Hauptfläche hin freiliegt,
    - wobei die zweite Halbleiterschicht (21) einen zweiten Leitfähigkeits-Typ aufweist,
    - wobei die zweite Halbleiterschicht (21) in eine erste, eine zweite und eine dritte Region (6, 7, 2) unterteilt ist,
    - wobei die erste Region (6) der ersten Halbleiterschicht (1) zugewandt gegenüberliegt und zusammen mit der ersten Halbleiterschicht (1) einen PN-Übergang bildet, und
    - wobei die zweite Region (7) und die dritte Region (2) einen Bereich in der zweiten Halbleiterschicht (12) einnehmen, der an die erste Region (6) angrenzt und diese erste Region (6) zusammen mit der ersten Halbleiterschicht (1) sandwichartig einschließt und der sich näher bei der unteren Hauptfläche befindet als die erste Region (6), sowie den genannten Bereich zwischeneinander in einer zu der oberen Hauptfläche parallelen Richtung gegenseitig unterteilen, und
    - wobei die Lebensdauer von Ladungsträgern in der zweiten Halbleiterschicht (21) in der ersten Region (6) und der zweiten Region (7) kürzer vorgegeben ist als in der dritten Region (2).
  2. Diode nach Anspruch 1,
    wobei das Halbleitersubstrat (20) ferner eine dritte Halbleiterschicht (3) aufweist, die an die zweite Halbleiterschicht (21) angrenzt und zu der unteren Hauptfläche freiliegt, wobei die dritte Halbleiterschicht (3) einen zweiten Leitfähigkeits-Typ aufweist und eine höhere Dotierstoffkonzentration hat als die zweite Halbleiterschicht (21).
  3. Diode nach Anspruch 1,
    wobei die Lebensdauer in der zweiten Region (7) länger vorgegeben ist als in der ersten Region (6).
  4. Diode nach Anspruch 1,
    wobei das Verhältnis der zweiten Region (7) zu der dritten Region (2) 50 % oder mehr beträgt.
  5. Diode nach Anspruch 1,
    wobei die zweite Region (7) in der zu der oberen Hauptfläche parallelen Richtung in eine Vielzahl von regionalen Einheiten (7) unterteilt ist.
  6. Diode nach Anspruch 1,
    wobei der Bereich der zweiten Halbleiterschicht (21) in eine Vielzahl von Regionen unterteilt ist, die von einem Zentrum in Richtung nach außen in der zu der oberen Hauptfläche parallelen Richtung derart angeordnet sind, daß die Regionen jeweils nacheinander von einer nächsten Region umgeben sind und die zweite Region (7) und die dritte Region (2) abwechselnd in jeder der Regionen angeordnet sind.
EP98923079A 1998-06-01 1998-06-01 Diode Expired - Lifetime EP1026754B1 (de)

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DE10052170C2 (de) * 2000-10-20 2002-10-31 Infineon Technologies Ag Mittels Feldeffekt steuerbares Halbleiterbauelement
US7211846B2 (en) 2000-10-20 2007-05-01 Infineon Technologies Ag Transistor having compensation zones enabling a low on-resistance and a high reverse voltage
JP2010098189A (ja) * 2008-10-17 2010-04-30 Toshiba Corp 半導体装置
EP2320451B1 (de) * 2009-11-09 2013-02-13 ABB Technology AG Schnelle Diode
CN104303285B (zh) 2012-08-22 2017-03-01 富士电机株式会社 半导体装置以及半导体装置的制造方法
JP2014063980A (ja) 2012-08-30 2014-04-10 Toshiba Corp 半導体装置
JP6846119B2 (ja) * 2016-05-02 2021-03-24 株式会社 日立パワーデバイス ダイオード、およびそれを用いた電力変換装置
CN110112209A (zh) * 2019-06-10 2019-08-09 洛阳鸿泰半导体有限公司 一种基于三维半导体晶圆的快恢复二极管结构

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DE2917786C2 (de) * 1979-05-03 1983-07-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Thyristortriode und Verfahren zu ihrer Herstellung
JPS5678127A (en) * 1979-11-30 1981-06-26 Toshiba Corp Manufacture of semiconductor device
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EP0398120B1 (de) * 1989-05-18 1993-10-13 Asea Brown Boveri Ag Halbleiterbauelement
KR0149840B1 (ko) 1989-11-29 1998-10-01 빈센트 죠셉 로너 고속 댐퍼 다이오드 및 방법
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JP3488599B2 (ja) * 1996-10-17 2004-01-19 株式会社東芝 半導体装置

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EP1026754A1 (de) 2000-08-09
EP1780799B9 (de) 2012-02-29
EP1026754A4 (de) 2000-08-09
JP4267083B2 (ja) 2009-05-27
EP1780799A3 (de) 2008-04-23
US6218683B1 (en) 2001-04-17
EP1780799A2 (de) 2007-05-02
DE69842207D1 (en) 2011-05-12
WO1999063597A1 (fr) 1999-12-09

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