EP0936569A1 - Procédé et dispositif de circuit pour multiplication de fréquence - Google Patents

Procédé et dispositif de circuit pour multiplication de fréquence Download PDF

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Publication number
EP0936569A1
EP0936569A1 EP98102333A EP98102333A EP0936569A1 EP 0936569 A1 EP0936569 A1 EP 0936569A1 EP 98102333 A EP98102333 A EP 98102333A EP 98102333 A EP98102333 A EP 98102333A EP 0936569 A1 EP0936569 A1 EP 0936569A1
Authority
EP
European Patent Office
Prior art keywords
circuit
input
chebyshev
output
modules
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98102333A
Other languages
German (de)
English (en)
Inventor
Klaus Dr.-Ing. Huber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Telekom AG
Original Assignee
Deutsche Telekom AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE19701067A priority Critical patent/DE19701067B4/de
Application filed by Deutsche Telekom AG filed Critical Deutsche Telekom AG
Priority to US09/022,017 priority patent/US6304997B1/en
Priority to EP98102333A priority patent/EP0936569A1/fr
Publication of EP0936569A1 publication Critical patent/EP0936569A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/22—Arrangements for performing computing operations, e.g. operational amplifiers for evaluating trigonometric functions; for conversion of co-ordinates; for computations involving vector quantities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/20—Arrangements for performing computing operations, e.g. operational amplifiers for evaluating powers, roots, polynomes, mean square values, standard deviation

Definitions

  • the invention relates to a method and a circuit arrangement according to the preamble of claim 1 or of claim 3.
  • Chebyshev polynomials are for example described in I. Schur, "Arithmetic about the Teschebyscheffschen Polynome", Collected Treatises Vol. III, pages 422 to 453, Springer Verlag 1973.
  • the invention has for its object a method and a circuit arrangement for analog frequency multiplication to create the means simple and easy combinable building blocks the frequency multiplication reach and especially the previous ones Avoid division circuits when multiples of one Fundamental frequency to be generated, which is not a Power of two are.
  • the method according to the invention or the one according to the invention Device has the advantage that by Structures derived from Chebyshev's polynomials Frequency multiplication is achieved using simple and easily combinable building blocks or modular Circuit structures is achieved.
  • Chebyshev polynomials as well as the multipliers and summers or add or subtract circuits required for the implementation in terms of circuitry can be implemented in integrated circuitry, which can then perform the most varied of functions depending on the external wiring or networking.
  • Other functions that can be easily implemented with such a chip are the synthesis of any function curves by representing the function using a Chebyshev series or the use of the function T n (x) as an amplifier with the gain factor n for small x sin (nx) ⁇ nx , and called odd n.
  • the circuit for equation (2) according to FIG. 1, which is constructed and implemented on this basis, consists of two series-connected Chebyshev modules 1 and 2, the input variable being at the base frequency at the input of the Chebyshev module 1 and the output variable at the output of the Chebyshev module 2 Factor n ⁇ m multiplied frequency.
  • the implementation of equation (3) is shown in Fig. 2.
  • This circuit consists of the Chebyshev modules 3, 4 and 5, the inputs of which are all fed with the input variable at the fundamental frequency.
  • the outputs of the Chebyshev modules 3 and 4 are routed to the input of a multiplier 7, at the further input of which a 2 is present for multiplication.
  • the output of the multiplier 7 is passed with the output of the Chebyshev module 5 to a subtractor 8, at the output of which the function T n + m (x) is then present if the function T nm (x) is realized in the Chebyshev module 5 and T nm ( x) if the function T n + m (x) is implemented in the Chebyshev module 5.
  • the Chebyshev module T N (x) can now be assembled from the circuits in FIGS. 1 and 2.
  • N there are different implementation options.
  • the respective implementation is to be selected by the specialist depending on the costs.
  • an implementation using operational amplifiers is assumed.
  • the specified circuits are not necessarily equally well suited for every application.
  • other realizations may be possible without further ado and may be cheaper in the given case.
  • the design can easily be modified and tailored to the corresponding application.
  • the circuit according to FIG. 4 for the implementation of the function T 3 (x) again consists of a squarer 9, a downstream multiplier 7 and an operational amplifier 10, the output signal of which is fed back to its input via a voltage divider consisting of resistors 14 and 15 is.
  • the corresponding electrical variables of the function T 3 (x) are available at the output of this circuit.
  • K 17th 3K 2nd + 2K 3rd + K (p 2nd )
  • the costs K (S 1 ) for realizing equation (2) are set at zero here.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Algebra (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP98102333A 1997-01-15 1998-02-11 Procédé et dispositif de circuit pour multiplication de fréquence Withdrawn EP0936569A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE19701067A DE19701067B4 (de) 1997-01-15 1997-01-15 Verfahren und Schaltungsanordnung zur Frequenzvervielfachung
US09/022,017 US6304997B1 (en) 1997-01-15 1998-02-11 Method and circuit arrangement for multiplying frequency
EP98102333A EP0936569A1 (fr) 1997-01-15 1998-02-11 Procédé et dispositif de circuit pour multiplication de fréquence

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19701067A DE19701067B4 (de) 1997-01-15 1997-01-15 Verfahren und Schaltungsanordnung zur Frequenzvervielfachung
US09/022,017 US6304997B1 (en) 1997-01-15 1998-02-11 Method and circuit arrangement for multiplying frequency
EP98102333A EP0936569A1 (fr) 1997-01-15 1998-02-11 Procédé et dispositif de circuit pour multiplication de fréquence

Publications (1)

Publication Number Publication Date
EP0936569A1 true EP0936569A1 (fr) 1999-08-18

Family

ID=27217026

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98102333A Withdrawn EP0936569A1 (fr) 1997-01-15 1998-02-11 Procédé et dispositif de circuit pour multiplication de fréquence

Country Status (3)

Country Link
US (1) US6304997B1 (fr)
EP (1) EP0936569A1 (fr)
DE (1) DE19701067B4 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3852746B2 (ja) * 2001-03-08 2006-12-06 インターナショナル・ビジネス・マシーンズ・コーポレーション データ補正装置及びデータ補正方法
US20040115995A1 (en) * 2002-11-25 2004-06-17 Sanders Samuel Sidney Circuit array module
US7119588B2 (en) * 2005-01-28 2006-10-10 James Wayne Kelley Circuit for multiplying continuously varying signals
DE102005006717B3 (de) 2005-02-04 2006-08-03 Atmel Germany Gmbh Kettenverstärker

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2086627A (en) * 1980-10-30 1982-05-12 Bei Electronics Multiplying circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163960A (en) * 1976-12-30 1979-08-07 Societe Lignes Telegraphiques Et Telephoniques Electromechanical filter structure
FR2461403A1 (fr) * 1979-07-13 1981-01-30 Lignes Telegraph Telephon Structure perfectionnee de cellules de filtre electromecanique et filtres passe-bande les incorporant
DE3231919A1 (de) * 1982-08-27 1984-03-01 Robert Bosch Gmbh, 7000 Stuttgart Aktive niederfrequenz-tiefpassfilteranordnung
DE3303133A1 (de) * 1983-01-31 1984-08-02 Siemens AG, 1000 Berlin und 8000 München Generator zur erzeugung einer sinusfoermigen spannung mit einer unter zwei festwerten waehlbaren frequenz

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2086627A (en) * 1980-10-30 1982-05-12 Bei Electronics Multiplying circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VON HUBER K: "On applications of Chebyshev polynomials in circuit design", FREQUENZ, JAN.-FEB. 1998, FACHVERLAG SCHIELE & SCHON, GERMANY, vol. 52, no. 1-2, ISSN 0016-1136, pages 11 - 13, XP002067845 *

Also Published As

Publication number Publication date
DE19701067A1 (de) 1998-07-16
DE19701067B4 (de) 2007-06-28
US6304997B1 (en) 2001-10-16

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