EP0853817A1 - Module electronique a conception avancee de plages de connexion - Google Patents

Module electronique a conception avancee de plages de connexion

Info

Publication number
EP0853817A1
EP0853817A1 EP96932706A EP96932706A EP0853817A1 EP 0853817 A1 EP0853817 A1 EP 0853817A1 EP 96932706 A EP96932706 A EP 96932706A EP 96932706 A EP96932706 A EP 96932706A EP 0853817 A1 EP0853817 A1 EP 0853817A1
Authority
EP
European Patent Office
Prior art keywords
substrate
parts
electronic package
pad
tne
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96932706A
Other languages
German (de)
English (en)
Inventor
Francesco Garbelli
Stefano Oggioni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0853817A1 publication Critical patent/EP0853817A1/fr
Ceased legal-status Critical Current

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions

  • the present invention relates to an electronic package and particularly, but not exclusively, to an electronic package including a substrate and at least one device, each of said at least one device being attached to said substrate by means of a conductive pad provided on a surface of said substrate.
  • An electronic package typically includes a circuitized substrate w th one or more active devices attached thereon; packages including only one device are known as Single Chip Modules (SCM) , while packages including a plurality of devices are called Multi Chip Modules (MCM) .
  • SCM Single Chip Modules
  • MCM Multi Chip Modules
  • attach materials such as a glue
  • BGA Ball Grid Array
  • BGA packages are a quite recent development in the electronic packaging industry replacing the current products as the Quad Flat PacKs (QFP) .
  • the main difference is the connection system to tne printed circuit board (PCB), also called second level attachment, that is made through eutectic Tin Lead alloy balls arranged in a matrix layout on the bottorr side of a substrate, instead of metal leads placed along tne per ⁇ phera_ corner of the plastic component body.
  • PCB printed circuit board
  • QFP packages are described m "Circuits Assembly (USA) - Vol.6, No.3 March 1995 Pag.38 40".
  • EacJn device is comror.ly attached tc tr.e s.cstrate cy reans of a conductive pad, typically a little bigger t.at tr.e corresponding attacne ⁇ device, provided on the top surface of tne s-Dstrate.
  • Tnese pads provide a better compatibility with the glue material; m addition, tney facilitate for some extent the heat transfer from the cack of the device into the substrate by conduction.
  • a drawback of the prior art is that each pad causes a waste of a big area on the top surface of the substrate that cannot be wired and then it is not at all available for the routing of connecting lines. This problem is particularly serious m a Multi Chip Module, wherein the wasted area not available for wiring has to be multiplied by the number of devices. This problem involves increasing the electronic package dimensions or reducing the number of devices installed on the same substrate, increasing the number of modules required for the same application.
  • tnis solution causes a degradation of the thermal performances of the pac age, particularly m organic substrates, with a value of thermal dissipation typically not greater than 0.5 W.
  • a different approach is to modify the substrate, either changing the raw-materials and technologies toward more conductive ones, like ceramic carriers, or increasing the number of layers thereof; both solutions however are more expensive and increases the cost of the whole package.
  • a further problem is that these modules, as any other electronic components, need to be decoupled with capacitors to reduce signal noise either at the application board level or at module substrate.
  • the signal noise optimisation is usually addressed oridging witn capacitors power and ground as close as possible to the active device, when these capacitors are on board at the package level, they require a specific wiring pattern and than impact tne already small real estate available for the circuitry, enlarging consequently the total module dimensions.
  • the capacitors are assembled on tne mother board where the modules are, they provide very often a oarely acceptable level of noise reduction.
  • the present invention provides an electronic package as set out above which is characterised in that said pad .s composed by a plurality of parts not contact.
  • This solution allows solving botr. tne aoove er.t-or.e_ proc-e-£ Particularly, it allows increasing the e.ec:r:ca. n.reac...:, of tr_ substrate top layer and enhancing tne electrical s:gr._- ro.se .eve. abatement of the electronic package.
  • tne packaging method involved by tne present invention is fully compatible with the current processes and related equipment used the industry.
  • said plurality of parts are separated by a wireable area of said suDStrate.
  • This free area between each couple of adjacent parts provides one or more wiring channels for the routing of connecting lines, thereby increasing the substrate wireability with regard to the available real estate or overall dimension of the package.
  • This embodiment of the present invention then involves decreasing the electronic package dimensions required for a particular application; on the contrary, it allows a greater number of devices to be installed on the same substrate, decreasing the number of modules required for the same application.
  • said device includes four corners, said pad being composed by four parts and said wireable area having the form of a cross extending from said corners.
  • This shape is particularly advantageous because the density of signals increases greatly at corners; tnerefore, the wiring channels starting from the corners of the device ma ⁇ .e easier the wiring far out.
  • said electronic package is a mult. chip module.
  • the propose ⁇ pad design gets the maximum effect on the overall package costs and performances .
  • At least a first of said parts is connected to a ground potentia.
  • a ⁇ _ a- least a second of sa ⁇ d parts is connected to a power pote't. ⁇ ., ?_.; ⁇ . - and sa ⁇ d second parts Demg connected to eac o.rer r. -ea'f decoupling capac.tor.
  • This solution provides a Detter device decoupling actior It _ .... -. a signal noise abatement for electrical performances .ridging . t capacitors power and ground very close to the active ⁇ evice. Ir. a ⁇ d.tior , this solution does not impact the real estate available on the s ⁇ Dstrate with a dedicated circuitry.
  • said substrate includes at least one conductive hole connected to at least one of said parts.
  • This embodiment of the present invention increases the package thermal dissipation, extending the applicability of this electronic packaging technology to a wider range of applications.
  • the electronic package comprises a further pad provided on a further surface of said substrate, said further pad being composed by a plurality of further parts not in contact, at least one of said further parts being connected to a corresponding one of said parts by means of at least one of said holes.
  • the resulting path is a heat dissipation solution that increases the overall packaging thermal performances and helps in managing very effectively the thermal dissipation factor for the device.
  • the result is a generalised spread of the heat that may be easily dissipated into the mother board.
  • said substrate includes a ground layer and a power layer, said first part being connected to said ground layer by means of a first of said holes and said second part being connected to said power layer by means of a second of said holes.
  • connections to tne decoupling capacitor may be achieved through via on pads design with no extra wiring required beyond the drilled holes to drive the connections from tne inner layers (power or ground) to the top surface of the laminate; the capacitors may then be assembled close to the device, enhancing the device electrical performances and allowing an ideal device decoupling.
  • this connection further enhances the heat dissipation factor of the package through the metallic ground and power planes and extends the thermal dissipation factor to all the ground module connections toward the mother board interface.
  • sa ⁇ first part is connected to said ground potential oy means of a corresponding first of said further parts and said second part is connected to said power potential by means of a corresponding second of said further parts.
  • Different types of electronic packages may be used to implement the present invention, such as QFP, BGA, either SCM or MCM; typically, said electronic package is a BGA.
  • Fig. 1 is an electronic pacKage according to the prior art
  • Fig. 2 depicts an electronic package according to an embodiment of the present invention
  • Fig. 3 is an electronic package with increased thermal dissipation
  • Fig. 4a and 4b show an electronic package with a device decoupling
  • Fig. 5 depicts a further electronic package with a device decoupling.
  • FIG. 1 a cross sectional view of an electronic package according tc the prior art is snown.
  • the figure depicts particularly a BGA 100 .nclud.rg a device 110 attached to a circuitized suostrate 120 by means of a glue layer.
  • the substrate 120 is provided on its bottom side with a plurality of connecting balls or Dumps 130 arranged a matrix layout; the connecting balls 130 are typically eutectic solder, such as T.r. Lead alloy.
  • These balls 130 are used to connect the BGA package to a Prmte ⁇ Circuit Board (not shown) .
  • Plastic Ball Grid Array (PBGA) , Ceramic Ball Grid Array (CBGA) and Tape Ba] 1 Grid Array (TBGA) , tne primary difference Demg the type cf s.c.-r ' material .
  • PBGA Plastic Ball Grid Array
  • CBGA Ceramic Ball Grid Array
  • the device 1 C .s attached to tr.e s ⁇ cstrate " .2 D/ re.-. . • . conductive pad 140 provided on the top surface cf tr.e s_t5Str_t- area, usually a little Digger tnan the device 11C, allows a c.tter compatibility with the glue material and facilitates tne neat transic from the back of the device 110 into the substrate 120 by cor.d-ction.
  • the device 110 is wired to the electrical circuit on the suDStrate 120 by means of wires 150, through a thermo-sonic wire bonding operatio n and the assembly is then covered with a plastic resin 160.
  • FIG.2 a top view of an electronic package according to an embodiment of the present invention is shown.
  • the figure depicts a BGA 200 with tne device 110 attached to the substrate 120.
  • the substrate 120 may be realized with different materials, such as plastic materials, fiberglass laminates, ceramic, poliymide, Alumina.
  • plastic materials such as plastic materials, fiberglass laminates, ceramic, poliymide, Alumina.
  • a quite recently developed electronic packaging technology consists of using an organ.c suostrate, consisting of a composite structure of laminated epoxy woven fibers g ass sheets; tne organic definition derives from the Epoxies resin compounds (organic chemistry) that are used to build these laminates.
  • the device 110 is typically a chip or active device, commonly made of Silicon, Germanium or Gallium Arsenide; this device is typically shaped substantially as a rectangular, particularly a square.
  • the device 110 is attached to the substrate 120 usually by means of a glue layer.
  • the glue may be a thermoplastic or thermoset one; typically, it is an epoxy glue, generally loaded with Silver particles for better heat dissipation.
  • the device 110 is attached to the substrate 120 by means of a conductive pad provided on the top surface of the substrate 120.
  • This pad allowing a better compatibility with the glue material and facilitating the heat transfer from the back of the device 110 into the substrate 120 by conduction, is usually made of a metallic material, typically copper or nickel and gold plated copper.
  • the pad is composed by a plurality of parts 212-218 not m contact, so that each couple of adjacent parts of the pad is separated by a free area of the substrate 120.
  • One or more insulating channels 222 228 are then provided the pad, particularly beyond the device 110.
  • the channels 222-228 shown m the figure are wide enough so that they may be used as wiring channels for the routing of connecting lines, thereby increasing the substrate wireability with regard to the available real estate or overall dimension of the package.
  • the wiring channels 222 228 allow tc draw 4 lines 100 ⁇ m wide (100 ⁇ m space) or 6 lines 75 ⁇ wide (75 urr space) for each channel.
  • this pad design involves decreasing the electronic package dimensions required for a particular application; on the contrary, it allows a greater number of devices to be installed on the same substrate, decreasing the number of modules required for the same application.
  • the proposed solution is fully compatible with the existing materials and does not affect their properties; it is cheap and of extremely easy implementation.
  • the packaging method involved by the present invention is fully compatible with the current processes and related equipment used in the industry. It should be noted that the delta heat dissipation capability driven by the differences between a full pad metal surface and the proposed design is negligible.
  • the pad is split in four separated parts.
  • the pad has been split in four different regions or islands 212-218, for their shape recalling the Maltese Cross.
  • Each of the four wiring channels 222-228 extends from a corresponding corner of the device 110 to a central region thereof.
  • the central area may be used to route the wires from one channel to the other or, the case of a multilayer substrate, to inner layers through vias (blind or through) .
  • This shape is particularly advantageous because the density of the signals to be carried to the device 110 increases at the corners; therefore, the wiring channels starting from the corners of the device 110 make easier the fan out from the device 110.
  • the same pad design is applicable to an electronic package including a plurality of devices, such as a multi chip module. Each device is attached to the substrate by means of a corresponding pad. Each pad is split m a plurality of parts not in contact, separated by a free area of the substrate, thereby providing one or more insulating channels available for wiring. It should be noted that the solution according to the present invention is particularly advantageous in a multi chip module, wnerem the proposed pad design gets the maximum effect on the overall package costs and performances.
  • FIG. 3 a cross sectional view of an electronic package with increased thermal dissipation is shown.
  • the BGA 300 includes the device 110 attached to a substrate 310.
  • the substrate 310 is a multilayer structure including a plurality of layers 312 318, typically used in Multi Chip Modules.
  • the device 110 is attached to the s-ostrate 310 oy means of the conductive pad described aoove; part.c.j.ar.), tr.e separate parts 216, 216 and 214 are visiDle the figure.
  • the substrate 310 includes at least one conductive hole, typically a drilled and metallized hole, connected to the pad provided on the top surface of the substrate 310; this embodiment, the thermal via 326 is connected to the part 216, while the thermal via 328 is connected to the part 218.
  • These thermal vias may in addition be connected to a further pad provided on the bottom surface of the same substrate 310.
  • tnis further pad has the same snape of tne pad provided on tne top surface of tne suDStrate 310.
  • the depicted package 300 includes a plurality of separate parts 334-338; the depicted package 300, the thermal via 326 for example connects the part 216 on the top surface of the substrate 310 to a corresponding part 336 on the bottom surface, and hole 328 connects the part 218 to a corresponding part 338.
  • the further pad on the bottom side of the substrate 310 is connected to the eutectic balls 130 used to connect the BGA package to a Printed Circuit Board (not shown) .
  • the result is a generalised spread of the heat that goes dissipated by the full array of balls 130 into the mother board. This heat dissipation path then increases the overall packaging thermal performances, with a thermal dissipation value typically about 2 w.
  • the multilayer substrate 310 includes a ground (GND) layer 342 and a power (VCC) layer 344.
  • the thermal vias 326 and 328 are connected to the GND layer 342 and to the VCC layer 344.
  • tney are once more enhancing the heat dissipation factor of the package 300.
  • the connection to the GND layer 342 extends the thermal dissipation factor to all the GND module connections toward the mother board mterface.
  • FIG.4a an electronic package with a device decoupling is shown.
  • the BGA 400 includes the device 110 attached to the suostrate 120 by means of the conductive pad descriDe ⁇ aoove; particularly, the pac is split in four different parts 212 218.
  • At least a first part of the pad such as part 216, is connected to the ground potential, while at least a second one, such as part 218, is connected to the power potential; the two parts 216 and 218 are then connected to each other by means of a decoupling capacitor 410.
  • the four parts 212-218 are connected in interfacing couples at different electric potentials GND and VCC (not shown) .
  • connections to the capacitors are achieved through lines extending from each part of the pad to the corresponding capacitor. It should be noted that this solution provides a signal noise level abatement for electrical performances.
  • the pad on the top surface of the substrate 120 is connected to a further pad provided on the bottom surface of the substrate 120; particularly, the part 216 is connected to the further part 336 by means of the conductive hole 326 and the part 218 is connected to another further pad 338 through another thermal via 328.
  • These further parts provided on the bottom surface of the substrate 120 offer very short connections to the bonding pads (VCC or GND) presents on the same side not requiring drilled holes for those connections.
  • the connecting balls positioned the two areas GND and VCC are multi access points with resulting very low resistance values.
  • a further embodiment of an electronic package with a device decoupling is shown m Fig.5.
  • the BGA 500 is a multilayer structure including the ground layer 342 and the power layer 344; tne metallized hole 326 is connected to the part 216 of the conductive pad, while the nole 328 is connected to the part 218 thereof.
  • the connections interfacing couples at different electric potentials GND and VCC are achieved on the same cnip carrier, -s g tr.e thermal vias cf eacn part of tne pad as connections to tne VCC or the G'. : p.anes, and the capac.tors assembled in close proximity to the aev.ce.
  • the part 216 is connected to tne ground p.ar.e 342 cy tne hole 326 and the part 218 is connected to the power layer 344 cy tne hole 328.
  • Tne connections to tne capacitor 510 are achieved through further metallized holes; particularly, the capacitor 510 is connected to the ground layer by means of a hole 520 and to the power layer 344 by another hole 530.
  • This embodiment of the present invention enhances the device electrical performances allowing an ideal device decoupling, with no extra wiring required beyond the drilled holes to drive the connections from the inner layers (VCC or GND) to the top surface of the laminate.

Abstract

Cette invention concerne un module électronique (400), notamment du type BGA, qui comporte un substrat (120) équipé de circuits et un ou plusieurs dispositifs actifs (110) fixés au substrat au moyen de plages de connexion respectives équipant la surface du substrat (120), chaque plage de connexion étant divisée en une pluralité de parties (212-218) qui ne sont pas en contact. Ces parties (212-218) peuvent être séparées par une zone du substrat (120) pouvant être pourvue de conducteurs, formant ainsi des gouttières d'interconnexion. En outre, ces mêmes parties (212-218) peuvent être reliées, en couples de jonction, à différents potentiels électriques (terre et alimentation électrique) et découplées les unes des autres au moyen de condensateurs (410), les connexions à la terre et à l'alimentation étant obtenues par l'intermédiaire de trous métallisés disposés à travers le substrat (120).
EP96932706A 1995-10-04 1996-10-03 Module electronique a conception avancee de plages de connexion Ceased EP0853817A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
WOPCT/IT95/00161 1995-10-04
IT9500161 1995-10-04
PCT/GB1996/002420 WO1997013275A1 (fr) 1995-10-04 1996-10-03 Module electronique a conception avancee de plages de connexion

Publications (1)

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EP0853817A1 true EP0853817A1 (fr) 1998-07-22

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EP (1) EP0853817A1 (fr)
JP (1) JP3093278B2 (fr)
KR (1) KR100276858B1 (fr)
TW (1) TW299564B (fr)
WO (1) WO1997013275A1 (fr)

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Publication number Priority date Publication date Assignee Title
JPH09175399A (ja) * 1995-12-28 1997-07-08 Motohiro Seisakusho:Kk コンテナなどの運搬車
KR100469911B1 (ko) * 1997-12-31 2005-07-07 주식회사 하이닉스반도체 레저바르커패시터의배열방법
JP2004214657A (ja) 2003-01-07 2004-07-29 Internatl Business Mach Corp <Ibm> プリント回路板製造用水溶性保護ペースト
JP5954013B2 (ja) 2012-07-18 2016-07-20 日亜化学工業株式会社 半導体素子実装部材及び半導体装置

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Publication number Priority date Publication date Assignee Title
EP0285064A2 (fr) * 1987-04-01 1988-10-05 Hitachi, Ltd. Structure de module à plusieurs puces
EP0382203A2 (fr) * 1989-02-10 1990-08-16 Fujitsu Limited Empaquetage céramique du type dispositif semi-conducteur et procédé pour son assemblage
JPH0422162A (ja) * 1990-05-17 1992-01-27 Hitachi Ltd リードフレームおよびそれを用いた半導体集積回路装置
JPH04139864A (ja) * 1990-10-01 1992-05-13 Seiko Epson Corp 半導体装置
US5258648A (en) * 1991-06-27 1993-11-02 Motorola, Inc. Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection

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US4595945A (en) * 1983-10-21 1986-06-17 At&T Bell Laboratories Plastic package with lead frame crossunder
JPH0494565A (ja) * 1990-08-10 1992-03-26 Toshiba Corp 半導体装置
JP2501953B2 (ja) * 1991-01-18 1996-05-29 株式会社東芝 半導体装置
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface

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EP0285064A2 (fr) * 1987-04-01 1988-10-05 Hitachi, Ltd. Structure de module à plusieurs puces
EP0382203A2 (fr) * 1989-02-10 1990-08-16 Fujitsu Limited Empaquetage céramique du type dispositif semi-conducteur et procédé pour son assemblage
JPH0422162A (ja) * 1990-05-17 1992-01-27 Hitachi Ltd リードフレームおよびそれを用いた半導体集積回路装置
JPH04139864A (ja) * 1990-10-01 1992-05-13 Seiko Epson Corp 半導体装置
US5258648A (en) * 1991-06-27 1993-11-02 Motorola, Inc. Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection

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See also references of WO9713275A1 *

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Publication number Publication date
JPH11508409A (ja) 1999-07-21
KR19990064001A (ko) 1999-07-26
TW299564B (fr) 1997-03-01
JP3093278B2 (ja) 2000-10-03
KR100276858B1 (ko) 2001-01-15
WO1997013275A1 (fr) 1997-04-10

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