Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • H03M1/186—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedforward mode, i.e. by determining the range to be selected directly from the input signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters

Definitions

• the present invention relates to an analog-to-digital converter circuit in which an input signal acts as a reference signal on an analog-to-digital converter which adapts its range to the level of the input signal without a variable gain amplifier.
• an analog-to-digital converter with a high resolution has been conventionally required.
• the range in decibels (dB) divided by six (6) gives the necessary number of bits to be output by the ADC.
• this formula would require an ADC to have 17 bits or more.
• a high conversion rate greater than 100 kHz could well be necessary, for example, due to a large bandwidth of the input signal.
• an input signal V* is rectified by a rectifier 12 and filtered through a low-pass filter 13 to extract the envelope of the signal.
• This signal envelope is used as a control signal to control the gain of a variable gain amplifier 11.
• the amplifier 11 will have a low gain if the input signal, and thus the control signal, is large and a high gain if the control signal is low.
• the amplifier will provide an output signal with a compressed dynamic range after the amplifier. If the signal is then converted to a digital signal, an ADC 14 with a fixed reference voltage is used. The reference voltage sets the range of the ADC.
• the Mason et al. patent discloses an ADC having an automatic range control.
• the automatic range control is in the form of a peak detector which generates a reference potential corresponding to the peak amplitude of the input signal, a level shifting circuit for shifting the dc level of the input signal in accordance with the reference potential, and a ADC for converting the shifted input signal relative to the reference potential for high resolution digital output signals.
• the present invention provides a solution to the ADC dynamic range problem while avoiding the use of an automatic gain control.
• the invention involves rectifying an input signal and filtering the rectified input signal through a low-pass filter in the conventional manner to extract a signal envelope, but instead of including an amplifier with a variable gain, the signal envelope is used as a reference signal on the ADC.
• the analog-to-digital converter circuit can further include an adder for adding the reference signal to the analog input signal as an offset and a multiplier for doubling the reference signal wherein the doubled reference signal sets the range of an analog-to-digital converter with two reference inputs.
• the analog-to-digital converter circuit may include a multiplier for generating a complement of the reference signal wherein the reference signal and its complement are used to set the range of an analog-to-digital converter with two reference inputs. Another embodiment enables absolute measurement of the output signal level.
• Another embodiment is presented that keeps the gain in the signal path constant over a period of time by scaling the digital output signal with a digital reference signal, thus enabling processing which might have this feature as a requirement.
• Figure 1 is a schematic diagram of a conventional automatic gain controlled analog-to-digital converter
• Figure 2 is a schematic diagram of a first embodiment in accordance with the present invention.
• Figure 3 is a schematic diagram of a second embodiment in accordance with the present invention.
• Figure 3(a) is a schematic diagram of one type of multiplier suitable for use in the embodiment of Figure 3;
• Figure 3(b) is a schematic diagram of one type of summing amplifier suitable for use in the embodiment of Figure 3;
• Figure 4 is a schematic diagram of a third embodiment in accordance in the present invention.
• Figure 4(a) is a schematic diagram of one type of multiplier suitable for use in the embodiment of Figure 4;
• Figure 5 is a schematic diagram of a fourth embodiment in accordance with the present invention.
• FIGS. 6 and 7 are schematic diagrams of a fifth embodiment in accordance with the present invention.
• Figure 2 illustrates a first embodiment of the invention wherein an input signal V k is rectified by a rectifier 22 and filtered by a low-pass filter 23 to provide a reference voltage V ref representative of the signal envelope of the input signal V k .
• the input signal V is also input to an input port of the ADC 25 for conversion to a digital signal.
• the input signal V* is rectified and low-pass filtered as conventionally done in automatic gain control, but instead of having an amplifier with a variable gain, the signal envelope is used as a reference signal in the analog- to-digital conversion.
• the reference signal V ⁇ sets the range of the ADC 25 and the ADC 25 will adapt its range to the level of the input signal V .
• One other advantage of the present invention is that it is easier to get it to work over a wider dynamic range compared to a variable gain amplifier because of the problem of making an amplifier with a gain that is variable over a wide range.
• ADCs have two reference inputs, one corresponds to the input level which gives the maximum output code and one that corresponds to the input level which gives the minimum output code.
• ADC0820 from National Semiconductor Corporation.
• FIG. 3 A second embodiment is shown in Figure 3 wherein the negative reference input of the ADC 25 is set to 0 V (ground), the positive input of the ADC 25 is set to two times the output of the low-pass filter 23 (2xV ref ) via a multiplier 38. An offset of V ⁇ (the output of the low-pass filter 23) is added via an adder 39 to the input signal V k . Thus, the full range is shifted up to the range of 0 V to a maximum value (i.e., 2xV ⁇ ef ), along with an upward offset of the input signal V* religious.
• Figure 3(a) illustrates one way to implement the multiplier 38.
• the multiplier 38 takes the form of an amplifier 38B the output of which is fed back through a resistor R 3gA to the negative input of the amplifier 38B.
• the node joining the negative input of the amplifier 38B and the resistor R 38A is also connected to ground through another resistor R 3(c .
• Figure 3(b) illustrates a summing amplifier 39 with a gain of one when all resisters indicated in Figure 3 are of equal value suitable for use in the embodiment shown in Figure 3. Any suitable summing amplifier maybe used, Figure 3(b) showing just one by way of example.
• the two inputs Vr f and V*. are input through resistors R 39A and R 3 B , respectively.
• the outputs of the resistors R 39A and Rj, B are joined at a node with the feedback output signal of a first amplifier 39C, which has passed through a feedback resistor R 39D .
• the signal at this node is input to the negative input of the amplifier 39C.
• the positive input of the amplifier 39C is grounded.
• the output of the amplifier 39C is passed through another resistor R 39B to be combined with a feedback signal at the negative input of a second amplifier 39F.
• the positive input of the amplifier 39F is grounded.
• the feedback signal passes through a feedback resistor R 390 .
• the configuration of this portion of the circuit is specific to a given application and the specific design to be implemented is within the skill level of any artisan.
• a third embodiment is shown in Figure 4, wherein the output of the low- pass filter serves both as a positive reference input and, after being converted to a complementary negative number (by multiplying by negative 1 via a multiplier 48) serves as a negative reference input.
• Figure 4(a) illustrates one way to implement the multiplier 48.
• the multiplier 48 takes the form of an amplifier 48A the output of which is fed back through a resistor R ⁇ to the negative input of the amplifier 48A.
• the node joining the negative input of the amplifier 48A and the resistor R ⁇ --, is also connected to the input signal V ⁇ , which has passed through another resistor R ⁇ c-
• the positive input of the amplifier 48A is grounded.
• the input V relieve f to the amplifier 48 A is thus subject to a gain of negative one.
• Figure 4(a) it must be emphasized that there are many ways to implement such a multiplier 48, Figure 4(a) showing just one.
• circuits shown in Figures 2, 3 and 4 will solve the problem of accommodating an input signal having a wide dynamic range, some limitations could become apparent.
• a disadvantage of the circuits shown in Figures 2, 3 and 4 is that it does not make an absolute measurement of the signal level.
• One other disadvantage is that there could be signal processing following the ADC that assumes the gain in the signal path to be constant over a period of time.
• Figure 5 shows a fourth embodiment not subject to these disadvantages in that it provides an absolute level measurement.
• a second ADC 56 is included to measure the reference voltage V ⁇ output from the low-pass filter 23.
• the time constant in the low pass filter 23 is typically long compared to the variations in the input signal. This means that the reference voltage V ⁇ will vary much slower than the input signal m . Because of this, a slower ADC could be used as the second ADC 56, which would be simpler to implement and less expensive than the first ADC 55.
• the second ADC 56 will have a fixed reference level V fa .
• the output V ⁇ from the LP-filter 23 is a signal that follows the envelope of the input signal W m and therefore the output D ⁇ of the second ADC 56 could be used as an absolute measure of the input signal level. In some applications, it might be sufficient to be able to measure the absolute level at a lower rate than the sampling rate of the first ADC 55. For example, in a cellular phone system, absolute level measurements of signal strength are used as an input to handover algorithms.
• each output sample D ⁇ would have to be scaled with the reference voltage V afford, if, however, the problem with the varying gain affecting the subsequent signal processing should be solved, then each output sample D ⁇ would have to be scaled with the reference voltage V afford,.
• the embodiment shown in Figure 6 provides this capability.
• an envelope signal V r from the low pass filter 23 is converted from analog to digital in a second ADC 66.
• the reference voltage V render f for the first ADC 65 is provided by a Digital Signal Processor (DSP) 68 through a Digital-to-Analog Converter (DAC) 67.
• DSP Digital Signal Processor
• DAC Digital-to-Analog Converter
• the DSP 68 shown in Figure 6, could be implemented as an Application Specific Integrated Circuit (ASIC). The advantage of providing the DAC 67 is explained below.
• Figure 7 shows one example of how output samples could be scaled.
• the DSP 68 can include a multiplier 69, implemented in software, for scaling the digital output from of the first ADC 65.
• the output from the first ADC 55 is:
• the second ADC 66 could be of a type that includes a DAC, for example a successive approximation converter. In this case it would be possible to get the quantized voltage V afford f directly from the second ADC 66. It should be noted that a converter implemented like the one in Figures 6 and 7 will have a dynamic range of N + M bits. The quantization error however will be like that of N bit converter. It should also be noted that, with a different algorithm in the DSP 68 shown in Figure 7 and without a low pass filter, the results of the circuit described in Beauducel patent, could be emulated. In this case the sample rate of the two ADCs would have to be equal.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Analogue/Digital Conversion (AREA)

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• 1995
  • 1995-01-30 US US08/380,719 patent/US5684480A/en not_active Expired - Lifetime
• 1996
  • 1996-01-24 CA CA002210394A patent/CA2210394A1/en not_active Abandoned
  • 1996-01-24 AU AU46373/96A patent/AU702862B2/en not_active Ceased
  • 1996-01-24 JP JP8523460A patent/JPH10513322A/ja active Pending
  • 1996-01-24 KR KR1019970705075A patent/KR19980701679A/ko not_active Application Discontinuation
  • 1996-01-24 EP EP96902033A patent/EP0807335A1/en not_active Ceased
  • 1996-01-24 WO PCT/SE1996/000072 patent/WO1996024193A1/en not_active Application Discontinuation
• 1997
  • 1997-07-29 FI FI973144A patent/FI973144A/fi unknown

Non-Patent Citations (1)

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