EP0789392A2 - Höckerloses Verfahren zur Verbindung von inneren Leitern mit integrierten Halbleiterschaltungen - Google Patents

Höckerloses Verfahren zur Verbindung von inneren Leitern mit integrierten Halbleiterschaltungen Download PDF

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Publication number
EP0789392A2
EP0789392A2 EP97300813A EP97300813A EP0789392A2 EP 0789392 A2 EP0789392 A2 EP 0789392A2 EP 97300813 A EP97300813 A EP 97300813A EP 97300813 A EP97300813 A EP 97300813A EP 0789392 A2 EP0789392 A2 EP 0789392A2
Authority
EP
European Patent Office
Prior art keywords
inner leads
tips
pressing
metal electrodes
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97300813A
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English (en)
French (fr)
Other versions
EP0789392B1 (de
EP0789392A3 (de
Inventor
Toshinari Oki Electric Industry Co. Ltd. Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of EP0789392A2 publication Critical patent/EP0789392A2/de
Publication of EP0789392A3 publication Critical patent/EP0789392A3/de
Application granted granted Critical
Publication of EP0789392B1 publication Critical patent/EP0789392B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a method of attaching inner leads to the metal electrodes of a semiconductor integrated-circuit die.
  • the invented method presses the tips of the inner leads onto the metal electrodes with a heated bonding tool.
  • the heat of the bonding tool softens the tips of the inner leads, so that when pressed onto the metal electrodes, they are directly pressure-welded to the metal electrodes without the need for soft metal bumps.
  • the invented method may comprise one or more of the additional steps of pre-softening the inner leads by annealing, roughening the surfaces of the inner leads that will be pressed against said metal electrodes, and forming mesas at the tips of the inner leads.
  • FIG. 1 shows part of a plastic-film lead frame of the type employed in, for example, tape-automated bonding.
  • the lead frame comprises a polyimide film 2 with a central hole 4, and a plurality of inner leads 6 that are attached to the polyimide film 2 but extend over the central hole 4.
  • the cross-sectional structure of the frame through line X-X is illustrated in FIG. 2.
  • Each inner lead 6 comprises a copper-foil core 8 approximately thirty-five micrometers (35 ⁇ m) thick, covered by gold plating 10 approximately 5 ⁇ m thick.
  • the inner lead 6 is attached to the polyimide film 2 by an adhesive 12.
  • the lead frame shown in FIGs. 1 and 2 is created by spreading adhesive 12 on the polyimide film 2, using the adhesive 12 to bond a sheet of copper foil onto the entire surface of the polyimide film 2 (including the central hole 4), patterning the copper foil to remove those portions that will not become inner leads 6, thus leaving the copper-foil cores 8 of the inner leads attached to the polyimide film 2, then gold-plating the exposed surfaces of the copper-foil cores 8, including both upper and lower surfaces.
  • the hardness of the resulting inner leads 6 normally has a value of 110 to 120 on the Vickers hardness scale (HV).
  • the lead frame Before the inner leads 6 are bonded to a semiconductor integrated-circuit die (referred to below as an IC chip), the lead frame is placed in an annealing kiln of the type shown in FIG. 3, and annealed at a temperature in the range from about 200°C to about 300°C for approximately thirty minutes, in a reducing atmosphere such as a nitrogen atmosphere. This annealing pre-softens the inner leads 6, reducing their hardness to approximately 80 to 100 HV.
  • the annealing temperature can be varied according to the type of copper foil employed in the inner leads.
  • FIG. 4 illustrates the relation between annealing temperature, shown on the horizontal axis, and lead hardness, shown on the vertical axis.
  • the white dots are data points taken for one type of copper foil commonly employed in inner leads, for which an annealing temperature of about 300°C is appropriate.
  • the black dots are data points for another type of copper foil commonly employed in inner leads, for which a lower annealing temperature is suitable.
  • the lead frame is next placed in a bonding apparatus so that the annealed inner leads 6 can be bonded to an IC chip 14, which is disposed within the central hole 4.
  • the bonding is accomplished by a bonding tool 16.
  • the bonding process is more clearly illustrated by the sectional view in FIG. 6.
  • the IC chip 14 is placed on the center of a stage 18, which is heated to 100°C.
  • the bonding tool 16, which is heated to 500°C, is positioned over the center of the stage.
  • a clamper 20 is placed on the stage 18, and the polyimide film 2 is placed on the clamper 20 and held in a position such that the tips of the inner leads 6 are directly over the aluminum electrodes 22 of the IC chip 14.
  • the bonding tool 16 is then lowered so that it presses the tips of the inner leads 6 against the aluminum electrodes 22, while simultaneously heating the tips of the inner leads 6 to 500°C. Pressure is maintained with a force of one kilogram (1 kg) for eight tenths of a second (0.8 s).
  • the combination of high temperature and pressure alloys the gold plating of the inner leads 6 with the aluminum of the electrodes 22, thereby pressure-welding the inner leads 6 directly to the aluminum electrodes 22.
  • a further advantage of the invented method is that the bonds have a uniformly low profile, as the leads are bonded directly to the aluminum electrodes, with no raised bumps.
  • the second embodiment of the invented method is similar to the first, except that the step of annealing the inner leads is omitted, and the temperature of the bonding tool 16 is increased to 560°C.
  • the bonding pressure is again 1.0 kg, maintained for 0.8 s. With these temperature and time conditions, the tips of the inner leads 6 can be softened to 40 HV to 60 HV even though the initial hardness of the leads is from 110 HV to 120 HV.
  • the second embodiment achieves effects similar to the first embodiment, and has the additional advantage of being shorter and simpler, since the annealing step is omitted.
  • the third embodiment is similar to the first embodiment, but comprises the additional step of roughening the under-surfaces of the inner leads 6.
  • FIG. 7 is a sectional view illustrating the roughened surface 24 of an inner lead 6.
  • the roughness scale (the spacing between adjacent valleys in the roughened surface) is substantially 1.0 ⁇ m. Roughening does not alter the hardness of the inner leads 6, which remains about 110 HV to 120 HV before annealing.
  • the annealing and bonding steps are carried out as in the first embodiment, so a description will be omitted.
  • the advantage of the third embodiment is that even if the aluminum electrodes 22 of the IC chip 14 are covered by a thick natural oxide layer, when the roughened surface 24 is pressed against the electrode surface, the oxide layer is readily broken through, enabling the reliable formation of an aluminum-gold alloy weld as in the first embodiment.
  • the third embodiment can be modified by omitting the annealing step, as in the second embodiment.
  • the third embodiment can also be modified by roughening only parts of the under-surfaces inner leads 6, instead of the entire under-surfaces, provided the parts that make contact with the aluminum electrodes 22 are roughened.
  • the fourth embodiment is similar to the first embodiment, but gives the tips of the inner leads a mesa shape, so that the inner leads can be bonded to the aluminum electrodes without exerting unwanted pressure on surrounding passivation films.
  • FIG. 8 is a sectional view showing an inner lead 6 of the type employed in the fourth embodiment.
  • the mesa 26 is formed after the inner leads 6 have been patterned by removing unwanted copper foil, and before the gold plating 10 is applied.
  • the mesa 26 is formed by etching to reduce the thickness of the copper-foil core 8 in areas other than the mesa 26.
  • the mesa may be square, round, hexagonal, diamond-shaped, or of any other shape suitable for bonding to an aluminum electrode 22. Mesa formation does not change the hardness of the inner leads 6, which remains 110 HV to 120 HV as in the first embodiment.
  • FIG. 9 illustrates the bonding of an inner lead 6 to an aluminum electrode 22 that is surrounded and partially covered by a passivation film 28.
  • the joint strength of the bond formed between the mesa 26 and aluminum electrode 22 is substantially the same as the joint strength of the bond formed in the first embodiment.
  • the advantage of the fourth embodiment is that the passivation film 28 cannot be cracked by the pressure of bonding.
  • the fourth embodiment can be modified by omitting the annealing step, as in the second embodiment.
  • the present invention is not limited to use in tape-automated bonding, but is applicable in any bonding process in which inner leads are attached to the metal electrodes of an IC chip by pressure welding, regardless of how the inner leads themselves are formed or mounted.
  • the temperatures of 200°C, 300°C, 500°C, and 560°C, and Vickers hardness values of 40 HV, 60 HV, 80 HV, 100 HV, 110 HV, and 120 HV mentioned in the above embodiments have been given as general guides; the invention is not restricted to these exact temperatures or hardness values.
  • the annealing time is not limited to thirty minutes.
  • the roughness scale of the roughened inner leads may be greater than 1.0 ⁇ m, and the roughening method is not limited to etching.
  • the IC chip may be individually packaged, or may become part of a multi-chip module.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
EP97300813A 1996-02-08 1997-02-07 Höckerloses Verfahren zur Verbindung von inneren Leitern mit integrierten Halbleiterschaltungen Expired - Lifetime EP0789392B1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP22353/96 1996-02-08
JP2235396 1996-02-08
JP2235396 1996-02-08
JP185784/96 1996-07-16
JP18578496 1996-07-16
JP18578496A JP3558459B2 (ja) 1996-02-08 1996-07-16 インナーリード接続方法

Publications (3)

Publication Number Publication Date
EP0789392A2 true EP0789392A2 (de) 1997-08-13
EP0789392A3 EP0789392A3 (de) 1998-02-25
EP0789392B1 EP0789392B1 (de) 2001-09-19

Family

ID=26359555

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97300813A Expired - Lifetime EP0789392B1 (de) 1996-02-08 1997-02-07 Höckerloses Verfahren zur Verbindung von inneren Leitern mit integrierten Halbleiterschaltungen

Country Status (5)

Country Link
US (1) US5885892A (de)
EP (1) EP0789392B1 (de)
JP (1) JP3558459B2 (de)
CN (1) CN1105399C (de)
DE (1) DE69706720T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0917211A3 (de) * 1997-11-17 1999-11-17 Canon Kabushiki Kaisha Halbleitervorrichtung ohne Harzverkapselung und Modul von photovoltaischen Vorrichtungen, die diese Vorrichtung anwendet
WO2022058360A3 (de) * 2020-09-18 2022-05-12 Heraeus Deutschland GmbH & Co. KG Herstellung von oberflächenmodifizierten cu-bändchen für das laserbonden

Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
ATE459099T1 (de) 2000-03-10 2010-03-15 Chippac Inc Flipchip-verbindungsstruktur und dessen herstellungsverfahren
US6306684B1 (en) * 2000-03-16 2001-10-23 Microchip Technology Incorporated Stress reducing lead-frame for plastic encapsulation
US6512304B2 (en) 2000-04-26 2003-01-28 International Rectifier Corporation Nickel-iron expansion contact for semiconductor die
US6656772B2 (en) * 2001-11-23 2003-12-02 Industrial Technology Research Institute Method for bonding inner leads to bond pads without bumps and structures formed
US7459376B2 (en) * 2005-02-04 2008-12-02 Infineon Technologies Ag Dissociated fabrication of packages and chips of integrated circuits
JP2006310530A (ja) 2005-04-28 2006-11-09 Sanyo Electric Co Ltd 回路装置およびその製造方法
IL196635A0 (en) * 2009-01-21 2009-11-18 Solomon Edlin High current capacity inner leads for semiconductor device
KR102061649B1 (ko) * 2012-11-07 2020-01-02 현대모비스 주식회사 차량용 레이더장치

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KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
DE19504543C2 (de) * 1995-02-11 1997-04-30 Fraunhofer Ges Forschung Verfahren zur Formung von Anschlußhöckern auf elektrisch leitenden mikroelektronischen Verbindungselementen zum lothöcker-freien Tab-Bonden

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0917211A3 (de) * 1997-11-17 1999-11-17 Canon Kabushiki Kaisha Halbleitervorrichtung ohne Harzverkapselung und Modul von photovoltaischen Vorrichtungen, die diese Vorrichtung anwendet
US6316832B1 (en) 1997-11-17 2001-11-13 Canon Kabushiki Kaisha Moldless semiconductor device and photovoltaic device module making use of the same
WO2022058360A3 (de) * 2020-09-18 2022-05-12 Heraeus Deutschland GmbH & Co. KG Herstellung von oberflächenmodifizierten cu-bändchen für das laserbonden

Also Published As

Publication number Publication date
US5885892A (en) 1999-03-23
EP0789392B1 (de) 2001-09-19
DE69706720T2 (de) 2002-07-04
EP0789392A3 (de) 1998-02-25
CN1161570A (zh) 1997-10-08
CN1105399C (zh) 2003-04-09
DE69706720D1 (de) 2001-10-25
JPH09275125A (ja) 1997-10-21
JP3558459B2 (ja) 2004-08-25

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