EP0774150B1 - Verfahren zur optimierten adressierung einer flüssigkristallanzeigetafel - Google Patents

Verfahren zur optimierten adressierung einer flüssigkristallanzeigetafel Download PDF

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Publication number
EP0774150B1
EP0774150B1 EP95927008A EP95927008A EP0774150B1 EP 0774150 B1 EP0774150 B1 EP 0774150B1 EP 95927008 A EP95927008 A EP 95927008A EP 95927008 A EP95927008 A EP 95927008A EP 0774150 B1 EP0774150 B1 EP 0774150B1
Authority
EP
European Patent Office
Prior art keywords
line
addressing
signal
slope
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95927008A
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English (en)
French (fr)
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EP0774150A1 (de
Inventor
Jean-Michel Vignolle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson-LCD
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Thomson-LCD
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present invention relates to an addressing method liquid crystal display for uniform quality display across the screen.
  • a liquid crystal display consists of a set image elements ("Pixels” for Picture Element in English) each formed by an electrode and a counter-electrode framing the liquid crystal, the value of the field between these electrodes modifying the optical properties of liquid crystal.
  • the voltage across the pixel electrodes is delivered via addressing columns by peripheral circuits ("Driver" in English) thanks to transistors control of these pixels, the passing and non-passing state of these transistors being determined by selection lines from other Line drivers.
  • FIG. 1 represents a selection line Lj of a liquid crystal screen with m lines and n columns, controlling the transistors T1 to Tn of the pixels P1 to Pn.
  • This line is connected to a line driver which delivers at A the square selection signal V A (t) as shown in FIG. 2.
  • the signal V A (t) turns on the transistors T1 to Tn of the line Lj and thus allows the polarization of the electrodes of the pixels P i by the video signal coming from the columns C 1 to C n .
  • the capacitors C cl represent the capacitive couplings between the line Lj and the counter-electrode CE through the liquid crystal.
  • This line Lj whose end is floating constitutes a delay line which results in a deformation of the selection signal at point B with respect to point A, this signal V B (t) at point B is shown in FIG. 2. This is particularly visible when one wishes to display a uniform image and when the same voltage is applied to all the columns C 1 to C n of the screen.
  • the voltage across the capacitors Cp constituted by the electrodes of the pixels P i and the counter-electrode CE is the same. However, after the instant t F this is no longer the case due to the difference between the forms of the signals V A (t) and V B (t).
  • V 1 is the voltage supplied to the pixel P1 by the column C1
  • the voltage .DELTA.V 1 drop across the pixel at the time when the transistor T1 becomes non-conducting is illustrated in Figure 3a, this being the voltage V of the counter electrode.
  • the capacitive coupling phenomenon is identical, but in this case, the transistor T n remains on as long as the voltage V B (t) is greater than V 1 + V t ' where V t is the threshold voltage of the transistor.
  • the coupling ⁇ V n between the line L j and the last pixel P n is therefore weaker than ⁇ V 1 , because as long as the transistor T n is on, the voltage across the pixels remains equal to the voltage delivered by the column C n .
  • ⁇ V ' being the voltage drop at point B.
  • the gray level is therefore not the same at the beginning and at the end of the line. This so-called "horizontal gradient" problem is particularly important for large screens.
  • the present invention provides a simple and effective solution to this. "horizontal gradient" problem.
  • the method according to the invention consists in periodically scanning each line by a voltage signal as a function of the time applied to the control of the switching element, each period consisting of a level then a curve.
  • the method is characterized in that the curve is chosen to go from the value of the bearing to the blocking voltage of the element switching at a time t> 0.
  • this process also makes it possible to reduce the coupling and therefore the parasitic voltages on a screen.
  • FIG. 4a An embodiment of the present invention is shown in FIG. 4a and consists in modifying the shape of the signal delivered by the selection circuit in order to compensate for the delay effect of the line responsible for the horizontal gradient.
  • the signal V a (t) does not decrease suddenly (after a plateau of duration t F - t j ), but from t F with a slope ⁇ preferably less than or equal to the characteristic slope of the delay line at point B, that is to say that ⁇ is less than ⁇ V / ⁇ , ⁇ being the characteristic time of the delay line in B and ⁇ V the potential drop at point A.
  • An example of the value of ⁇ can be a few volts per ⁇ s. This signal thus decreases until the voltage V A (t) is equal to V F ' , voltage for which the transistors T1 to Tn are blocked. From this instant t F ' , the signal drops instantly.
  • the signal is the same at point A and B, all the transistors of the line maintaining the voltages constants on pixels.
  • the selection signal with delay provided with a slope ⁇ between t F and t F ' is shown in Figures 4b.
  • a refinement of the method consists in using between t F and t F ' a curve which is not a straight line portion but a portion of a function f (t) which remains unchanged by the transfer function of the delay line : applying f (t) to T 1 results in applying f (t - T) to T n , T being a delay.
  • f (t) can for example be a sinusoid or a sum of sinusoids.
  • This method according to the invention can be implemented by a "driver" having an input which makes it possible to control the output current.
  • a "driver” having an input which makes it possible to control the output current.
  • the desired signal is obtained at the output of the "driver” by modulating this input so as to obtain a V H wave having an inverted sawtooth shape as illustrated in FIG. 6. That is to say each line 1 , 2, 3, 4, etc ... the high level V H is maintained on a level for a line period until time T F , then lowered linearly until time T F ' to be instantly raised again at this landing and sweep the next line.
  • the present invention can be used for repair LCD flat screen. Indeed, there are procedures known repairs but which do not work because they increase the RC of the repaired line, which makes it visible because it does not not undergo the same coupling as the neighboring lines. Taking for ⁇ the greater of the characteristic times repaired line or normal lines, repaired lines become similar to neighboring lines.
  • the present invention applies to the control of flat screens liquid crystal with peripheral or integrated drivers, and especially large screens.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Claims (9)

  1. Verfahren zur matrixartigen Adressierung eines Schirms, wobei jede Leitung (Lj) durch ein periodisches Signal mit der Spannung (VA(t)) in Abhängigkeit von der Zeit abgetastet wird, das an den Steuereingang eines Umschaltelementes angelegt ist, wobei jede Periode des Signals (VA(t)) durch eine Stufe und dann durch eine Kurve f(t) gebildet ist,
    dadurch gekennzeichnet, daß
    die Kurve f(t) für einen Übergang von dem Wert der Stufe zu der Sperrspannung des Umschaltelementes in einer Zeit t > 0 dient.
  2. Verfahren zur matrixartigen Adressierung nach Anspruch 1, dadurch gekennzeichnet, daß f(t) ein Teil der Geraden der Steigung (α) ist.
  3. Verfahren zur matrixartigen Adressierung nach Anspruch 1, dadurch gekennzeichnet, daß f(t) ein Teil einer Sinuskurve mit der Amplitude A und der Periodendauer w ist.
  4. Verfahren zur matrixartigen Adressierung nach Anspruch 1, dadurch gekennzeichnet, daß f(t) ein Teil der Summe der Sinuskurven mit den Amplituden Ai und der Periodendauer wi ist.
  5. Verfahren zur matrixartigen Adressierung nach Anspruch 3 oder 4, dadurch gekennzeichnet, daß die Koeffizienten der Sinuskurve oder der Sinuskurven derart berechnet werden, daß f(t) zu Beginn und am Ende der Leitung unverändert bleibt.
  6. Verfahren zur matrixartigen Adressierung nach Anspruch 2, dadurch gekennzeichnet, daß der Wert (α) der Steigung des Signals kleiner ist als der Wert der charakteristischen Steigung der Verzögerungsleitung am Ende der Leitung (B).
  7. Verfahren zur Adressierung nach einem der Ansprüche 2 und 6, dadurch gekennzeichnet, daß die Steigung (α) eine negative Steigung ist.
  8. Verfahren zur Adressierung nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, daß das Signal (VA(t)) durch eine periphere Adressierschaltung mit einem Eingang geliefert wird, der eine Steuerung des Ausgangsstroms ermöglicht.
  9. Verfahren zur Adressierung nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, daß das Signal (VA(t)) durch eine Adressierschaltung geliefert wird, die einen analogen Eingang zur Bestimmung des Ausgangswertes enthält und durch ein Sägezahnsignal moduliert ist, das sich mit der Zeilenperiode umkehrt.
EP95927008A 1994-08-02 1995-08-02 Verfahren zur optimierten adressierung einer flüssigkristallanzeigetafel Expired - Lifetime EP0774150B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9409586A FR2723462B1 (fr) 1994-08-02 1994-08-02 Procede d'adressage optimise d'ecran a cristaux liquides et dispositif pour sa mise en oeuvre
FR9409586 1994-08-02
PCT/FR1995/001038 WO1996004640A1 (fr) 1994-08-02 1995-08-02 Procede d'adressage optimise d'ecran a cristaux liquides et dispositif pour sa mise en ×uvre

Publications (2)

Publication Number Publication Date
EP0774150A1 EP0774150A1 (de) 1997-05-21
EP0774150B1 true EP0774150B1 (de) 2001-10-31

Family

ID=9466000

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Application Number Title Priority Date Filing Date
EP95927008A Expired - Lifetime EP0774150B1 (de) 1994-08-02 1995-08-02 Verfahren zur optimierten adressierung einer flüssigkristallanzeigetafel

Country Status (7)

Country Link
US (1) US5995075A (de)
EP (1) EP0774150B1 (de)
JP (1) JPH10504911A (de)
KR (1) KR100366476B1 (de)
DE (1) DE69523601T2 (de)
FR (1) FR2723462B1 (de)
WO (1) WO1996004640A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3406508B2 (ja) 1998-03-27 2003-05-12 シャープ株式会社 表示装置および表示方法
KR100796787B1 (ko) * 2001-01-04 2008-01-22 삼성전자주식회사 게이트 신호 지연 보상 액정 디스플레이 장치, 패널 및 방법
KR100830098B1 (ko) * 2001-12-27 2008-05-20 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
AU2003217386B2 (en) 2002-02-13 2008-06-26 Ludwig Institute For Cancer Research Humanized GM-CSF antibodies
KR100796298B1 (ko) * 2002-08-30 2008-01-21 삼성전자주식회사 액정표시장치
TWI251183B (en) * 2003-05-16 2006-03-11 Toshiba Matsushita Display Tec Active matrix display device
TWI253051B (en) * 2004-10-28 2006-04-11 Quanta Display Inc Gate driving method and circuit for liquid crystal display
JP4667904B2 (ja) * 2005-02-22 2011-04-13 株式会社 日立ディスプレイズ 表示装置
CN101300619B (zh) * 2005-11-04 2010-11-17 夏普株式会社 显示装置
US20100289785A1 (en) * 2006-09-15 2010-11-18 Daiichi Sawabe Display apparatus
JP2008304513A (ja) * 2007-06-05 2008-12-18 Funai Electric Co Ltd 液晶表示装置、および液晶表示装置の駆動方法
US8462099B2 (en) 2007-10-24 2013-06-11 Sharp Kabushiki Kaisha Display panel and display device
TWI409743B (zh) * 2008-08-07 2013-09-21 Innolux Corp 修正電路、顯示面板及顯示裝置
JP2011128642A (ja) * 2011-02-03 2011-06-30 Sharp Corp 表示装置
CN107533828B (zh) * 2015-04-07 2020-05-05 夏普株式会社 有源矩阵型显示装置及其驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0683416B2 (ja) * 1986-10-24 1994-10-19 株式会社日立製作所 液晶表示装置用駆動回路
JP2820336B2 (ja) * 1991-10-22 1998-11-05 シャープ株式会社 アクティブマトリクス型液晶表示装置の駆動方法
JPH05181113A (ja) * 1991-12-27 1993-07-23 Sharp Corp 液晶プロジェクタ
JPH063647A (ja) * 1992-06-18 1994-01-14 Sony Corp アクティブマトリクス型液晶表示装置の駆動方法
JPH0749670A (ja) * 1993-08-09 1995-02-21 Sharp Corp 液晶駆動回路
JPH07287554A (ja) * 1994-04-18 1995-10-31 Casio Comput Co Ltd 液晶表示装置

Also Published As

Publication number Publication date
EP0774150A1 (de) 1997-05-21
WO1996004640A1 (fr) 1996-02-15
US5995075A (en) 1999-11-30
KR100366476B1 (ko) 2003-03-06
DE69523601D1 (de) 2001-12-06
FR2723462A1 (fr) 1996-02-09
FR2723462B1 (fr) 1996-09-06
DE69523601T2 (de) 2002-07-11
JPH10504911A (ja) 1998-05-12

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