EP0774150B1 - Method for optimised addressing of a liquid crystal display - Google Patents

Method for optimised addressing of a liquid crystal display Download PDF

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Publication number
EP0774150B1
EP0774150B1 EP95927008A EP95927008A EP0774150B1 EP 0774150 B1 EP0774150 B1 EP 0774150B1 EP 95927008 A EP95927008 A EP 95927008A EP 95927008 A EP95927008 A EP 95927008A EP 0774150 B1 EP0774150 B1 EP 0774150B1
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Prior art keywords
line
addressing
signal
slope
voltage
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German (de)
French (fr)
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EP0774150A1 (en
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Jean-Michel Vignolle
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Thomson-LCD
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Thomson-LCD
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present invention relates to an addressing method liquid crystal display for uniform quality display across the screen.
  • a liquid crystal display consists of a set image elements ("Pixels” for Picture Element in English) each formed by an electrode and a counter-electrode framing the liquid crystal, the value of the field between these electrodes modifying the optical properties of liquid crystal.
  • the voltage across the pixel electrodes is delivered via addressing columns by peripheral circuits ("Driver" in English) thanks to transistors control of these pixels, the passing and non-passing state of these transistors being determined by selection lines from other Line drivers.
  • FIG. 1 represents a selection line Lj of a liquid crystal screen with m lines and n columns, controlling the transistors T1 to Tn of the pixels P1 to Pn.
  • This line is connected to a line driver which delivers at A the square selection signal V A (t) as shown in FIG. 2.
  • the signal V A (t) turns on the transistors T1 to Tn of the line Lj and thus allows the polarization of the electrodes of the pixels P i by the video signal coming from the columns C 1 to C n .
  • the capacitors C cl represent the capacitive couplings between the line Lj and the counter-electrode CE through the liquid crystal.
  • This line Lj whose end is floating constitutes a delay line which results in a deformation of the selection signal at point B with respect to point A, this signal V B (t) at point B is shown in FIG. 2. This is particularly visible when one wishes to display a uniform image and when the same voltage is applied to all the columns C 1 to C n of the screen.
  • the voltage across the capacitors Cp constituted by the electrodes of the pixels P i and the counter-electrode CE is the same. However, after the instant t F this is no longer the case due to the difference between the forms of the signals V A (t) and V B (t).
  • V 1 is the voltage supplied to the pixel P1 by the column C1
  • the voltage .DELTA.V 1 drop across the pixel at the time when the transistor T1 becomes non-conducting is illustrated in Figure 3a, this being the voltage V of the counter electrode.
  • the capacitive coupling phenomenon is identical, but in this case, the transistor T n remains on as long as the voltage V B (t) is greater than V 1 + V t ' where V t is the threshold voltage of the transistor.
  • the coupling ⁇ V n between the line L j and the last pixel P n is therefore weaker than ⁇ V 1 , because as long as the transistor T n is on, the voltage across the pixels remains equal to the voltage delivered by the column C n .
  • ⁇ V ' being the voltage drop at point B.
  • the gray level is therefore not the same at the beginning and at the end of the line. This so-called "horizontal gradient" problem is particularly important for large screens.
  • the present invention provides a simple and effective solution to this. "horizontal gradient" problem.
  • the method according to the invention consists in periodically scanning each line by a voltage signal as a function of the time applied to the control of the switching element, each period consisting of a level then a curve.
  • the method is characterized in that the curve is chosen to go from the value of the bearing to the blocking voltage of the element switching at a time t> 0.
  • this process also makes it possible to reduce the coupling and therefore the parasitic voltages on a screen.
  • FIG. 4a An embodiment of the present invention is shown in FIG. 4a and consists in modifying the shape of the signal delivered by the selection circuit in order to compensate for the delay effect of the line responsible for the horizontal gradient.
  • the signal V a (t) does not decrease suddenly (after a plateau of duration t F - t j ), but from t F with a slope ⁇ preferably less than or equal to the characteristic slope of the delay line at point B, that is to say that ⁇ is less than ⁇ V / ⁇ , ⁇ being the characteristic time of the delay line in B and ⁇ V the potential drop at point A.
  • An example of the value of ⁇ can be a few volts per ⁇ s. This signal thus decreases until the voltage V A (t) is equal to V F ' , voltage for which the transistors T1 to Tn are blocked. From this instant t F ' , the signal drops instantly.
  • the signal is the same at point A and B, all the transistors of the line maintaining the voltages constants on pixels.
  • the selection signal with delay provided with a slope ⁇ between t F and t F ' is shown in Figures 4b.
  • a refinement of the method consists in using between t F and t F ' a curve which is not a straight line portion but a portion of a function f (t) which remains unchanged by the transfer function of the delay line : applying f (t) to T 1 results in applying f (t - T) to T n , T being a delay.
  • f (t) can for example be a sinusoid or a sum of sinusoids.
  • This method according to the invention can be implemented by a "driver" having an input which makes it possible to control the output current.
  • a "driver” having an input which makes it possible to control the output current.
  • the desired signal is obtained at the output of the "driver” by modulating this input so as to obtain a V H wave having an inverted sawtooth shape as illustrated in FIG. 6. That is to say each line 1 , 2, 3, 4, etc ... the high level V H is maintained on a level for a line period until time T F , then lowered linearly until time T F ' to be instantly raised again at this landing and sweep the next line.
  • the present invention can be used for repair LCD flat screen. Indeed, there are procedures known repairs but which do not work because they increase the RC of the repaired line, which makes it visible because it does not not undergo the same coupling as the neighboring lines. Taking for ⁇ the greater of the characteristic times repaired line or normal lines, repaired lines become similar to neighboring lines.
  • the present invention applies to the control of flat screens liquid crystal with peripheral or integrated drivers, and especially large screens.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

La présente invention concerne un procédé d'adressage d'écran à cristaux liquides permettant un affichage de qualité uniforme sur toute la ligne de l'écran.The present invention relates to an addressing method liquid crystal display for uniform quality display across the screen.

Un écran à cristaux liquides est constitué d'un ensemble d'éléments images ("Pixels" pour Picture Element en langue anglaise) formés chacun d'une électrode et d'une contre-électrode encadrant le cristal liquide, la valeur du champ entre ces électrodes modifiant les propriétés optiques du cristal liquide. La tension aux bornes des électrodes des pixels est délivrée via des colonnes d'adressage par des circuits périphériques ("Driver" en langue anglaise) grâce aux transistors de commande de ces pixels, l'état passant et non passant de ces transistors étant déterminés par des lignes de sélection issues d'autres Drivers-lignes.A liquid crystal display consists of a set image elements ("Pixels" for Picture Element in English) each formed by an electrode and a counter-electrode framing the liquid crystal, the value of the field between these electrodes modifying the optical properties of liquid crystal. The voltage across the pixel electrodes is delivered via addressing columns by peripheral circuits ("Driver" in English) thanks to transistors control of these pixels, the passing and non-passing state of these transistors being determined by selection lines from other Line drivers.

La figure 1 représente une ligne de sélection Lj d'un écran à cristal liquide à m lignes et n colonnes, commandant les transistors T1 à Tn des pixels P1 à Pn. Cette ligne est connectée à un driver-lignes qui délivre en A le signal de sélection carré VA (t) tel que représenté sur la figure 2. Le signal VA (t) rend passant les transistors T1 à Tn de la ligne Lj et permet ainsi la polarisation des électrodes des pixels Pi par le signal vidéo issu des colonnes C1 à Cn. Les capacités Ccl représentent les couplages capacitifs entre la ligne Lj et la contre-électrode CE au travers du cristal liquide. Cette ligne Lj dont l'extrémité est flottante constitue une ligne de retard qui se traduit par une déformation du signal de sélection au point B par rapport au point A, ce signal VB(t) au point B est représenté sur la figure 2. Cela est particulièrement visible lorsque l'on désire afficher une image uniforme et que l'on applique la même tension sur toutes les colonnes C1 à Cn de l'écran. A l'instant tF, la tension aux bornes des capacités Cp constituée par les électrodes des pixels Pi et la contre-électrode CE est la même. Cependant, après l'instant tF cela n'est plus le cas du fait de la différence entre les formes des signaux VA(t) et VB(t). FIG. 1 represents a selection line Lj of a liquid crystal screen with m lines and n columns, controlling the transistors T1 to Tn of the pixels P1 to Pn. This line is connected to a line driver which delivers at A the square selection signal V A (t) as shown in FIG. 2. The signal V A (t) turns on the transistors T1 to Tn of the line Lj and thus allows the polarization of the electrodes of the pixels P i by the video signal coming from the columns C 1 to C n . The capacitors C cl represent the capacitive couplings between the line Lj and the counter-electrode CE through the liquid crystal. This line Lj whose end is floating constitutes a delay line which results in a deformation of the selection signal at point B with respect to point A, this signal V B (t) at point B is shown in FIG. 2. This is particularly visible when one wishes to display a uniform image and when the same voltage is applied to all the columns C 1 to C n of the screen. At the instant t F , the voltage across the capacitors Cp constituted by the electrodes of the pixels P i and the counter-electrode CE is the same. However, after the instant t F this is no longer the case due to the difference between the forms of the signals V A (t) and V B (t).

En effet, au point A, la chute de tension est très rapide, le transistor T1 est donc bloqué immédiatement après tF. Par ailleurs, il existe une capacité parasite Cp entre la ligne Lj et les pixels Pj. La chute de tension ΔVG au point A entraíne ainsi par couplage capacitif une chute de tension sur le pixel qui est : ΔV1 = Cp/Cpi x ΔVG Indeed, at point A, the voltage drop is very rapid, the transistor T 1 is therefore blocked immediately after t F. Furthermore, there is a stray capacitance C p between the line L j and the pixels P j . The voltage drop ΔV G at point A thus causes by capacitive coupling a voltage drop on the pixel which is: ΔV 1 = C p /VS pi x ΔV G

Si V1 est la tension fournie au pixel P1 par la colonne C1, la chute de tension ΔV1 sur le pixel à l'instant où le transistor T1 devient non-passant est illustrée par la figure 3a, Vce étant la tension de la contre-électrode.If V 1 is the voltage supplied to the pixel P1 by the column C1, the voltage .DELTA.V 1 drop across the pixel at the time when the transistor T1 becomes non-conducting is illustrated in Figure 3a, this being the voltage V of the counter electrode.

Au point B, le phénomène de couplage capacitif est identique, mais dans ce cas, le transistor Tn reste passant tant que la tension VB(t) est supérieure à V1 + Vt' où Vt est la tension de seuil du transistor. Le couplage ΔVn entre la ligne Lj et le dernier pixel Pn est donc plus faible que ΔV1, car tant que le transistor Tn est passant, la tension aux bornes des pixels reste égale à la tension délivrée par la colonne Cn. Le couplage capacitif entraíne donc une chute de tension pour le pixel Pn : ΔVn = Cp/Cpi x ΔV', At point B, the capacitive coupling phenomenon is identical, but in this case, the transistor T n remains on as long as the voltage V B (t) is greater than V 1 + V t ' where V t is the threshold voltage of the transistor. The coupling ΔV n between the line L j and the last pixel P n is therefore weaker than ΔV 1 , because as long as the transistor T n is on, the voltage across the pixels remains equal to the voltage delivered by the column C n . The capacitive coupling therefore causes a voltage drop for the pixel P n : ΔV not = C p /VS pi x ΔV ',

ΔV' étant la chute de tension au point B.ΔV 'being the voltage drop at point B.

La tension qui permet aux pixels de modifier les propriétés optiques du cristal liquide est donc Vpix1 = V1-Vce pour le pixel P1 et Vpixn = Vn-Vce pour le pixel Pn, Vpix1 étant différent de Vpixn. C'est ce qui est représenté sur la figure 3b. Le niveau de gris n'est donc pas le même en début et en fin de ligne. Ce problème dit de « dégradé horizontal » est particulièrement important pour les écrans de grande taille.The voltage which allows the pixels to modify the optical properties of the liquid crystal is therefore V pix1 = V 1 -V ce for the pixel P 1 and V pixn = V n -V ce for the pixel P n , V pix1 being different from V pixn . This is what is shown in Figure 3b. The gray level is therefore not the same at the beginning and at the end of the line. This so-called "horizontal gradient" problem is particularly important for large screens.

Une solution fréquemment utilisée et décrite dans le document SID 94 Digest, page 263, consiste à utiliser une contre-impulsion pour diminuer cet effet. Cette solution est coûteuse car elle oblige à réaliser des « drivers » plus compliqués.A solution frequently used and described in the document SID 94 Digest, page 263, consists of using a counter-pulse to reduce this effect. This solution is costly because it requires more "drivers" complicated.

Une autre solution fréquemment utilisée consiste à réduire la résistivité des lignes. Cependant, cela implique d'augmenter l'épaisseur du métal utilisé pour réaliser la ligne, ce qui rend le procédé plus coûteux et plus difficile à maítriser.Another frequently used solution is to reduce the resistivity lines. However, this involves increasing the thickness of the metal used to realize the line, which makes the process more expensive and more difficult to control.

Encore une autre solution est suggérée dans le brevet EP-A-0574920. Ce document décrit un procédé d'adressage matriciel dans lequel on balaie périodiquement chaque ligne avec un signal périodique de tension GP en fonction du temps. Ce signal appliqué sur la grille du transistor de commutation de l'écran matriciel à cristaux liquides comporte un palier puis une pente douce, ceci pour éviter la décharge instantanée de la charge stockée dans la capacité du cristal liquide.Yet another solution is suggested in patent EP-A-0574920. This document describes a matrix addressing process in which we scan periodically each line with a periodic voltage signal GP in function time. This signal applied to the gate of the screen switching transistor liquid crystal matrix has a level then a gentle slope, this for avoid the instantaneous discharge of the charge stored in the crystal capacity liquid.

La présente invention propose une solution simple et efficace à ce problème de « dégradé horizontal ». The present invention provides a simple and effective solution to this. "horizontal gradient" problem.

En effet, le procédé selon l'invention consiste à balayer périodiquement chaque ligne par un signal de tension en fonction du temps appliqué sur la commande de l'élément de commutation, chaque période étant constituée par un palier puis une courbe. Le procédé est caractérisé en ce que la courbe est choisie pour passer de la valeur du palier à la tension de blocage de l'élément de commutation en un temps t>0.In fact, the method according to the invention consists in periodically scanning each line by a voltage signal as a function of the time applied to the control of the switching element, each period consisting of a level then a curve. The method is characterized in that the curve is chosen to go from the value of the bearing to the blocking voltage of the element switching at a time t> 0.

Ces caractéristiques peuvent être facilement mises en oeuvre grâce à des drivers ayant une entrée analogique VDD permettant de contrôler le niveau haut VH, comme par exemple les drivers de Toshiba du type T6A02/T6A03.These characteristics can be easily implemented thanks to drivers with an analog VDD input to control the level high VH, like for example the Toshiba drivers of the T6A02 / T6A03 type.

D'autre part, ce procédé permet également de diminuer le couplage et donc les tensions parasites sur un écran.On the other hand, this process also makes it possible to reduce the coupling and therefore the parasitic voltages on a screen.

La présente invention sera mieux comprise et des avantages supplémentaires apparaítront à la lecture de la description qui va suivre illustrée par les figures suivantes :

  • la figure 1 déjà décrite est un schéma d'un exemple de lignes d'un écran à cristaux liquides,
  • la figure 2 déjà décrite représente le signal de sélection tel qu'il est reçu en début de ligne et en fin de ligne, et illustre le problème posé du retard de la ligne,
  • les figures 3a et 3b représentent les tensions des pixels en début et fin de ligne,
  • les figures 4a et 4b représentent respectivement les signaux selon l'invention reçus respectivement en début et fin de ligne,
  • les figures 5a et 5b représentent les tensions des pixels commandés selon l'invention respectivement en début et en fin de ligne,
  • et la figure 6 représente la forme du niveau haut de référence d'un driver permettant la mise en oeuvre de l'invention.
The present invention will be better understood and additional advantages will appear on reading the description which follows, illustrated by the following figures:
  • FIG. 1 already described is a diagram of an example of lines of a liquid crystal screen,
  • FIG. 2 already described represents the selection signal as it is received at the start of the line and at the end of the line, and illustrates the problem posed by the delay of the line,
  • FIGS. 3a and 3b represent the voltages of the pixels at the start and end of the line,
  • FIGS. 4a and 4b respectively represent the signals according to the invention received respectively at the start and end of the line,
  • FIGS. 5a and 5b represent the voltages of the pixels controlled according to the invention respectively at the start and at the end of the line,
  • and FIG. 6 represents the shape of the high reference level of a driver allowing the implementation of the invention.

Un mode de réalisation de la présente invention est représenté par la figure 4a et consiste à modifier la forme du signal délivré par le circuit de sélection afin de compenser l'effet de retard de la ligne responsable du dégradé horizontal. Après un palier d'une largeur par exemple de 28µs et selon une caractéristique importante de l'invention, le signal Va (t) ne décroít pas brutalement (après un palier de durée tF - tj), mais à partir de tF avec une pente α de préférence plus faible ou égale à la pente caractéristique de la ligne à retard au point B, c'est-à-dire que α est inférieur à ΔV/τ, τ étant le temps caractéristique de la ligne à retard en B et ΔV la chute de potentiel au point A. Un exemple de valeur de α peut être de quelques volts par µs. Ce signal décroít ainsi jusqu'à ce que la tension VA (t) soit égale à VF', tension pour laquelle les transistors T1 à Tn sont bloqués. A partir de cet instant tF', le signal chute instantanément.An embodiment of the present invention is shown in FIG. 4a and consists in modifying the shape of the signal delivered by the selection circuit in order to compensate for the delay effect of the line responsible for the horizontal gradient. After a plateau with a width for example of 28 μs and according to an important characteristic of the invention, the signal V a (t) does not decrease suddenly (after a plateau of duration t F - t j ), but from t F with a slope α preferably less than or equal to the characteristic slope of the delay line at point B, that is to say that α is less than ΔV / τ, τ being the characteristic time of the delay line in B and ΔV the potential drop at point A. An example of the value of α can be a few volts per µs. This signal thus decreases until the voltage V A (t) is equal to V F ' , voltage for which the transistors T1 to Tn are blocked. From this instant t F ' , the signal drops instantly.

Ainsi, entre tF et tF' (la durée tF'-tF peut être par exemple égale à 3µs pour 6 volts), le signal est le même au point A et B, tous les transistors de la ligne maintenant les tensions constantes sur les pixels. Le signal de sélection avec retard muni d'une pente α entre tF et tF' est représenté sur les figures 4b.Thus, between t F and t F ' (the duration t F' -t F can be for example equal to 3 μs for 6 volts), the signal is the same at point A and B, all the transistors of the line maintaining the voltages constants on pixels. The selection signal with delay provided with a slope α between t F and t F ' is shown in Figures 4b.

A partir de l'instant TF', les transistors T1 et Tn sont bloqués, le couplage est donc ΔV1 = ΔV2 = CP/C x ΔV. Les tensions aux bornes des pixels P1 et Pn sont illustrées respectivement par les figures 5a et 5b. On constate que les tensions des pixels P1 à Pn sont égales et qu'il n'y a par conséquent plus de dégradé horizontal.From the instant T F ' , the transistors T 1 and T n are blocked, the coupling is therefore ΔV 1 = ΔV 2 = C P / C x ΔV. The voltages at the terminals of the pixels P 1 and P n are illustrated respectively by FIGS. 5a and 5b. It can be seen that the voltages of the pixels P 1 to P n are equal and that there is therefore no longer any horizontal gradient.

Un raffinement de la méthode consiste à utiliser entre tF et tF' une courbe qui n'est pas une portion de droite mais une portion d'une fonction f(t) qui reste inchangée par la fonction de transfert de la ligne à retard : appliquer f(t) sur T1 résulte à appliquer f(t - T) sur Tn, T étant un retard. f(t) peut être par exemple une sinusoïde ou une somme de sinusoïdes.A refinement of the method consists in using between t F and t F ' a curve which is not a straight line portion but a portion of a function f (t) which remains unchanged by the transfer function of the delay line : applying f (t) to T 1 results in applying f (t - T) to T n , T being a delay. f (t) can for example be a sinusoid or a sum of sinusoids.

Ce procédé selon l'invention peut être mis en oeuvre par un "driver" ayant une entrée qui permet de contrôler le courant de sortie. En limitant fortement le courant de sortie entre tF et tF', on peut modifier le signal standard pour obtenir la forme d'onde désirée.This method according to the invention can be implemented by a "driver" having an input which makes it possible to control the output current. By strongly limiting the output current between t F and t F ' , the standard signal can be modified to obtain the desired waveform.

On peut aussi utiliser des "drivers" qui ont une entrée analogique qui permet de définir le niveau haut VH. On obtient le signal désiré en sortie du "driver" en modulant cette entrée de manière à obtenir une onde VH ayant une forme en dents de scie inversées telle qu'illustrée par la figure 6. C'est-à-dire chaque ligne 1, 2, 3, 4, etc ... le niveau haut VH est maintenu sur un palier pendant une période ligne jusqu'à l'instant TF, puis descendu linéairement jusqu'à l'instant TF' pour être instantanément remonté à nouveau audit palier et balayer la ligne suivante.One can also use "drivers" which have an analog input which makes it possible to define the high level V H. The desired signal is obtained at the output of the "driver" by modulating this input so as to obtain a V H wave having an inverted sawtooth shape as illustrated in FIG. 6. That is to say each line 1 , 2, 3, 4, etc ... the high level V H is maintained on a level for a line period until time T F , then lowered linearly until time T F ' to be instantly raised again at this landing and sweep the next line.

La présente invention peut être utilisée pour la réparation d'écran plat à cristaux liquides. En effet, il existe des procédures connues de réparation mais qui ne fonctionnent pas car elles augmentent le RC de la ligne réparée, ce qui la rend visible car elle ne subit pas le même couplage que les lignes voisines. En prenant pour τ le plus grand des temps caractéristiques ligne réparée ou lignes normales, les lignes réparées deviennent semblables aux lignes voisines.The present invention can be used for repair LCD flat screen. Indeed, there are procedures known repairs but which do not work because they increase the RC of the repaired line, which makes it visible because it does not not undergo the same coupling as the neighboring lines. Taking for τ the greater of the characteristic times repaired line or normal lines, repaired lines become similar to neighboring lines.

La présente invention s'applique à la commande d'écrans plats à cristaux liquides comportant des drivers périphériques ou intégrés, et en particulier à des écrans de grandes tailles.The present invention applies to the control of flat screens liquid crystal with peripheral or integrated drivers, and especially large screens.

Claims (9)

  1. Method of matrix addressing of a screen periodically scanning each line (Lj) with a periodic time-varying voltage signal (VA(t)) applied to the control of a switching element, each period of this signal (VA(t)) consisting of a plateau and then a curve f(t), characterized in that the curve f(t) is chosen in order to pass from the plateau value to the voltage for turning off the switching element at a time t > 0.
  2. Method of matrix addressing according to Claim 1, characterized in that f(t) is a straight-line portion of slope (α).
  3. Method of matrix addressing according to Claim 1, characterized in that f(t) is a sinusoidal portion of amplitude A and angular frequency w.
  4. Method of matrix addressing according to Claim 1, characterized in that f(t) is a portion of a sum of sinusoids of amplitudes Ai and of angular frequency wi.
  5. Method of matrix addressing according to Claim 3 or 4, characterized in that the coefficients of the sinusoid or sinusoids are calculated in such a way that f(t) is unchanged at the start and at the end of the line.
  6. Method of matrix addressing according to Claim 2, characterized in that the value of the slope (α) of the signal is less than the value of the characteristic slope of the delay line at the end of line (B).
  7. Addressing method according to one of Claims 2 and 6, characterized in that. the slope (α) is a negative slope.
  8. Addressing method according to one of Claims 1 to 7, characterized in that the signal (VA(t)) is delivered by a peripheral addressing circuit having an input which makes it possible to control the output current.
  9. Addressing method according to one of Claims 1 to 7, characterized in that this signal (VA(t)) is delivered by an addressing circuit having an analogue input making it possible to define the high level in the output and modulated by an inverse-sawtooth signal of line period.
EP95927008A 1994-08-02 1995-08-02 Method for optimised addressing of a liquid crystal display Expired - Lifetime EP0774150B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9409586A FR2723462B1 (en) 1994-08-02 1994-08-02 OPTIMIZED ADDRESSING METHOD OF LIQUID CRYSTAL SCREEN AND DEVICE FOR IMPLEMENTING SAME
FR9409586 1994-09-02
PCT/FR1995/001038 WO1996004640A1 (en) 1994-08-02 1995-08-02 Method for optimised addressing of a liquid crystal display and device for implementing same

Publications (2)

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EP0774150A1 EP0774150A1 (en) 1997-05-21
EP0774150B1 true EP0774150B1 (en) 2001-10-31

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EP95927008A Expired - Lifetime EP0774150B1 (en) 1994-08-02 1995-08-02 Method for optimised addressing of a liquid crystal display

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US (1) US5995075A (en)
EP (1) EP0774150B1 (en)
JP (1) JPH10504911A (en)
KR (1) KR100366476B1 (en)
DE (1) DE69523601T2 (en)
FR (1) FR2723462B1 (en)
WO (1) WO1996004640A1 (en)

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JP3406508B2 (en) 1998-03-27 2003-05-12 シャープ株式会社 Display device and display method
KR100796787B1 (en) * 2001-01-04 2008-01-22 삼성전자주식회사 Liquid crystal display system, panel and method for compensating gate line delay
KR100830098B1 (en) * 2001-12-27 2008-05-20 엘지디스플레이 주식회사 Liquid crystal display and driving method thereof
WO2003068920A2 (en) 2002-02-13 2003-08-21 Ludwig Institute For Cancer Research Humanized gm-csf antibodies
KR100796298B1 (en) * 2002-08-30 2008-01-21 삼성전자주식회사 Liquid crystal display
TWI251183B (en) * 2003-05-16 2006-03-11 Toshiba Matsushita Display Tec Active matrix display device
TWI253051B (en) * 2004-10-28 2006-04-11 Quanta Display Inc Gate driving method and circuit for liquid crystal display
JP4667904B2 (en) * 2005-02-22 2011-04-13 株式会社 日立ディスプレイズ Display device
US8411006B2 (en) * 2005-11-04 2013-04-02 Sharp Kabushiki Kaisha Display device including scan signal line driving circuits connected via signal wiring
WO2008032468A1 (en) * 2006-09-15 2008-03-20 Sharp Kabushiki Kaisha Display apparatus
JP2008304513A (en) * 2007-06-05 2008-12-18 Funai Electric Co Ltd Liquid crystal display device and driving method thereof
CN101779227B (en) * 2007-10-24 2012-03-28 夏普株式会社 Display panel and display
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JP2011128642A (en) * 2011-02-03 2011-06-30 Sharp Corp Display device
CN107533828B (en) * 2015-04-07 2020-05-05 夏普株式会社 Active matrix display device and method of driving the same

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Also Published As

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FR2723462B1 (en) 1996-09-06
DE69523601D1 (en) 2001-12-06
EP0774150A1 (en) 1997-05-21
WO1996004640A1 (en) 1996-02-15
FR2723462A1 (en) 1996-02-09
DE69523601T2 (en) 2002-07-11
KR100366476B1 (en) 2003-03-06
JPH10504911A (en) 1998-05-12
US5995075A (en) 1999-11-30

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