EP0525168A1 - Demultiplexer comprising a three-state gate. - Google Patents

Demultiplexer comprising a three-state gate.

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Publication number
EP0525168A1
EP0525168A1 EP92906547A EP92906547A EP0525168A1 EP 0525168 A1 EP0525168 A1 EP 0525168A1 EP 92906547 A EP92906547 A EP 92906547A EP 92906547 A EP92906547 A EP 92906547A EP 0525168 A1 EP0525168 A1 EP 0525168A1
Authority
EP
European Patent Office
Prior art keywords
demultiplexer
lines
control electrode
voltage
coupling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92906547A
Other languages
German (de)
French (fr)
Other versions
EP0525168B1 (en
Inventor
Roger Stewart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technicolor SA
Original Assignee
Thomson SA
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Filing date
Publication date
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Publication of EP0525168A1 publication Critical patent/EP0525168A1/en
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters

Definitions

  • the present invention generally relates to
  • the circuit can be used as a three-state gate.
  • LCD liquid crystals
  • liquid crystal cells which are arranged at the intersection of data lines and selection lines.
  • the selection lines are selected in sequence to produce the horizontal lines of the display.
  • Data lines apply brightness signals to columns
  • Each liquid crystal cell is associated with a switching device by which a ramp-shaped voltage is applied to the liquid crystal cells in the line
  • Each of the switching devices is held by a comparator, or a counter, which receives the brightness signal (gray scale) to allow the ramp-shaped voltage to charge the device associated with liquid crystal at a voltage proportional to the level
  • the incoming signal is analog and must be digitized.
  • Each data line of the display must therefore be associated with a demultiplexer which has a
  • a display with a thousand lines of data and eight gray scale bits requires loading a total of eight thousand pieces of information for each line of image and would require 180 connections (twice the square root of eight thousand). Even with an optimized one-stage demultiplexer, this is an excessive number of outputs.
  • a two-stage demultiplexer considerably reduces the number of connections in proportion to the cube root, instead of being in proportion to the square root (three times the cube root of eight thousand). The number of outputs is therefore reduced from 180 to 60 by the use of a two-stage demultiplexing.
  • the demultiplexer 10 comprises sections 15-1 to 15-N, one for each bit of the digitized word.
  • Each section 15 includes a data input terminal 11, a capacitor 12, an input node 13, an intermediate node 14 and output nodes 16.
  • the capacitor 12 stores the data signal at the input to keep the node 13 at the data entry level.
  • Additional capacitors 17 and 18 keep the nodes 14 and 16 respectively at their applied voltage levels.
  • Each data entry section 15 has a most significant binary stage MSB (for "Most Significant Bit” in English) including several transistors 19 with a number equal to the number of lines MSB (including three, Ml, M2, M3 , are shown) upstairs.
  • the control electrode of each transistor is connected to one of the lines MSB M.
  • Each data input section 15 also has a least significant binary stage LSB (for "Least Significant Bit” in English) comprising several transistors 21 of a number equal to the number of LSB lines (of which four, L1 to L4, are shown) in the floor.
  • the control electrode of each transistor 21 is connected to one of the LSB lines L.
  • the transistors 19 and 21 are preferably TFT thin film transistors (for "Thm Film Transistors" in language 2> English).
  • the conductive link of each MSB TFT 19 is connected in series with the conductive links of all the LSB TFT 21. Consequently, each input signal is connected to an output line through two TFTs.
  • the current flows from the input node 13 to an output node 16 via the conductive links of the conductive TFTs.
  • the transistors 19-2 and 21-3 are on and the current flows from the input node 13 to the output node 16.
  • a demultiplexer with N sections for decoding an N-bit digital signal comprises an input terminal and an output node.
  • a most significant bit bus (MSB) has a large number of MSB lines and a least significant bit bus
  • LSB has a large number of LSB lines.
  • a number of transistors have their conductive link arranged between the input terminal and an output node.
  • a number of pairs of capacitive coupling means are connected in series to the junctions, each junction being connected to one of the control electrodes.
  • a pair of capacitive coupling means is therefore disposed between each of the lines MSB and each of the lines LSB, so that each line MSB is coupled to each line LSB.
  • Figure 1 shows a two-stage demultiplexer according to the prior art.
  • Figure 2 shows the voltages applicable to the circuit of Figure 1.
  • Figure 3 is a preferred embodiment.
  • Figures 4a and 4b show exemplary wave profiles of LSB and MSB respectively, for the embodiment of Figure 3.
  • FIG. 3 shows a demultiplexer 25 having N sections 30-1 to 30-N for demultiplexing N signals.
  • Each section 30 includes a data entry terminal 31 and a plurality of output nodes 32.
  • a plurality of semiconductor switching devices 33 which are preferably thin film transistors (TFT) have conductive links connected between the input terminal 31 and the respective output nodes 32
  • a bus 34 with most significant bits (MSB) comprises a first number of lines 34-1 to 34-X.
  • a least significant bit bus (LSB) 35 includes a second number of lines 35-1 to 35-Y. The product of the total number of lines on the bus at MSB 34 and on the bus at LSB 35 is 2 N.
  • the bus with MSB can comprise 32 lines and the bus with LSB 8 lines.
  • the control electrode of each TFT 33 is coupled to one of the MSB lines 34 by signal coupling means 36, which is preferably a capacitor.
  • the control electrode of each of the TFTs 33 is coupled by a coupling means 37, which is also preferably a capacitor, to one of the LSB lines 35.
  • the capacitors are connected in series to the junctions , and the junctions connected to the control electrodes.
  • the total number of TFT thin film transistors 33 in each section 30 of the demultiplexer 25 is a multiple of the number of lines on the MSB bus times the number of lines on the LSB bus 35.
  • Additional thin film transistors 38 have their conductive link connected between the TFT 33 control electrode and a reference potential.
  • the TFT control electrode 38 is connected to a preloaded line 39 and therefore the TFT 38 serve as a means for precharging the TFT control electrodes 33 to a voltage substantially equal to the blocking voltage of the TFT 33; in the example given, this voltage is mass.
  • the invention shown in Figure 3 eliminates the node 14 of the prior art demultiplexer shown in Figure 1 and thus structurally resembles a single-stage demultiplexer.
  • the equivalent of two levels of demultiplexing is obtained by coupling the G demultiplexing signal on each of the lines MSB and each of the lines LSB to the respective control electrodes passing through the capacitors 36 and 37, which are equivalent.
  • the preloaded TFTs 38 are used to simultaneously preload the TFT control electrodes 33 of all sections 30 to a fixed potential before normal operation of the demultiplexer begins.
  • the MSB 34 decoding lines and the LSB 35 decoding lines operate in a range of -20 to +20 volts.
  • Examples of voltage waveforms that can be used for one of the LSB lines 35 and one of the MSB lines 34 are shown in Figures 4a and 4b respectively.
  • the coefficients of use for the LSB and MSB wave profiles are equal to the inverse of the number of lines in the bus to which the wave profiles are applied.
  • the ratio of the activation pulse widths is equal to Y, therefore for the example given above, the pulse 42 is eight times wider than the pulse 41.
  • the potentials of the lines MSB and LSB are V M and V " L respectively and the capacitors 36 and 37 are equal.
  • the voltage coupled to the control electrode is roughly equal to (V ⁇ + V ⁇ .) / 2.
  • V j ⁇ and V ⁇ are both equal to -20 volts
  • the voltage at the control electrode is -20 volts.
  • the voltage applied to the control electrode is zero.
  • the TFT 33 remains in its blocked preloaded state.
  • the voltage of 20 volts is coupled to l control electrode of the TFT 33 and the TFT is energized for a short time determined by the pulse width of the signal having the smallest width. prc charge is applied at the end of each line period to reset the TFT 33 to the desired precharge voltage.
  • TFT 33 remains blocked until two positive inputs are received simultaneously. Consequently, in its widest application, the circuit object of ? the invention can be used as a gate with three single transistor states.
  • An advantage of the circuit which is the subject of the invention lies in the fact that it transfers the voltage from the input terminal 31 to the output node 32 through a single transistor and that it is therefore fast enough to be used in a display. liquid crystal.
  • Another advantage of the circuit object of the invention lies in the fact that it reduces the number of outputs pa by the same factor as the known two-stage demultiplexers.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Démultiplexeur (25) comprenant une pluralité de transistors (33, 38) avec des liaisons conductrices connectées entre une borne d'entrée (31) et des noeuds de sortie (32). L'électrode de commande de chaque transistor (33) est connectée à une ligne d'un bus à bits de poids fort (34) par un premier dispositif capacitif, l'électrode de commande de chaque transistor est aussi couplée à une ligne d'un bus à bits de poids faible (35) par un second dispositif capacitif. Quand les dispositifs capacitifs associés avec le même transistor reçoivent simultanément un signal d'activation, le transistor (33) devient passant et le courant passe de la borne d'entrée (31) à un noeud de sortie (32). Chaque transistor dans le démultiplexeur (25) agit ainsi comme une porte à trois états.A demultiplexer (25) comprising a plurality of transistors (33, 38) with conductive links connected between an input terminal (31) and output nodes (32). The control electrode of each transistor (33) is connected to a line of a most significant bit bus (34) by a first capacitive device, the control electrode of each transistor is also coupled to a line of a low order bit bus (35) by a second capacitive device. When the capacitive devices associated with the same transistor simultaneously receive an activation signal, the transistor (33) turns on and the current flows from the input terminal (31) to an output node (32). Each transistor in the demultiplexer (25) thus acts as a tri-state gate.

Description

4. 4.
DEMULTIPLEXEUR COMPRENANT UNE PORTE A TROIS ETATSDEMULTIPLEXER COMPRISING A THREE-STATE DOOR
La présente invention concerne généralement lesThe present invention generally relates to
5 démultiplexeurs et en particulier un circuit à un seul5 demultiplexers and in particular a single circuit
/ étage qui fonctionne comme un démultiplexeur à deux étages./ stage which functions as a two stage demultiplexer.
Dans ses caractéristiques les plus générales, le circuit peut être utilisé comme porte à trois états.In its most general characteristics, the circuit can be used as a three-state gate.
Les afficheurs de télévision et d'ordinateurs àTV and computer displays at
10 cristaux liquides (LCD) sont connus dans l'état de la technique. Par exemple, se référer aux brevets Américains 4.742.346 et 4.766.430, accordés tous deux à G.G. Gillette et al. et pris ici comme référence. Les afficheurs du type décrit dans les brevets Gillette comprennent une matrice de10 liquid crystals (LCD) are known in the state of the art. For example, refer to U.S. patents 4,742,346 and 4,766,430, both granted to G.G. Gillette et al. and taken here as a reference. Displays of the type described in the Gillette patents include a matrix of
15 cellules à cristaux liquides qui sont disposées aux croisements de lignes de données et de lignes de sélection. Les lignes de sélection sont sélectionnées en séquence pour produire les lignes horizontales de l'affichage. Les lignes de données appliquent les signaux de brillance aux colonnes15 liquid crystal cells which are arranged at the intersection of data lines and selection lines. The selection lines are selected in sequence to produce the horizontal lines of the display. Data lines apply brightness signals to columns
20 de cristaux liquides au fur et à mesure que les lignes de sélection sont sélectionnées en séquence. Chaque cellule de cristal liquide est associée avec un dispositif de commutation par lequel une tension en forme de rampe est appliquée aux cellules de cristaux liquides dans la ligne20 of liquid crystal as the selection lines are selected in sequence. Each liquid crystal cell is associated with a switching device by which a ramp-shaped voltage is applied to the liquid crystal cells in the line
25 de sélection. Chacun des dispositifs de commutation est tenu par un comparateur, ou un compteur, qui reçoit le signal de brillance (échelle de gris) pour permettre a la tension en forme de rampe de charger le dispositif associé à cristaux liquides à une tension proportionnelle au niveau25 selection. Each of the switching devices is held by a comparator, or a counter, which receives the brightness signal (gray scale) to allow the ramp-shaped voltage to charge the device associated with liquid crystal at a voltage proportional to the level
30 de brillance reçu de la ligne de données par le comparateur. Quand l'afficheur est un afficheur de télévision en couleurs, le signal entrant est analogique et doit être numérisé. Chaque ligne de données de l'afficheur doit donc être associée avec un démultiplexeur qui a un30 of brightness received from the data line by the comparator. When the display is a color television display, the incoming signal is analog and must be digitized. Each data line of the display must therefore be associated with a demultiplexer which has a
35 nombre d'étages suffisant pour appliquer tous les bits d'information du signal de brillance numérisé au comparateur pour cette ligne.35 number of stages sufficient to apply all the information bits of the digitized brightness signal to the comparator for this line.
Dans l'état de ιa technique, des multiplexeurs à deux étages sont utilisés pour réduire le nombre de connections.In the state of the art, multiplexers with two floors are used to reduce the number of connections.
Par exemple, un afficheur avec mille lignes de données et huit bits d'échelle de gris nécessite le chargement d'un total de huit mille éléments d'information pour chaque ligne d'image et nécessiterait 180 connections (deux fois la racine carrée de huit mille) . Même avec un démultiplexeur optimisé à un étage, c'est un nombre de sorties excessif. Un démultiplexeur à deux étages réduit considérablement le nombre de connections en proportion avec la racine cubique, au lieu d'être en proportion avec la racine carrée (trois fois la racine cubique de huit mille) . Le nombre de sorties est donc réduit de 180 à 60 par l'utilisation d'un démultiplexage à deux étages.For example, a display with a thousand lines of data and eight gray scale bits requires loading a total of eight thousand pieces of information for each line of image and would require 180 connections (twice the square root of eight thousand). Even with an optimized one-stage demultiplexer, this is an excessive number of outputs. A two-stage demultiplexer considerably reduces the number of connections in proportion to the cube root, instead of being in proportion to the square root (three times the cube root of eight thousand). The number of outputs is therefore reduced from 180 to 60 by the use of a two-stage demultiplexing.
Un circuit de démultiplexage à deux étages de l'état antérieur de la technique est montré sur la Figure 1. Le démultiplexeur 10 comprend les sections 15-1 à 15-N, une pour chaque bit du mot numérisé. Chaque section 15 comprend une borne d'entrée de données 11, un condensateur 12, un noeud d'entrée 13, un noeud intermédiaire 14 et des noeuds de sortie 16. Le condensateur 12 mémorise le signal de données à l'entrée pour garder le noeud 13 au niveau d'entrée de données. Des condensateurs supplémentaires 17 et 18 gardent les noeuds 14 et 16 respectivement à leurs niveaux de tension appliquée. Chaque section d'entrée de données 15 a un étage binaire de poids fort MSB (pour "Most Significant Bit" en langue anglaise) incluant plusieurs transistors 19 d'un nombre égal au nombre de lignes MSB (dont trois, Ml, M2, M3, sont montrées) dans l'étage. L'électrode de commande de chaque transistor est connectée à l'une des lignes MSB M. Chaque section d'entrée de données 15 a aussi un étage binaire de poids faible LSB (pour "Least Significant Bit" en langue anglaise) comprenant plusieurs transistors 21 d'un nombre égal au nombre de lignes LSB (dont quatre, Ll à L4, sont montrées) dans l'étage. L'électrode de commande de chaque transistor 21 est connectée à une des lignes LSB L. Les transistors 19 et 21 sont de préférence des transistors à couches minces TFT (pour "Thm Film Transistors" en langue 2> anglaise) . La liaison conductrice de chaque MSB TFT 19 est connectée en série avec les liaisons conductrices de tous les LSB TFT 21. En conséquence, chaque signal d'entrée est connecté à une ligne de sortie à travers deux TFT. Ainsi, quand une ligne MSB et une ligne LSB sont hautes simultanément, le courant s'écoule du noeud d'entrée 13 à un noeud de sortie 16 par les liaisons conductrices des TFT conducteurs. Par exemple, quand la ligne MSB M2 et la ligne LSB L3 sont hautes simultanément, les transistors 19-2 et 21-3 sont passants et le courant s'écoule du noeud d'entrée 13 au noeud de sortie 16.A two-stage demultiplexing circuit of the prior art is shown in Figure 1. The demultiplexer 10 comprises sections 15-1 to 15-N, one for each bit of the digitized word. Each section 15 includes a data input terminal 11, a capacitor 12, an input node 13, an intermediate node 14 and output nodes 16. The capacitor 12 stores the data signal at the input to keep the node 13 at the data entry level. Additional capacitors 17 and 18 keep the nodes 14 and 16 respectively at their applied voltage levels. Each data entry section 15 has a most significant binary stage MSB (for "Most Significant Bit" in English) including several transistors 19 with a number equal to the number of lines MSB (including three, Ml, M2, M3 , are shown) upstairs. The control electrode of each transistor is connected to one of the lines MSB M. Each data input section 15 also has a least significant binary stage LSB (for "Least Significant Bit" in English) comprising several transistors 21 of a number equal to the number of LSB lines (of which four, L1 to L4, are shown) in the floor. The control electrode of each transistor 21 is connected to one of the LSB lines L. The transistors 19 and 21 are preferably TFT thin film transistors (for "Thm Film Transistors" in language 2> English). The conductive link of each MSB TFT 19 is connected in series with the conductive links of all the LSB TFT 21. Consequently, each input signal is connected to an output line through two TFTs. Thus, when an MSB line and an LSB line are high simultaneously, the current flows from the input node 13 to an output node 16 via the conductive links of the conductive TFTs. For example, when the line MSB M2 and the line LSB L3 are high simultaneously, the transistors 19-2 and 21-3 are on and the current flows from the input node 13 to the output node 16.
Dans une situation d'excursion complète de tension, le ralentissement causé par l'impédance drain-source de deux TFT en série est dans un rapport d'environ deux, c'est-à- dire qu'un courant environ moitié plus fort passe par la combinaison en série et il faut environ deux fois plus longtemps pour charger le noeud 16. Cependant, dans les applications à grande vitesse, comme celles d'afficheur à LCD, le temps disponible pour le transfert de signal est très court et les excursions de signaux au noeud 14 ne sont pas les excursions complètes de tension. L'effet complet d'une combinaison de transistors en série dans un afficheur à grande vitesse est donc beaucoup plus mauvais qu'un rapport de deux. Dans la Figure 2, la tension d'entrée de données 22 s'élève fortement puis est sensiblement plate. La tension 23 sur le noeud 14 monte à peu près linéairement dans le temps.In a full voltage excursion situation, the deceleration caused by the drain-source impedance of two TFTs in series is in a ratio of about two, that is, about half the current flows by serial combination and it takes about twice as long to charge node 16. However, in high speed applications, such as those of LCD display, the time available for signal transfer is very short and excursions of signals at node 14 are not full voltage excursions. The full effect of a combination of transistors in series in a high speed display is therefore much worse than a ratio of two. In Figure 2, the data input voltage 22 rises sharply and then is substantially flat. The voltage 23 on the node 14 increases approximately linearly in time.
Cependant, la tension 24 sur le noeud 16 s'élève beaucoup plus lentement que celle sur le noeud 14. Ceci a lieu parce que le courant qui passe par l'étage décodeur de bit de poids faible vers le noeud de sortie 16 est proportionnel à la tension sur le noeud 14, qui s'élève à peu près linéairement avec le temps. La tension réelle sur le noeud de sortie 16 augmente proportionnellement au carré du temps. Par conséquent, pendant la courte période disponible pour le transfert de tension dans les applications avec LCD, le signal accouplé au noeud 16 est très faible. La réponse en fréquence de cet arrangement de démultiplexeur est donc limitée.However, voltage 24 on node 16 rises much more slowly than that on node 14. This occurs because the current flowing through the least significant bit decoder stage to output node 16 is proportional to the tension on node 14, which rises roughly linearly over time. The actual voltage on the output node 16 increases proportionally to the square of the time. Consequently, during the short period available for voltage transfer in applications with LCD, the signal coupled to node 16 is very weak. The frequency response of this arrangement of demultiplexer is therefore limited.
Pour ces raisons, il y a besoin d'un démultiplexeur à un étage qui permette la réduction du nombre de connections d'entrée possible avec un démultiplexeur à deux étages, tout en rendant possible simultanément la vitesse de fonctionnement nécessaire pour les dispositifs d'affichage à LCD et autres types. La présente invention satisfait ces besoins.For these reasons, there is a need for a single-stage demultiplexer which allows the reduction of the number of possible input connections with a two-stage demultiplexer, while simultaneously making possible the operating speed necessary for the display devices. LCD and other types. The present invention satisfies these needs.
Un démultiplexeur avec N sections pour décoder un signal numérique à N bits comprend une borne d'entrée et un noeud de sortie. Un bus à bits de poids fort (MSB) a un grand nombre de lignes MSB et un bus à bits de poids faibleA demultiplexer with N sections for decoding an N-bit digital signal comprises an input terminal and an output node. A most significant bit bus (MSB) has a large number of MSB lines and a least significant bit bus
(LSB) a un grand nombre de lignes LSB. Un certain nombre de transistors ont leur liaison conductrice disposée entre la borne d'entrée et un noeud de sortie. Un certain nombre de paires de moyens de couplage capacitif sont connectées en série aux jonctions, chaque jonction étant connectée à une des électrodes de commande. Une paire de moyens de couplage capacitif est donc disposée entre chacune des lignes MSB et chacune des lignes LSB, si bien que chaque ligne MSB est couplée à chaque ligne LSB.(LSB) has a large number of LSB lines. A number of transistors have their conductive link arranged between the input terminal and an output node. A number of pairs of capacitive coupling means are connected in series to the junctions, each junction being connected to one of the control electrodes. A pair of capacitive coupling means is therefore disposed between each of the lines MSB and each of the lines LSB, so that each line MSB is coupled to each line LSB.
Cette invention peut être utilisée avec l'invention décrite dans la demande de brevet S/N 600.046 déposée le 19 Octobre 1990 par Dora Plus et Léopold A. Harwood et qui a pour titre "Système pour l'application de signaux de brillance à un dispositif afficheur et Comparateur pour le réaliser".This invention can be used with the invention described in patent application S / N 600.046 filed on October 19, 1990 by Dora Plus and Léopold A. Harwood and which is entitled "System for the application of brightness signals to a device display and Comparator to make it ".
La Figure 1 montre un démultiplexeur à deux étages selon l'art antérieur. La Figure 2 montre les tensions applicables au circuit de la Figure 1.Figure 1 shows a two-stage demultiplexer according to the prior art. Figure 2 shows the voltages applicable to the circuit of Figure 1.
La Figure 3 est un mode de réalisation préférentiel. Les Figures 4a et 4b montrent des profils d'onde exemplaires de LSB et MSB respectivement, pour le mode de réalisation de la Figure 3.Figure 3 is a preferred embodiment. Figures 4a and 4b show exemplary wave profiles of LSB and MSB respectively, for the embodiment of Figure 3.
La Figure 3 montre un démultiplexeur 25 ayant N sections 30-1 à 30-N pour démultiplexer N signaux. Chaque section 30 comprend une borne d'entrée de données 31 et une pluralité de noeuds de sortie 32. Une pluralité de dispositifs de commutation à semi-conducteurs 33, qui sont de préférence des transistors à couches minces (TFT) ont des liaisons conductrices connectées entre la borne d'entrée 31 et les noeuds respectifs de sortie 32. Un bus 34 à bits de poids fort (MSB) comprend un premier nombre de lignes 34-1 à 34-X. Un bus 35 à bits de poids faible (LSB) comprend un deuxième nombre de lignes 35-1 à 35-Y. Le produit du nombre total de lignes dans le bus à MSB 34 et dans le bus à LSB 35 est égal à 2N. Ainsi, par exemple pour un démultiplexeur de rapport 2N = 256 à un, le bus à MSB peut comprendre 32 lignes et le bus à LSB 8 lignes. L'électrode de commande de chaque TFT 33 est couplée à l'une des lignes MSB 34 par un moyen de couplage de signaux 36, qui est de préférence un condensateur. De plus, l'électrode de commande de chacun des TFT 33 est couplée par un moyen de couplage 37, qui est aussi de préférence un condensateur, à l'une des lignes LSB 35. En fait, les condensateurs sont connectés en série aux jonctions, et les jonctions connectées aux électrodes de commande. Le nombre total de transistors à couches minces TFT 33 dans chaque section 30 du démultiplexeur 25 est un multiple du nombre de lignes dans le bus à MSB fois le nombre de lignes dans le bus à LSB 35. Des transistors supplémentaires à couches minces 38 ont leur liaison conductrice connectée entre l'électrode de commande des TFT 33 et un potentiel de référence. L'électrode de commande des TFT 38 est connectée à une ligne préchargée 39 et en conséquence, les TFT 38 servent de moyen pour précharger les électrodes de commande des TFT 33 à une tension sensiblement égale à la tension de blocage des TFT 33 ; dans l'exemple donné, cette tension est la masse.Figure 3 shows a demultiplexer 25 having N sections 30-1 to 30-N for demultiplexing N signals. Each section 30 includes a data entry terminal 31 and a plurality of output nodes 32. A plurality of semiconductor switching devices 33, which are preferably thin film transistors (TFT) have conductive links connected between the input terminal 31 and the respective output nodes 32 A bus 34 with most significant bits (MSB) comprises a first number of lines 34-1 to 34-X. A least significant bit bus (LSB) 35 includes a second number of lines 35-1 to 35-Y. The product of the total number of lines on the bus at MSB 34 and on the bus at LSB 35 is 2 N. Thus, for example for a demultiplexer of ratio 2 N = 256 to one, the bus with MSB can comprise 32 lines and the bus with LSB 8 lines. The control electrode of each TFT 33 is coupled to one of the MSB lines 34 by signal coupling means 36, which is preferably a capacitor. In addition, the control electrode of each of the TFTs 33 is coupled by a coupling means 37, which is also preferably a capacitor, to one of the LSB lines 35. In fact, the capacitors are connected in series to the junctions , and the junctions connected to the control electrodes. The total number of TFT thin film transistors 33 in each section 30 of the demultiplexer 25 is a multiple of the number of lines on the MSB bus times the number of lines on the LSB bus 35. Additional thin film transistors 38 have their conductive link connected between the TFT 33 control electrode and a reference potential. The TFT control electrode 38 is connected to a preloaded line 39 and therefore the TFT 38 serve as a means for precharging the TFT control electrodes 33 to a voltage substantially equal to the blocking voltage of the TFT 33; in the example given, this voltage is mass.
L'invention présentée sur la Figure 3 élimine le noeud 14 du démultiplexeur de l'état de la technique montré sur la Figure 1 et ainsi, ressemble structurellement à un démultiplexeur à un étage. Cependant, l'équivalent de deux niveaux de démultiplexage est obtenu par le couplage du G signal de démultiplexage sur chacune des lignes MSB et chacune des lignes LSB aux électrodes de commande respectives en passant par les condensateurs 36 et 37, qui sont équivalents. Les TFT 38 préchargés sont utilisés pour précharger simultanément les électrodes de commande des TFT 33 de toutes les sections 30 à un potentiel fixe avant que le fonctionnement normal du démultiplexeur ne commence.The invention shown in Figure 3 eliminates the node 14 of the prior art demultiplexer shown in Figure 1 and thus structurally resembles a single-stage demultiplexer. However, the equivalent of two levels of demultiplexing is obtained by coupling the G demultiplexing signal on each of the lines MSB and each of the lines LSB to the respective control electrodes passing through the capacitors 36 and 37, which are equivalent. The preloaded TFTs 38 are used to simultaneously preload the TFT control electrodes 33 of all sections 30 to a fixed potential before normal operation of the demultiplexer begins.
En fonctionnement, les lignes de décodage MSB 34 et les lignes de décodage LSB 35 fonctionnent dans une plage de -20 à +20 volts. Des exemples de profils d'onde de tension qui peuvent être utilisées pour une des lignes LSB 35 et une des lignes MSB 34 sont présentés sur les Figures 4a et 4b respectivement. Les coefficients d'utilisation pour les profils d'onde LSB et MSB sont égaux à l'inverse du nombre de lignes dans le bus auquel les profils d'onde sont .appliqués. Aussi, le rapport des largeurs d'impulsion d'activation est égal à Y, donc pour l'exemple donné ci- dessus, l'impulsion 42 est huit fois plus large que l'impulsion 41. Supposons que les potentiels des lignes MSB et LSB sont VM et V"L respectivement et que les condensateurs 36 et 37 sont égaux. La tension couplée à l'électrode de commande est en gros égale à (V^ + Vτ.) /2. Ainsi, quand Vj^ et V^ sont tous deux égaux à -20 volts, la tension à l'électrode de commande est -20 volts. Quand l'un des potentiels V^ ou V^ est de +20 volts et l'autre de -20 volts, la tension appliquée à l'électrode de commande est nulle. Pour ces trois conditions, le TFT 33 reste à son état préchargé bloqué. Quand les deux V^ et V_, sont égaux à +20 volts, la tension de 20 volts est couplée à l'électrode de commande du TFT 33 et le TFT est mis sous tension brutale pendant un temps court déterminé par la largeur d'impulsion du signal ayant la largeur la plus faible. Une impulsion de précharge pç est appliquée à la fin de chaque période de ligne pour remettre les TFT 33 à la tension désirée de précharge.In operation, the MSB 34 decoding lines and the LSB 35 decoding lines operate in a range of -20 to +20 volts. Examples of voltage waveforms that can be used for one of the LSB lines 35 and one of the MSB lines 34 are shown in Figures 4a and 4b respectively. The coefficients of use for the LSB and MSB wave profiles are equal to the inverse of the number of lines in the bus to which the wave profiles are applied. Also, the ratio of the activation pulse widths is equal to Y, therefore for the example given above, the pulse 42 is eight times wider than the pulse 41. Suppose that the potentials of the lines MSB and LSB are V M and V " L respectively and the capacitors 36 and 37 are equal. The voltage coupled to the control electrode is roughly equal to (V ^ + Vτ.) / 2. Thus, when V j ^ and V ^ are both equal to -20 volts, the voltage at the control electrode is -20 volts. When one of the potentials V ^ or V ^ is +20 volts and the other of -20 volts, the voltage applied to the control electrode is zero. For these three conditions, the TFT 33 remains in its blocked preloaded state. When the two V ^ and V_, are equal to +20 volts, the voltage of 20 volts is coupled to l control electrode of the TFT 33 and the TFT is energized for a short time determined by the pulse width of the signal having the smallest width. prc charge is applied at the end of each line period to reset the TFT 33 to the desired precharge voltage.
Les TFT 33 restent bloqués jusqu'à ce que deux entrées positives soient reçues simultanément. Par conséquence, dans son application la plus large, le circuit objet de ? l'invention peut être utilisé comme porte à trois états transistor unique. Un avantage du circuit objet d l'invention réside dans le fait qu'il transfère la tensio de la borne d'entrée 31 au noeud de sortie 32 à travers u transistor unique et qu'il est donc suffisamment rapid pour être utilisé dans un afficheur à cristaux liquides.TFT 33 remains blocked until two positive inputs are received simultaneously. Consequently, in its widest application, the circuit object of ? the invention can be used as a gate with three single transistor states. An advantage of the circuit which is the subject of the invention lies in the fact that it transfers the voltage from the input terminal 31 to the output node 32 through a single transistor and that it is therefore fast enough to be used in a display. liquid crystal.
Un autre avantage du circuit objet de l'inventio réside dans le fait qu'il réduit le nombre de sorties pa le même facteur que les démultiplexeurs à deux étages connus. Another advantage of the circuit object of the invention lies in the fact that it reduces the number of outputs pa by the same factor as the known two-stage demultiplexers.

Claims

REVENDICATIONS
1. Démultiplexeur (25) à N sections (30) pour décoder un signal numérique, chacune desdites sections (30) étant caractérisée en ce qu'elle comprend :1. Demultiplexer (25) with N sections (30) for decoding a digital signal, each of said sections (30) being characterized in that it comprises:
- une borne d'entrée (31) et au moins un noeud de sortie (32) ;- an input terminal (31) and at least one output node (32);
- un bus à poids fort (34) avec une pluralité de lignes MSB et un bus à poids faible avec une pluralité de lignes LSB (35) ;- a most significant bus (34) with a plurality of MSB lines and a least significant bus with a plurality of LSB lines (35);
- une pluralité de transistors (33) ayant des électrodes de commande et ayant des chemins de conduction disposés entre ladite borne d'entrée (31) et un noeud de sortie (32) ; - une pluralité de paires de moyens de couplage capacitif (36, 37) connectés en série aux jonctions, chacune desdites jonctions étant connectée à une desdites commandes, une paire desdits moyens de couplage capacitif (36, 37) étant disposée entre chacune desdites lignes MSB (34) et chacune desdites lignes LSB (35) .- a plurality of transistors (33) having control electrodes and having conduction paths arranged between said input terminal (31) and an output node (32); - a plurality of pairs of capacitive coupling means (36, 37) connected in series to the junctions, each of said junctions being connected to one of said controls, a pair of said capacitive coupling means (36, 37) being arranged between each of said MSB lines (34) and each of said LSB lines (35).
2. Démultiplexeur selon la revendication 1 caractérisé en ce que lesdits moyens de couplage capacitif (36, 37) sont des condensateurs équivalents.2. demultiplexer according to claim 1 characterized in that said capacitive coupling means (36, 37) are equivalent capacitors.
3. Démultiplexeur selon la revendication 2 caractérisé en ce qu'il comprend de plus des moyens (38) pour précharger ladite électrode de commande à une tension sensiblement égale à la tension de blocage dudit dispositif de commutation à semi-conducteurs (33) .3. demultiplexer according to claim 2 characterized in that it further comprises means (38) for precharging said control electrode to a voltage substantially equal to the blocking voltage of said semiconductor switching device (33).
4. Démultiplexeur selon la revendication 1 comprenant de plus des moyens (38) pour précharger ladite électrode de commande à une tension sensiblement égale à la tension de blocage dudit dispositif de commutation à semi-conducteurs (33) .4. The demultiplexer according to claim 1 further comprising means (38) for precharging said control electrode to a voltage substantially equal to the blocking voltage of said semiconductor switching device (33).
5. Démultiplexeur (25) ayant N sections (30) pour décoder un signal numérique à N bits, chacune desdites sections (30) étant caractérisée en ce qu'elle comprend : une borne d'entrée (31) ;5. Demultiplexer (25) having N sections (30) for decoding an N-bit digital signal, each of said sections (30) being characterized in that it comprises: an input terminal (31);
- au moins un noeud de sortie (32) ; - une pluralité de dispositifs de commutation à semi¬ conducteurs (33) ayant une électrode de commande et une liaison conductrice, la liaison conductrice de chacun desdits dispositifs de commutation (33) connectant la borne d'entrée (31) à un noeud de sortie (32) ; - un bus à bits de poids fort (34) ayant X lignes MSB pour recevoir les bits de poids fort dudit signal numérique ;- at least one output node (32); - a plurality of semiconductor switching devices (33) having a control electrode and a conductive link, the conductive link of each of said switch devices (33) connecting the input terminal (31) to an output node (32); - a most significant bit bus (34) having X MSB lines for receiving the most significant bits of said digital signal;
- un bus à bits de poids faible (35) ayant Y lignes LSB pour recevoir les bits de poids faible dudit signal numérique, où XY=2N ;- a least significant bit bus (35) having Y LSB lines for receiving the least significant bits of said digital signal, where XY = 2 N ;
- des moyens de premier (36) et second couplage (37) de signaux, couplant respectivement chacune desdites électrodes de commande à une desdites lignes MSB et à une desdites lignes LSB pour actionner lesdits dispositifs de commutation (33) afin de passer du courant de ladite borne d'entrée audit noeud de sortie quand les deux moyens de couplage de signaaux (36, 37) reçoivent une entrée logique ayant un niveau choisi.- first (36) and second coupling (37) signal means, respectively coupling each of said control electrodes to one of said MSB lines and to one of said LSB lines for actuating said switching devices (33) in order to pass current from said input terminal to said output node when the two signal coupling means (36, 37) receive a logic input having a selected level.
6. Démultiplexeur (25) selon la revendication 5 caractérisé en ce que chacune desdites lignes à poids fort et chacune des lignes à poids faible reçoivent des profils d'onde de tension différentes ayant des largeurs d'impulsion différentes et variant entre les mêmes valeurs négatives et positives, et lesdits dispositifs de commutation à semi-conducteurs (33) ne deviennent passants que lorsque ces deux tensions sont simultanément à la même polarité.6. demultiplexer (25) according to claim 5 characterized in that each of said high-weight lines and each of the low-weight lines receive different voltage wave profiles having different pulse widths and varying between the same negative values and positive, and said semiconductor switching devices (33) only turn on when these two voltages are simultaneously at the same polarity.
7. Démultiplexeur (25) selon la revendication 5 caractérisé en ce qu'il comprend de plus des moyens (38) pour précharger ladite électrode de commande à une tension sensiblement égale à la tension de blocage dudit dispositif de commutation à semi-conducteur (33) .7. demultiplexer (25) according to claim 5 characterized in that it further comprises means (38) for preloading said control electrode to a voltage substantially equal to the blocking voltage of said device semiconductor switch (33).
8. Démultiplexeur (25) selon la revendication 7 caractérisé en ce que ledit moyen pour précharger est un transistor (38) .8. demultiplexer (25) according to claim 7 characterized in that said means for preloading is a transistor (38).
9. Démultiplexeur (25) selon la revendication 7 caractérisé en ce que lesdits moyens de couplage (36, 37) de signaux sont des condensateurs équivalents.9. demultiplexer (25) according to claim 7 characterized in that said coupling means (36, 37) of signals are equivalent capacitors.
10. Démultiplexeur (25) selon la revendication 5 caractérisé en ce que lesdits moyens de couplage (36, 37) de signaux sont des condensateurs sensiblement égaux.10. Demultiplexer (25) according to claim 5 characterized in that said coupling means (36, 37) of signals are substantially equal capacitors.
11. Porte à trois états caractérisée en ce qu'elle comprend :11. Three-state door characterized in that it comprises:
- un transistor (33) ayant une électrode de commande et une liaison conductrice pour connecter ledit transistor entre une source de tension (31) et une borne de sortie (32) ;- a transistor (33) having a control electrode and a conductive link for connecting said transistor between a voltage source (31) and an output terminal (32);
- des premiers moyens (36) pour couplage réactif de ladite électrode de commande à un premier signal d'entrée ;- first means (36) for reactive coupling of said control electrode to a first input signal;
- des seconds moyens (37) pour couplage réactif de ladite électrode de commande à un second signal d'entrée, grâce à quoi le courant passe dans ladite liaison conductrice quand lesdits premiers et seconds moyens reçoivent simultanément des signaux d'activation.- second means (37) for reactive coupling of said control electrode to a second input signal, whereby the current flows through said conductive link when said first and second means simultaneously receive activation signals.
12. Porte à trois états selon la revendication 11 caractérisée en ce que lesdits moyens de couplage (36, 37) sont des condensateurs équivalents.12. Three-state door according to claim 11 characterized in that said coupling means (36, 37) are equivalent capacitors.
13. Porte à trois états selon la revendication 11 caractérisées en ce qu'elle comprend de plus des moyens (38) pour précharger ladite électrode de commande à une tension sensiblement égale à la tension de blocage dudit transistor (33) . 13. Three-state door according to claim 11 characterized in that it further comprises means (38) for precharging said control electrode at a voltage substantially equal to the blocking voltage of said transistor (33).
14. Porte à trois états selon la revendication 13 caractérisée en ce que lesdits moyens pour précharger sont un transistor supplémentaire (33).14. Three-state door according to claim 13 characterized in that said means for preloading are an additional transistor (33).
15. Porte à trois états selon la revendication 14 caractérisée en ce que lesdits moyens (36, 37) pour le couplage sont des condensateurs équivalents.15. Three-state door according to claim 14 characterized in that said means (36, 37) for coupling are equivalent capacitors.
16. Porte à trois états selon la revendication 15 caractérisée en ce que lesdits moyens (36, 37) pour le couplage sont des condensateurs équivalents. 16. Three-state door according to claim 15 characterized in that said means (36, 37) for coupling are equivalent capacitors.
EP92906547A 1991-02-14 1992-02-11 Demultiplexer comprising a three-state gate Expired - Lifetime EP0525168B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US655498 1984-09-28
US07/655,498 US5175446A (en) 1991-02-14 1991-02-14 Demultiplexer including a three-state gate
PCT/FR1992/000116 WO1992015085A1 (en) 1991-02-14 1992-02-11 Demultiplexer comprising a three-state gate

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EP0525168A1 true EP0525168A1 (en) 1993-02-03
EP0525168B1 EP0525168B1 (en) 1997-05-07

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US5175446A (en) 1992-12-29
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WO1992015085A1 (en) 1992-09-03
JPH05506347A (en) 1993-09-16
DE69219525T2 (en) 1997-09-11

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