TW501069B - Method of operating capacitive thin film transistor arrays - Google Patents

Abstract

A method of scanning a matrix of capacitors, with an associated matrix of TFT devices which are connected to respective capacitors, includes scanning the matrix of capacitors to sequentially precharge respective capacitors to a precharge voltage, and then scanning the matrix of capacitors to sequentially detect the capacitor charges and thereby to determine respective capacitor values. The TFT's operate as switches to connect respective capacitors to column electrodes which alternately operate as sources of precharge potential and sense electrodes. The precharge voltage is selected to have the same polarity as the turn-off transitions of the scanning pulses applied to the TFT's. Selecting the precharge voltage to have the same polarity as the TFT turn-off transitions tends to enhance the effective dynamic range of the detected charges.

Description

A7 B7 V. Description of the invention (feg field) The present invention relates to an operating TFT array and more particularly an operating TFT, S is used to scan a capacitive matrix array. MAN Jg Background It is known to use a thin film transistor (TFT) to describe an array element. For example, one method for performing fingerprint detection is to arrange an array of electrodes to act as individual capacitors of one version. See the example in FIG. 2. The convex and concave portions of one finger are brought close to the array to act as individual capacitors of the second version. The capacitance value of the array can be converted into an electronic image of fingerprints carried only to the vicinity of the array. The electron pattern can be formed by xy scanning and the capacitance value can be detected in a conventional order. The capacitance value is indirectly determined by measuring the charge on the capacitance. The array is scanned twice in sequence. In the first scan, each capacitor is represented by a TFT and precharged to a conventional voltage Vp. The charge on the respective capacitor is A, where q is each The capacitance of each array capacitor. In the second scan, the capacitance of each array 0 is discharged. That is, the charge is removed and integrated to provide an output voltage value. The detected voltage value is directly related Capacitance. Now consider the procedure of forming TFT and S on the substrate, such as forming a scanning capacitor array. This procedure is not as streamlined as the usual integrated circuit procedure. This complexity may cause undesired characteristics in manufacturing circuits ◊ For example, if a TFT is first deposited on the lower substrate via a sunk gate electrode and then a TFT body is formed on the gate electrode, the resulting transistor will generally have an undesired stacked capacitance. Second, the resulting transistor The equipment-will have a larger expected uninterrupted voltage and will inevitably require a larger excitation -4- I would like to ask #Mingyun Yun on the date of the amendments ^ Manshi 5? ^ Customers are ^^ to be amended. 5面 1 · ί · 2Ϊ Α7 Β7 V. Description of the invention (2) Consider how these characteristics affect the operation of the capacitive array fingerprint detector. The dynamic range of the capacitive array fingerprint is given the maximum to minimum capacitance that can be detected. The value ratio, or more appropriately, the maximum and minimum corresponding charges that can be detected. Assume that the maximum capacitance is associated with an electrode adjacent to a bump and the charge corresponding to Qmax and the minimum capacitance corresponds to a charge of Qmin. This period The dynamic range is Qmax / Qmin. The minimum capacitance value in this array is about an electrode that is not adjacent to any port of the finger. Its value is expected to be determined only by stray capacitance, and is assumed to be very small and odd. For economic reasons, the TFT's of the array can be formed using amorphous technology. The operating characteristics of these transistors are expected to be relatively large scanning pulses are supplied to the gates of these transistors. The large gate pulse voltage will be coupled, at least in part To the respective source and drain. Therefore, when a particular TFT is turned off by the gate, some charges will be coupled off the associated array capacitor. In the next scan, when the TFT is turned on by the gate to sense, assuming an equal amount of charge Will be coupled back to the array capacitor. The inventors will find that this assumption is incorrect and thus trigger the motivation of the present invention. It is found that a brief description of the array capacitor, and the larger capacitance value, will have a larger value than the gate-sink or gate-source overlapping capacitance of the TFT Multiple capacitors. Therefore, coupling all the charges with the gate closed will not significantly change the electrode (capacitance) voltage. Therefore the transistor, as expected, will turn off when the gate potential is supplied.

Array capacitors have a small capacitance value. On the contrary, they may have the same capacitance value or slightly smaller than the TFT gate-drain or gate-source overlapping capacitance. Therefore, it may have significant off-gate voltage coupling to the array capacitor electrodes. The gate-to-capacitance voltage can exceed the TFT's turn-on value (such as the threshold), so TFT -5 is excluded in advance. This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Members are kindly requested to indicate clearly the date mentioned on year, month, and day. • Are there any changes to the substance that are allowed to be amended? Variable Amplitude Pulse Generator Variable DC Source Capacitor Between TFT Gate and Drain Electrode Capacitance Operational Amplifier Switching Time between TFT Gate and Source Electrode A7 B7 V. Description of the Invention (3) Immediately close and insulate the capacitor electrode . This capacitor will eventually charge to the point where the TFT is turned off. As a result of this charging and charging, the additional charge, A Q, and unrelated capacitance related to fingerprints will occur in this capacitance. This has the effect of reducing the dynamic range of the scanning system. The expected system dynamic range of Qmax / Qmin is essentially Qmax / (Qmin + AQ) ο The inventors have learned that capacitor charging can be used after the charge transients can be used to enhance the apparent dynamic range. In the previous dynamic range ratio, if the charges Qmin and AQ are relatively polar, the charge will delete some Qmin charges and the denominator will tend to zero effectively increase the apparent dynamic range. The invention will be clearly clarified via the following scheme. Brief Description of the Drawings Figure 1 is a schematic diagram of a part of a previously scanned capacitor array; Figure 2 is a schematic diagram of a more detailed logic grid shown in Figure 1; Figure 3 is before and after the TFT gate pulse turn-off transient A waveform of one of the capacitors of the voltage switching array. FIG. 4 is a schematic diagram of a TFT scanning array embodied by the present invention. Component symbol description 40 42 Cgd Cgs

Op-Amp SI, S2, S3 Ti, T2 -6- This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm)

A7 B7 V. Explanation of the invention (4 TI3 9ί ί 29) I would like to ask members of Lou to indicate clearly whether the amendments mentioned in the amendments are permitted to be amended.

Til, TI2 TFT invention detailed description 2. The invention will be described in the context of a capacitive array fingerprint reader. No matter how, it will be found to make it wider. I typically the invention will be useful in all anti-smuggling arrays. Among them, a relatively large scanning pulse charger is used and the scanning τρτ is coupled to a high-impedance element including a partial capacitance. Referring to FIG. 1, a portion of a scanning capacitor array is illustrated. Here the capacitor array includes only one plate for each individual capacitor. The array is configured for xy scanning, and element scanning, or addressing, and is connected to each capacitor plate to perform * TFT. The gates or control electrodes of all TFTs in a row are coupled to a common gate drive electrode, and the drain electrodes of all TFTs in a row are connected to a common bus. The columns and rows around the circuit (not shown) will be sequentially gated and addressed for each column and row bus. Typically, in this type of array, a pulse will be supplied as a gate drive to a row of buses to turn on all TFTs, s to turn on in a row 'and then the row of buses will be scanned sequentially via the signal detection circuit. Figure 2 shows a logical grid of the array in detail. In FIG. 2, the existing and parasitic capacitive elements regarding the TFT are included. There is a capacitor, Cgd, between the TFT gate and the drain electrode, and a capacitor, Cgs, between the gate and the source electrode. Generally, the capacitance of these capacitors is as small as possible in terms of technical feasibility. In ordinary integrated circuit manufacturing, the value of these capacitors is very small due to the self-aligned gate technology. Unfortunately, the self-aligned gate fabrication technology cannot be used for the manufacture of a specific type of TFT's and the resulting Cgs and Cgd capacitance values may be relatively large. Periodic thin film transistor This paper size is in accordance with Chinese National Standard (CNS) A4 specification (21 × 297 mm) Binder line 5. Description of the invention (5) The detector capacitor is shown as an array board with a solid line drawing and a dotted line drawing The second board. The second board is assumed to be connected to ground via a human finger or its port. For a detector capacitor that is not quite close to a finger-to-pin port, its capacitance is assumed to be zero. A specific amount of parasitic capacitance will refer to the board of the detector capacitor as shown by the capacitor STRAY. The minimum value of the detector capacitance will therefore be equal to the level combination of parasitic or stray capacitance and the gate-source capacitance Cgs, if the finger capacitance is non-significant. COLL 2 assumes an array with a sensor pitch of 50 microns by 50 microns (approximately a 35x35 um capacitor plate) with a maximum finger capacitance of 40 fF, and an overall parasitic capacitance of approximately 6.8 fF. For a switching transistor with a 4 um width, the gate-source capacitance is 2 fF. It will learn that for these capacitance values, when there is no finger capacitance value, only about one-third of the pulse voltage is supplied to the gate of the selected transistor and will be coupled to an array finger capacitor plate via the capacitor Cgs. Consider, for example, supplying a 15 volt gate pulse to a selected transistor and pre-charging the array finger to 3 volts. When the selected transistor is turned off, approximately negative 5 volts are coupled to the fingerboard. The result is a negative 2 volt precharge. Generally this coupling will have only a small effect because the lost precharge voltage will be stored when the selected transistor is a positive pulse to read the capacitance charge value. In any case, if the negative coupling is of a magnitude such that the resulting gate-to-source voltage of the transistor is greater than the threshold or start-up voltage of the transistor, then the transistor will not turn off. The result is that the part of the array finger that is continuously charged or discharged will give the capacitance value that it will detect. If the row potential is maintained at a positive precharge potential of 3 volts, then the fingerboard capacitor will be charged in the positive direction until the gate source potential of the selected transistor is equal to or less than its threshold voltage. The charging effect of -8- This paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm) Members are kindly requested to indicate whether there are any changes to the amendments proposed on the day. Whether the substance is allowed to be amended A7 B7 V. Description of the invention (6 An example will be shown in Figure 3 (the voltage is not drawn into the grid). In Fig. 3, at period T1, the selected transistor is pulsed and the array finger capacitance is precharged to 3 volts. At time T1, the selected transistor is temporarily turned off by the negative pulse of the gate pulse from 15 to 0 volts. As a result of the transient, a 4.5 volt negative voltage is coupled to the array board. The terminal voltage of the array board will be reduced from 3 volts to 4.5 volts or minus 1.5 volts. Because the transistor gate voltage is now zero volts, it has a positive 1.5-volt gate-source voltage. Assuming a one-volt transistor threshold, the transistor will keep conducting forward during period T12. The array board capacitor will charge positively until the capacitor voltage reaches negative 1 volt at which point the transistor will stop conducting. At time T2, a positive pulse is supplied to the gate of the selected transistor to read the charge of the array capacitor. The positive transient of the start pulse will couple a positive 4.5 volt voltage to the array capacitor, raising its potential to · 1 volt plus 4.5 volts or positive 3.5 volts. This is greater than the precharge value of 0.5 volts, or 0.5 volt error. This conversion translates into a desired 0.5xCstray detection charge miss, which tends to lead to a minimum capacitance value to appear larger than it should, and reduces the dynamic range of the system. When the selected transistor is properly closed when the gate pulse is removed, the minimum charge on the array capacitor is equal to VpCstray, where Vp is the precharge charge. Coupling the negative transient of the gate pulse to the array capacitor, the minimum charge is actually (VP + AV) Cstiray, where AV is the error voltage caused by the capacitor overcharge in period T12. The dynamic range of the system is the Qmax / Qmin ratio, which corresponds to VpCmax / (Vp + AV) Cstray = Cmax / (l + AV / Vp) Cstray. The inventors understand that if ΔV / Vp is negative, the denominator will become smaller and the effective dynamic range will be enhanced. This can be done by pre-charging the array capacitor to a negative rather than a positive pre-charging voltage -9 _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

V: Γ ^ Please ask members to indicate clearly. Afternoon: whether the revision of the IL mentioned in e Q has been changed in substance and whether the content is allowed to be amended. To complete, and then change the voltage level of the gate pulse. For example, changing the pre-charge voltage to minus 3 volts requires the open-pole pulse voltage level to be changed from minus 6 volts to plus 9 volts by the system drive parameters to remain equal. The turn-off transient is still coupled with negative 4.5 volts on the array $ valley 'and the result is that the gate-source voltage will be positive volts, excluding the transistor turning off. The capacitor will charge i (K5 volts until the transistor is turned off. The effective dynamic range is Cmax / (1_AV / Vp) Cs. The value of (l-AV / Vp) is a function of the parasitic parameter and the value applied. The parasitic parameter cannot be Accurate evaluation because of unpredictable manufacturing procedures. In order to adjust these parameter variables, one of these voltage values may be adjusted to produce the desired i (1_AV / Vp) value. The pre-charge value vp * —can be adjusted to control ( 1_Δν / νρ) value. However, the signal-to-noise ratio may determine the amount and this parameter is reduced. The signal size is directly proportional to VP, because Qmax is equal to VpCmax. Cmax is tens of fF ', so vp should be sufficient You can get a good signal-to-noise ratio. The other adjustment change is the gate pulse size. This value can be adjusted to cause more or less Δν to be coupled to the array capacitor plate. The only limitation of this voltage is the collapse-feedback limit. Third, in order to ensure proper coupling to the array capacitor board, the gate-source overlapping capacitor may tend to increase during manufacturing. Figure 4 shows a port of a TFT scan capacitor array including a sense amplifier coupled to the row of buses. Each row will be lightly coupled to a separate sense amplifier, but the row may be multiplied by a smaller number of sense amplifiers. In Figure 4, the row bus is selected to be coupled to a variable voltage source and precharged. Via the switch S1, and selected to be coupled to a charge-sensing amplifier. The charge-sensing amplifier is an operational amplifier or Op-Amp and a feedback capacitor-10- ^ Paper size applies to China National Standard (CNS) A4 specification (210X297) )) &Quot; _

Revise i sound to A7 B7 V. Description of invention (8

Cintegrate is connected to a switch S3 across the feedback capacitor and resets the capacitor before sensing the charge on the existing capacitor. The Op-Amp is a high-gain device, so that the charge integration method in practice is essentially zero-input impedance. Therefore, all capacitors related to the bus of the bank are inconclusive and will not affect the sensitivity of the detection function. During pre-charging, switch S1 is off and switch S2 is on. When pre-charging, the selected transistor can be activated on one row at a time, or it can be activated simultaneously. The entire array can be scanned sequentially at the pre-cycle and then the entire array can be scanned sequentially for reads. Alternatively, the individual column capacitors may be precharged first and then sensed. When the signal is read, the switch S1 is on and the switch S2 is off. That is, switches U and S3 act interactively, such as when switch S2 is closed, switch 83 is on and vice versa, and so on. The switch S3 is turned off to reset the integrated capacitor between the sensing charge packages. The switch S3 is turned on when a scanning TFT is conducted, for example, during a scanning period. The switch S2 can be adjusted to be on or off when sensing the pre-charging and sensing modes. Alternatively, S2 can be maintained as a sequential scan that is closed across the array. The gate drive is coupled to the column selection electrode including a series of variable DC source 42 and a variable amplitude pulse generator 40. The device is shown as a unique circuit element to ^ Shows individual functions, regardless of their possible arrangement as a single pulse supply. It is displayed in this way to indicate the potential source of the two pulse swings and their absolute amplitude values for range control. For example, if the dynamic range of the system is adjusted by changing the precharge = voltage vp, it may be necessary to adjust the DC level of the gate pulse without changing the pulse voltage swing. Remember that the amount of charge that exceeds the capacitance is-gate_source

Binding

Line 11-

A7 B7 V. Description of the invention (.) As a function of the Ό position, most of the negative values of the pulse enter the gate-source potential equation. Therefore, changing only Vp can affect the amount of charge beyond the capacitor, and also change most negative DC values, or the closing voltage of the gate drive pulse. Alternatively, if the dynamic range is adjusted by changing the pulse size to adjust the value of A V, then a variable-size pulse generator is required. The dynamic range of the detection signal can be controlled by the gate drive pulse amplitude, the negative value of most gate drive pulses, and the value of the precharge voltage. It is better to understand the signal processing technology, and the contrast of the display image generated by the capacitance sensing can also be adjusted by the same variables as described above. Regardless of the type of scanning transistor used to scan a matrix such as this example capacitive sensing array, it is related to the stray capacitance of each capacitive sensing array. In order to scan a capacitor that would close without charging the ultracapacitor, it may be beneficial to physically guide the excess charge to delete the charge accumulated on the stray capacitance as in the present invention. This may be done by exceeding the required amplitude of the scan pulse, or by a larger transistor overlapping capacitor such as Cgs design, and then biasing the system appropriately to remove the charge on the stray capacitance. In the scope of the following patent application, the "polarity" item should be referred to as a transient state if it is positive if the transient state swings from a relatively negative value to a relatively positive value (more positive to more negative). Members are requested to indicate the amendments mentioned Whether there is any change in the content of the paper is allowed to repair the price 〇 This paper size applies the Chinese National Standard (CNS) Α4 specification (210X 297 mm)

Claims (1)

D8 VI. Application Patent Scope 1. A method for scanning an array capacitor with related TFT arrays connected to respective capacitors, wherein the capacitor array is sequentially precharged to a precharge voltage, the method includes: providing a scan pulse to The TFT element is used to adjust the TFT element to be conducted between a row of buses and the capacitor, and the scan pulse has a polarity off transient to tend to adjust the TFT element to leave conduction after the capacitor is precharged; to provide a coupling The DC pre-charge source of the busbars has the same polarity as the transient state. 2. The method according to item 2 of the patent scope, wherein the array is a capacitive sensor array and the method is operated to sense the charge on the respective array capacitors, and the method further comprises variably adjusting the scan pulses. Size to adjust the dynamic range of the sensed charge. w 3. The method according to item 1 of the patent application range, wherein the array is a capacitive sensor array which is operated by sensing the charge on the respective array capacitors. 1 The method further comprises variably adjusting the precharge voltage DC value to adjust the dynamic range of the sensed charge. 4. The method according to item 3 of the patent application range, wherein the array is a capacitive sensor which is operated by sensing the charge on the respective array capacitors, and the method also variably adjusts the sweeping DC The size is measured by the dynamic range of the charge. • 5. The method according to item 丨 of the patent application range, wherein the array is a capacitive sensor array and the method operates to sense a charge on each array capacitor, and the method further comprises adjusting the scan pulse One of the DC levels -13- ^, the scope of patent application, and the size of the scanning pulse to adjust the saturation of the image signal of the sensing capacitance value. 6. A capacitive thin film transistor array device, comprising: a variable capacitor array; an array of TFTfs scanned by a conductive path of a respective TFT connected between a row bus and a respective capacitor; a timing and pulse generator To provide a scanning pulse to each of the TFT's to adjust the TFT, for conduction, the pulse has a polarity transient to adjust the TFPs to leave conduction; a pre-charged voltage source has the same polarity as the transient; a charge sensing A switch for interactively connecting the pre-charged voltage source or the charge sensor to the row bus. 7. If the device in the scope of patent application No. 6 further includes a variable control circuit to adjust one of the DC value and the amplitude of the scan pulse. -14-This paper size applies to China National Standard (CNS) A4 (210X297 mm)