KR100767648B1 - Method of operating capacitive thin film transistor arrays - Google Patents

Abstract

The method of scanning a capacitor matrix employs an associated TFT device matrix connected to each capacitor, scanning the capacitor matrix to sequentially precharge each capacitor to a precharge voltage, and then sequentially detect the capacitor charge to determine each capacitor value. Scanning the capacitor matrix to determine. The TFT operates as a switch by connecting each capacitor to a column electrode and a sensing electrode alternately operating as a source of precharge potential. The precharge voltage is selected to have the same polarity as the turn off conversion point of the scanning pulse applied to the TFT. Selecting the precharge voltage to have the same polarity as the TFT turn off conversion point helps to improve the effective dynamic range of the detected charge.

Description

How a Capacitive Thin Film Transistor Array Works {METHOD OF OPERATING CAPACITIVE THIN FILM TRANSISTOR ARRAYS}

1 is a partial schematic diagram of a conventional scanning capacitor array.

FIG. 2 is a detailed schematic diagram of one cell of the array of FIG. 1. FIG.

3 is a waveform diagram showing the voltage along the array capacitor before and immediately after the turn-off transition of the TFT gate pulse occurs.

4 is a schematic diagram of a TFT scanning array incorporating the present invention;

The present invention relates to a method of operating a TFT array, and more particularly, to a method of operating a TFT used to scan a capacitive matrix array.

It is well known to use thin film transistor (TFT) arrays to address matrix elements. For example, one method of performing fingerprint detection is to arrange an electrode matrix that serves as the first plate of each capacitor. See for example FIG. 1. The ridges and valleys of the fingers taken near the array serve as the second plate of each capacitor. The capacitance value of the capacitor in the array can be converted into an electronic picture of a finger fingerprint taken near the array.

The electronic image can be formed by xy scanning the array and detecting its capacitance values in a known order. The capacitance value is determined indirectly by measuring the charge on the capacitor. The array is scanned twice in succession. During the first scanning, each capacitor is addressed by the TFT and precharged to a known voltage V _p . The charge on each capacitor is C _i V _p , where C _i is the capacitance of each array capacitor. During the second scanning, each array capacitor is discharged. In other words, charges are integrated to provide an output voltage value. The detected voltage value is directly related to the capacitance value.

Consider a process of forming a TFT on a substrate other than silicon, such as forming a scanning capacitor array. Such a process is not as accurate as a normal integrated circuit process. This inaccuracy can cause undesirable properties in the fabricated circuit. For example, if the gate electrode is first deposited on the underlying substrate and then the body of the TFT is formed on the gate electrode to form the TFT, as a result the transistor will normally have large gate-source and gate-drain redundancy capacitance which is undesirable . As a result, the device will normally have a large threshold voltage, which is undesirable, and will inevitably require a large excitation voltage.

Consider how these characteristics can affect the operation of a capacitor array fingerprint detector. The dynamic range of the capacitor array fingerprint detector is given as the ratio of the maximum capacitance value to the minimum capacitance value that can be detected, or more precisely as the ratio of the maximum charge to the minimum charge that can be detected. Assume that the maximum capacitance is related to the electrode near the ridge and corresponds to the charge of Qmax and the minimum capacitance corresponds to the charge of Qmin. Therefore, the expected dynamic range is Qmax / Qmin. The minimum capacitance value of the array relates to the electrode that is not in proximity to any part of the finger. Its value is only determined by the floating capacitance and is probably expected to be very small and constant.

For economic reasons, the TFTs on the array can be formed by amorphous silicon technology. The operating characteristics of these transistors require that relatively large scanning pulses be applied to the gates of these transistors. The large gate pulse voltage will be coupled at least in part to each source and drain electrode. Thus, when a particular TFT is gated off, some charge will be coupled leaving the associated array capacitor. During the next scanning, when the TFT is gated on for sensing, perhaps the same amount of charge will be coupled back to the array capacitor. The inventor finds that this estimation is incorrect and proposes the present invention.

Array capacitors with large capacitance values will have significantly greater capacitance than the gate-drain or gate-source redundant capacitance of the TFT. As such, any charge coupled to the array capacitor during gate turn off will not significantly change the electrode (capacitor) voltage. In this case, as expected, the transistor will be turned off when an off gate potential is applied.

On the other hand, an array capacitor having a relatively small capacitance value will have a capacitance value that is only slightly larger than the gate-drain or gate-source redundant capacitance value of the TFT, or a capacitance value of approximately that size. In this case, a significant turnoff gate voltage can be coupled to the array capacitor electrode. The gate-capacitor voltage may exceed the turn-on value (ie, the threshold value) of the TFT to prevent the TFT from being turned off immediately to insulate the capacitor electrode. The capacitor will eventually charge up to the point where the TFT is turned off. As a result, additional charge ΔQ will be generated in the capacitor regardless of the capacitance associated with the fingerprint. This has the effect of reducing the dynamic range of the sensing system. The expected system dynamic range of Qmax / Qmin is Qmax / (Qmin + ΔQ).

The inventors clearly understand that the capacitor charging that occurs after the turnoff pulse transition can be used more effectively to improve the apparent dynamic range. At the aforementioned dynamic range ratio, if the charges Qmin and ΔQ are opposite polarities, the charge ΔQ will remove some of the Qmin charges, effectively increasing the apparent dynamic range as the denominator goes to zero. The invention will become more apparent in the drawings and construction of the invention.

Although the present invention will be described in a capacitive array fingerprint detector environment, it will provide even more widespread use. Typically, the present invention will be useful in any scanning array in which a relatively large scanning pulse is used and the scanning TFT is connected to a high impedance element containing some capacitance.

1 shows a portion of a scanning capacitor array. In this case, the capacitor array contains only one plate for each capacitor. The capacitor array is arranged for xy scanning and element scanning or addressing and is performed by a TFT connected to each capacitor plate. The gate or control electrodes of all the TFTs in the row are connected to the common low gate drive electrode, and the drain electrodes of all the TFTs in the column are connected to the common column bus. Row and column decoders near circuitry (not shown) will strobe or address each row and column bus in succession. Typically, in this type of array, a pulse will be applied as a gate drive to one of the row buses to turn on all the TFTs in the row, and the column bus will be scanned continuously in the signal detection circuit.

2 shows one cell of the array in more detail. In FIG. 2, intrinsic and parasitic capacitive elements connected to the TFTs are included. The capacitor Cgd exists between the gate electrode and the drain electrode of the TFT, and the capacitor Cgs exists between the gate electrode and the source electrode. In general, the capacitance values of these capacitors are made as technically as small as possible. In normal integrated circuit fabrication, the value of these capacitors is very small by using self aligned gate technology. However, since the self-aligned gate fabrication technique is not available for any type of TFT fabrication, the Cgs and Cgd capacitance values can be relatively large.                     

The detector capacitor includes an array plate made of a solid line and an imaginary second plate. The second flat plate is assumed to be connected to the ground potential by, for example, a finger of a human body or a part thereof. For detector capacitors that are not very close to the part of the finger, the capacitance is assumed to be zero.

A certain amount of parasitic capacitance will inherently be connected to the plate of the detector capacitor, as indicated by capacitor STRAY. The minimum value of the detector capacitance will be equal to the parallel combination of parasitic or stray capacitance and gate-source capacitance Cgs. In other words, finger capacitors are meaningless.

Assuming an array with a sensor pitch of 50 microns x 50 microns (approximately 35 x 35 um capacitor plates), the maximum finger capacitance is calculated to be about 40 fF, and the total stray capacitance is about 6.8 fF. For a switching transistor with a channel width of 4 um, the gate-source capacitance is approximately 2 fF. For these capacitance values, in the absence of finger capacitance, a pulse voltage of approximately 1/3 applied to the gate of the select transistor will be coupled to the array finger capacitor plate by capacitor Cgs. For example, assume that a 15 V gate pulse was applied to the select transistor and the array finger plate was precharged to +3 V. When the select transistor is turned off, approximately -5 V is coupled to the finger plate resulting in a precharge value of -2 V. Usually such coupling is rarely a problem because when the select transistor is pulsed positively to read the capacitance charge value, the lost precharge voltage is restored. However, if the magnitude of the bond is negative such that the select transistor gate-source voltage is greater than the threshold or turn-on voltage of the transistor, the transistor does not turn off as expected. As a result, the array finger plate will be charged or discharged somewhat and will incorrectly detect the capacitor value. If the column potential maintains a precharge potential of +3 V, the finger plate capacitor will charge in the positive direction until the gate-source potential of the select transistor becomes less than or equal to its threshold voltage. An example of such a charging effect is shown in FIG. 3 (voltage is not drawn to scale at a constant rate).

In Figure 3, during the interval T | 1, the select transistor is pulsed on and the array finger plate capacitor is precharged to 3V. At T1, the select transistor is switched off by transitioning the gate pulse voltage in the negative direction from 15V to 0V. As a result of such a transition, a negative voltage of 4.5 V is coupled onto the array plate. The terminal voltage on the array plate will be 3 V-4.5 V, or -1.5 V. Since the transistor gate voltage is currently 0V, the gate-source voltage is + 1.5V. During the interval T | 2, assuming that the transistor has a threshold of 1 V, the transistor will maintain forward conduction. The array plate capacitance will be positively charged until the capacitor voltage reaches the -1 V point where the transistor stops conducting.

At T2, a positive pulse is applied to the gate of the select transistor to read the charge on the array capacitor. As the turn-on pulse transitions in the positive direction, a positive voltage of 4.5 V will be coupled on the array capacitor, and the potential of the array plate will rise to -1 V + 4.5 V, ie +3.5 V. This is 0.5 V greater than the precharge value. That is, 0.5 V error. This is transformed into a detected charge error of 0.5 x Cstray, making the minimum capacitance value appear larger than that value, which tends to reduce the dynamic range of the system.

If the select transistor is turned off correctly when the gate pulse is removed, the minimum charge on the array capacitor will be equal to V _p Cstray, where V _p is the precharge voltage. By combining the positively transitioned gate pulses on the array capacitor, the minimum charge actually becomes (V _p + ΔV) Cstray, where ΔV is the error voltage caused by excessive charging of the capacitor during the interval T | 2.

The dynamic range of the system is given as the ratio of Qmax / Qmin and corresponds to V _p Cmax / (V _p + ΔV) Cstray = Cmax / (1 + ΔV / V _p ) Cstray. The inventors clearly understand that if the term ΔV / V _p is negative the denominator will be smaller and the effective dynamic range will be improved. This can be accomplished by precharging the array capacitor negatively rather than by a positive precharge voltage and appropriately changing the voltage level of the gate pulse. For example, a change of precharge voltage to -3 V should change the gate pulse voltage level from -6 V to +9 V to keep the system drive parameters the same. The turn off transition still couples -4.5 V onto the array capacitor, resulting in a gate-source voltage of +1.5 V, which will prevent the transistor from turning off. The capacitor will be charged to +1.5 V until the gate-source voltage reaches -7 V, ie until the transistor is turned off. The effective dynamic range is the current Cmax / - is _{(1 ΔV / V p) Cs} .

The value of the term (1-ΔV / V _p ) is a function of the parasitic parameters and the applied voltage. Parasitic parameters may not be converted to accurate measurements due to changes in the manufacturing process. To accommodate this change in the parameter, one of the voltage values can be adjusted to produce the desired value of (1-ΔV / V _p ). The precharge value V _p is one variable that can be adjusted to control the value of (1 −ΔV / V _p ). However, in considering the signal-to-noise ratio, the amount by which this parameter is reduced is limited. The magnitude of the signal is directly proportional to V _p because Q max is equal to V _{p C} max. Cmax is approximately 10 fF, so V _p should be as large as possible to obtain good signal-to-noise ratio characteristics.

Another variable that can be adjusted is the gate pulse amplitude. This value can be adjusted by coupling some ΔV on the array capacitor plate. The only constraint on this voltage is the breakdown constraint. Third, gate-source redundant capacitors can be deliberately increased during the manufacturing process to ensure proper coupling on the array capacitor plate.

4 shows a portion of a TFT scanning capacitor array including a sense amplifier coupled to one column bus. Each column bus is preferably coupled to a separate sense amplifier, but the column bus may be multiplexed to fewer sense amplifiers.

In Fig. 4, the column bus is selectively coupled to a variable voltage source, i.e., precharge, by switch S1, and also to the charge sense amplifier. The charge sense amplifier is an op amp, or op amp, connected to a feedback capacitor C _integrate . Switch S3 is connected in parallel with the feedback capacitor and resets the capacitor before sensing the charge on a given array capacitor. Because Op-Amp is a high gain device, when operating in a known charge integration scheme, it exhibits substantially zero input impedance. Therefore, any capacitance connected to the column bus is not a problem at all and cannot affect the sensitivity of the detection function.

During precharging, switch S1 is closed and switch S2 is open. During precharging, the select transistors can be turned on simultaneously in a row or all on at the same time. The entire array can be scanned sequentially during the precharge cycle, after which the entire array can be read sequentially. Alternatively, the capacitors in each column may be sensed after being precharged.

During signal reading, switch S1 is open and switch S2 is closed. Normally switches S2 and S3 work alternatively. That is, switch S3 is opened when switch S2 is closed, and switch S3 is closed when switch S2 is opened. The switch S3 is closed to reset the integral capacitor between the times of detecting each charge packet. The switch S3 is opened when the scanning TFT is inverted, that is, during the sensing interval.

The switch S2 can be adjusted to open and close between the times of sensing each heat in either the precharging mode or the sensing mode. Alternatively, switch S2 can remain closed during sequential scanning of the entire array.

The gate drive coupled to the row select electrode includes a series connection of a variable DC voltage source 42 and a variable amplitude pulse generator 40. The device may be arranged as a single integrated pulse supply, but is shown as a distinct circuit element to indicate each function. They are shown in this way to indicate that both the pulse swing and its absolute amplitude value are possible causes of range control. For example, if the system dynamic range can be adjusted by a change in the precharge voltage V _p , it may be necessary to adjust the DC level of the gate pulse without changing the pulse voltage swing. Remember that the excess capacitor charge is a function of the gate-source potential, and the maximum negative value of the pulse is a component of the gate-source potential equation. Therefore, just as the change in V _p can affect the amount of excess capacitor charge, so does the change in the maximum negative DC value of the gate drive pulse, ie the off-voltage. Alternatively, if the dynamic range can be adjusted by a change in pulse amplitude, then an adjustment of the ΔV value rather than a variable amplitude pulse generator is required. The dynamic range of the detection signal can be controlled by the gate drive pulse amplitude, the maximum negative value of the gate drive pulse and the precharge voltage value.

One skilled in the art of signal processing will appreciate that the contrast of the display image generated from the capacitance sensor can be adjusted by such variables as described above.

Regardless of the type of scanning transistor used to scan the matrix, such as an example capacitance sensing array, there will be stray capacitance connected to each array capacitor plate. For a scanning transistor that is turned off without excess capacitor charge, it may be beneficial to delete the charge accumulated on the floating capacitance by such excess charge, as seen by the present invention. This can easily be solved by biasing the system appropriately to eliminate the charge remaining on the floating capacitance, by designing a transistor redundant capacitance, such as Cgs, which intentionally exceeds the amplitude normally required or by scanning transistors.

In the following claims, "polarity" when a conversion point is mentioned is positive if the conversion point swings from a relatively negative value to a relatively positive value.

Claims (7)

A method of scanning a capacitor matrix having an associated matrix of TFT elements connected to each capacitor and sequentially precharged with a precharge voltage, After the capacitor is precharged, a scanning pulse having a turn-off transition point of polarity for adjusting to stop the conduction of the TFT element is provided to the gate of the corresponding TFT element so that the TFT element is between the column bus and the capacitor. Adjusting it to fall, Providing a DC precharge voltage source coupled to the column bus and having the same polarity as the conversion point. The method of claim 1, wherein the array is a capacitance sensor array that senses charge on each matrix capacitor, And variably adjusting the amplitude of the scanning pulse to adjust the dynamic range of sense charge. The method of claim 1, wherein the array is a capacitance sensor array that senses charge on each matrix capacitor, And variably adjusting the DC value of the precharge voltage to adjust a dynamic range of sense charge. The method of claim 3, wherein the array is a capacitance sensor that senses charge on each matrix capacitor, And variably adjusting the DC amplitude of the scanning pulse to adjust the dynamic range of sense charge. The method of claim 1, wherein the array is a capacitance sensor array that senses charge on each matrix capacitor, And adjusting the saturation of the image signal indicative of the sensed capacitor value by adjusting one of the DC level of the scanning pulse and the amplitude of the scanning pulse. A variable capacitance matrix, A scanning TFT matrix having respective TFT conducting paths connected between a column bus and each of the capacitances; A timing and pulse generator for applying a scanning pulse having a switching point of polarity for controlling the TFT not to be conducted to each TFT to adjust the conduction state of the TFT; A precharge voltage source having the same polarity as the conversion point; With charge sensors, And a switch for alternatively connecting said precharge voltage source or said charge sensor to said column bus. 7. The capacitor matrix scanning device of claim 6, further comprising a variable control circuit for adjusting one of a DC value and an amplitude value of the scanning pulse.

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