JP4531219B2 - Method of operating capacitive thin film transistor array - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of operating a thin film transistor array, and more particularly to a method of operating a thin film transistor used to scan a capacitive matrix array.
[0002]
[Prior art]
It is known to use thin film transistor (TFT) arrays to address matrix elements. For example, in one method for performing fingerprint detection, a matrix of electrodes is placed that acts as one plate of each capacitor. See, for example, FIG. The ridges and troughs of the fingers placed in close proximity to the array act as second plates for the respective capacitors. Capacitance values of capacitors included in the array can be converted into an electronic image of a fingerprint of a finger placed in the vicinity of the array.
[0003]
An electronic image can be formed by xy scanning the array and detecting capacitance values in a known order. The capacitance value is indirectly determined by measuring the charge on the capacitor. The array is scanned twice in sequence. During the first scan, each capacitor is addressed by the TFT and precharged to a known value V _p . The charge applied to each capacitor is C _i V _p , where C _i is the capacitance of each array capacitor. During the second scan, each array capacitor is discharged. That is, the charge is removed and stored to provide an output voltage value. The detected voltage value is directly related to the capacitance value.
[0004]
Here, for example, a method of forming TFTs on a substrate other than silicon in order to form a scanned capacitor array will be considered. This method is not as accurate as normal integrated circuit processing. Inaccuracies can give undesirable characteristics to the manufactured circuit. For example, if a TFT is formed by first depositing a gate electrode on the underlying substrate and then forming the TFT body on the gate electrode, the resulting transistor is usually too large and desirable Has no gate-source and gate-drain overlap capacitance. Second, the resulting device is usually too large and has an undesirable voltage, requiring a larger activation voltage, etc.
[0005]
Now consider how the above features can affect the operation of the capacitor array fingerprint detector. The dynamic range of a capacitor array fingerprint detector is given by the ratio of the maximum to minimum capacitance that can be detected, or more precisely, the ratio of the corresponding maximum to minimum charge that can be detected. Assume that the maximum capacitance is associated with the electrode near the ridge and corresponds to a charge of Qmax and the minimum capacitance corresponds to a charge of Qmin. Therefore, the expected dynamic range is Qmax / Qmin. The minimum capacitance value in the array is associated with an electrode that is not near any part of the finger. Its value is determined only by stray capacitance and is expected to be very small and constant.
[0006]
[Problems to be solved by the invention]
For economic reasons, the TFTs on the array can be formed with amorphous silicon technology. The operational characteristics of these transistors require that a relatively large scan pulse be applied to the gates of these transistors. A large gate pulse voltage is applied at least partially to the respective source and drain electrodes. Thus, when a particular TFT is gated off, some charge is decoupled from the associated array capacitor. During the next scan, when the TFT is gated on for sensing operation, an equal amount of charge will be applied back to the array capacitor. The inventor of the present application has found that this assumption is not correct, thereby leading to the present invention.
[0007]
[Means for Solving the Problems]
An array capacitor having a relatively large capacitance value has a capacitance that is significantly greater than the overlapping capacitance of the gate-drain or gate-source of the TFT. Thus, all charges applied during gate turn-off do not significantly change the voltage on the electrode (capacitor). In this case, as expected, the transistor is turned off when an off-gate potential is applied.
[0008]
An array capacitor having a relatively small capacitance value may have a capacitance value on the same order as or slightly larger than the overlapping capacitance value of the gate-drain or gate-source of the TFT. In this case, a significant turn-off gate voltage can be applied to the array capacitor electrode. The gate capacitor voltage may exceed the TFT turn-on value (ie, threshold), thereby preventing the TFT from turning off immediately and disconnecting the capacitor electrode. The capacitor is gradually charged to the point where the TFT is turned off. This charging results in an additional charge ΔQ on the capacitor that is independent of the capacitance associated with the fingerprint. This has the effect of reducing the dynamic range of the sensing system. The expected system dynamic range Qmax / Qmin is actually Qmax / (Qmin + ΔQ).
[0009]
The inventors of the present application have recognized that capacitor charging that occurs after a turn-off pulse transition can be advantageously used to increase the apparent dynamic range. With the above dynamic range ratio, if the charges Qmin and ΔQ are of opposite polarity, the charge ΔQ cancels some of the Qmin charge and the denominator approaches zero, increasing the apparent dynamic range.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The invention will become more apparent with reference to the accompanying drawings. Although the present invention will be described in the context of a capacitive array fingerprint detector, it has a wider range of applications. Typically, the present invention is useful in any scanned array where relatively large scan pulses are used and the scanning TFT is coupled to a high impedance device that includes some capacitance.
[0011]
Referring to FIG. 1, a portion of a capacitor array that is scanned is illustrated. In this example, the capacitor array includes only one plate of each capacitor. The array is configured for xy scanning, device scanning, or addressing, and these scanning are performed by TFTs connected to each capacitor plate. The gate electrodes or control electrodes of all TFTs in a row are coupled to a common row gate drive electrode, and the drain electrodes of all TFTs in a column are connected to a common bus. Near the periphery of the circuit (not shown), the row and column decoders sequentially strobe or address their respective row and column buses. In general, in this type of arrangement, a pulse is applied as a gate drive to one of the row buses to turn on all the TFTs in the row, and the column bus is sequentially scanned by the signal detection circuit.
[0012]
FIG. 2 shows in more detail one cell of the array. In FIG. 2, intrinsic and parasitic capacitive elements associated with the TFT are included. A capacitor Cgd exists between the gate and drain electrodes of the TFT, and a capacitor Cgs exists between the gate and source electrodes. In general, the capacitance values of these capacitors are minimized as technically possible. In normal integrated circuit manufacturing, the value of these capacitors is very small due to the self-aligned gate technology. Unfortunately, self-aligned gate fabrication techniques cannot be used to fabricate certain types of TFTs and the resulting Cgs and Cgd capacitance values can be relatively large.
[0013]
The detector capacitor has an array plate indicated by a solid line and a second plate indicated by a phantom. The second electrode plate is assumed to be connected to the ground potential by, for example, a human finger or a part thereof. For detector capacitors that are not near the part of the finger, the capacitance is assumed to be zero.
[0014]
A certain amount of parasitic capacitance is inherently associated with the detector capacitor plate, as indicated by capacitor STRAY. The minimum value of the detector capacitance is therefore equal to the parallel combination of parasitic or stray capacitance and gate-source capacitance Cgs, i.e. the finger capacitor is not critical.
[0015]
Assuming an array with a sensor pitch of 50 microns × 50 microns (about 35 × 35 μm capacitor plate), the maximum finger capacitance is calculated to be about 40 fF and the total stray capacitance is about 6.8 fF. For a switching transistor having a channel width of 4 μm, the gate-source capacitance is on the order of 2 fF. At these capacitance values, in the absence of finger capacitance, approximately one third of the pulse voltage applied to the gate of the select transistor is coupled to the array finger capacitor plate by capacitor Cgs. For example, consider the case where a 15 volt gate pulse is applied to the select transistor and the array finger plate is precharged to positive 3 volts. When the select transistor is turned off, a negative voltage of approximately 5 volts is coupled to the finger plate, resulting in a negative precharge value of 2 volts. Usually, when the transistor selected to read the capacitance charge value is given a positive pulse, the lost precharge voltage is restored, so the effect of such coupling is small. However, if the magnitude of the negative coupling is such that the resulting select transistor gate-source voltage is greater than the threshold or transistor turn-on voltage, the transistor is not turned off as expected. As a result, a continuous charge or discharge of the array finger plate occurs, thereby producing a falsely detected capacitor value. If the column potential is maintained at a positive 3 volt precharge potential, the finger plate capacitor is charged in the positive direction until the gate-source potential of the select transistor is below its threshold. An example of this charging effect is shown in FIG. 3 (the voltage scale shown is not correct).
[0016]
In FIG. 3, at interval TI1, the select transistor is pulsed on and the array finger plate capacitor is precharged to 3 volts. At time T1, the select transistor is switched off by a negative transition to form a 15 to 0 volt gate pulse. As a result of the transition, a negative voltage of 4.5 volts is coupled to the array plate. Since the transistor gate voltage is now zero volts, there is a positive 1.5 gate-source voltage. Assuming a transistor threshold of 1 volt during interval TI2, the transistor remains positively conductive. The array plate capacitance is negatively charged until the capacitor voltage reaches a negative 1 volt and the transistor stops conducting.
[0017]
At time T2, a positive pulse is applied to the gate of the select transistor to read out the charge on the array capacitor. The positive transition of the turn-on pulse applies a positive voltage of 4.5 volts to the array capacitor and raises its potential to minus 1 volt plus 4.5 volts, ie positive 3.5 volts. This is 0.5 volts greater than the precharge value, or there is an error of 0.5 volts. This translates to a detected charge error of 0.5 × Cstray, which makes the minimum capacitance value appear larger than the actual value, thereby reducing the dynamic range of the system. In order for the select transistor to turn off correctly when the gate pulse is removed, the minimum charge on the array capacitor is equal to V _p Cs, where V _p is the precharge voltage. By applying a negative transition of the gate pulse to the array capacitor, the minimum charge is actually (V _p + ΔV) Csray, where ΔV is the error voltage caused by excessive charging of the capacitor over the interval TI2.
[0018]
Dynamic range of the system is given by the ratio Qmax / Qmin, which corresponds to _{V p Cmax / (V p +} ΔV) Cstray = Cmax / (1 + ΔV / V p) Cstray. The inventor of the present application has recognized that if the ΔV / V _p term is negative, the denominator is reduced and the effective dynamic range is increased. This can be achieved by precharging to a negative precharge voltage rather than positive and appropriately changing the voltage level of the gate pulse. For example, changing the precharge voltage to negative 3 volts requires a change in the gate pulse voltage level from negative 6 volts to positive 9 volts in order for the system drive parameters to remain equal. The turn-off transition also applies a negative 4.5 volts on the array capacitor, resulting in a positive gate-source voltage of 1.5 volts, preventing the transistor from being turned off. The capacitor charges positive 0.5 volts until the gate-source voltage reaches negative 7 volts, at which point the transistor is turned off. Effective dynamic range here is a Cmax / (1-ΔV / V p) Cs.
[0019]
The value of the term (1-ΔV / V _p ) is a function of the parasitic parameters and the applied voltage. Parasitic parameters may not lead to an accurate assessment due to unforeseen changes in the manufacturing process. In order to absorb variations in these parameters, some of the voltage values can be adjusted to produce the desired (1-ΔV / V _p ) value. The precharge value V _p is one variable that can be adjusted to control the value of (1−ΔV / V _p ). However, signal to noise ratio considerations determine the amount by which this parameter is reduced. Since Qmax is equal to V _p Cmax, the signal size is directly proportional to V _p . Cmax is on the order of several tens of fF, and V _p must be as large as possible to achieve a good signal-to-noise ratio.
[0020]
Another variable that is adjusted is the gate pulse amplitude. This value can be adjusted to apply some ΔV to the array capacitor plate. The only constraint on this voltage is a breakdown constraint. Third, the gate-source overlap capacitor can be intentionally increased during manufacture to ensure proper coupling to the array capacitor plate.
[0021]
FIG. 4 is a diagram illustrating a portion of a TFT-scanned capacitor array that includes a sense amplifier coupled to one of the column buses. Preferably each column is coupled to a separate sense amplifier, but the columns can be multiplexed into a smaller number of sense amplifiers.
[0022]
In FIG. 4, the column bus is selectively coupled to the variable voltage source Precharge by the switch S1 and is selectively coupled to the charge sense amplifier. The charge sense amplifier is an operational amplifier or operational amplifier connected to the feedback capacitor C _integrate . Switch S3 is connected across the feedback capacitor and resets the capacitor before sensing the charge on a given array capacitor. An operational amplifier is a high gain device that exhibits a substantially zero input impedance when it operates to store charge as is well known. Thus, any capacitance associated with the column bus is irrelevant and does not affect the sensitivity of the detection function.
[0023]
During precharging, the switch S1 is closed and the switch S2 is opened. During precharging, the select transistors are turned on line by line or simultaneously. During the precharge cycle, the entire array is scanned sequentially and then the entire array is sequentially scanned for reading. Alternatively, each row of capacitors is first precharged and then sensed.
[0024]
During signal readout, switch S1 is opened and switch S2 is closed. Normally, the switch values S2 and S3 operate alternately, that is, the switch S3 is opened when the switch S2 is closed, and conversely, the switch S3 is closed when the switch S2 is opened. Switch S3 is closed to reset the storage capacitor during detection of each charge packet. Switch S3 is open whenever the scanning TFT is conducting, i.e. during the sensing interval.
[0025]
Switch S2 is configured to open and close while sensing each row in both precharge and sense modes. Alternatively, S2 can remain closed while sequentially scanning the entire array.
[0026]
The gate drive coupled to the row select electrode includes a direct connection between the variable DC source 42 and the variable amplitude pulse generator 40. The device is illustrated as a separate circuit element that exhibits each function, but may be arranged as a single overall pulse supply. These are shown to show that the pulse swing and its absolute amplitude value are potential sources of range control. For example, the dynamic range of the system, if it is adjusted by changing the precharge voltage V _p, it is necessary to adjust the DC level of the gate pulse without changing the deflection of the pulse voltage. Since the amount of excess capacitor charge is a function of the gate-source voltage, the most negative value of the pulse falls into the gate-source potential equation. Accordingly, the most negative DC value or off voltage of the gate drive pulse is changed in the same manner as V _P affects the excessive capacitor charge amount. Alternatively, a variable amplitude pulse generator is required if the dynamic range must be changed to change the pulse amplitude in order to adjust the value of ΔV. The dynamic range of the detected signal can be controlled by the gate drive pulse amplitude, the most negative value of the gate drive pulse, and the value of the precharge voltage.
[0027]
Those skilled in the art of signal processing will recognize that the contrast of the displayed image generated from the capacitance sensor can be adjusted by the similar variables described above.
[0028]
Regardless of the type of transistor scanning used to scan the matrix, such as the exemplary capacitance sensing array, there is a stray capacitance associated with each array capacitor plate. In order to scan a transistor that is turned off without excessive capacitor charging, it is advantageous to actually induce such excessive charging to counteract the charge stored on the stray capacitance as taught by the present invention. This simply exceeds the amplitude normally required for a scan pulse, or designs a larger transistor overlap capacitance, eg Cgs, and properly biases the system to counteract the charge present on the stray capacitance. Can be achieved.
[0029]
In the claims, when the term “polarity” is used with respect to a transition, it is positive when the transition swings from a relatively negative value to a relatively positive value, and relative to a relatively positive value. Is negative when the value swings to a negative value.
[Brief description of the drawings]
FIG. 1 is a partial schematic diagram showing a prior art scanned capacitor array.
2 is a schematic diagram showing one cell of the array of FIG. 1 in more detail.
FIG. 3 is a waveform diagram showing a voltage associated with an array capacitor immediately before and immediately after the occurrence of a TFT gate pulse turn-off transition.
FIG. 4 is a schematic diagram illustrating a TFT scanned array embodying the present invention.
[Explanation of symbols]
40 variable amplitude pulse generator 42 variable direct current source S1 to S3 switch

Claims (7)

A method of scanning a matrix of capacitors sequentially precharged to a precharge voltage by a matrix of associated thin film transistor devices connected to each capacitor,
Applying a scan pulse to a gate associated with the thin film transistor device to regulate conduction of the thin film transistor device between a column bus and the capacitor, the scan pulse after the capacitor is precharged Having a negative polarity turn-off transition that causes the thin film transistor device to become non-conductive;
Supplying a DC precharge voltage to the column bus having the same negative polarity as the transition;
A method characterized by comprising: The array is a capacitance sensor array;
The method operates to sense the charge on each matrix capacitor;
The method further includes variably adjusting the amplitude of the scan pulse to adjust the dynamic range of the sensed charge.
The method of claim 1 wherein: The array is a capacitance sensor array that operates by sensing the charge on each matrix capacitor;
The method further includes variably adjusting the DC value of the precharge voltage to adjust the dynamic range of the sensed charge.
The method of claim 1 wherein: The array is a capacitance sensor array that operates by sensing the charge on each matrix capacitor;
The method further includes the step of variably adjusting the DC amplitude of the scan pulse to adjust the dynamic range of the sensed charge.
The method of claim 3 wherein: The array is a capacitance sensor array;
The method operates to sense the charge on each matrix capacitor;
The method further includes adjusting the saturation of the image signal representing the sensed capacitor value by adjusting one of the DC level of the scan pulse and the amplitude of the scan pulse.
The method of claim 1 wherein: A matrix of variable capacitance;
A matrix of scanning thin film transistors having respective thin film transistor conduction paths connected between a column bus and the respective capacitances;
A timing and pulse generator for applying a scan pulse to each of the thin film transistors to adjust the thin film transistor to be conductive, the scan pulse having a negative polarity transition that causes the thin film transistor to become non-conductive; and ,
A precharge voltage source having the same negative polarity as the transition;
A charge sensor;
A switch for selectively connecting the precharge voltage source or the charge sensor to the column bus;
A device characterized by comprising:   7. The apparatus of claim 6, further comprising a variable control circuit for adjusting one of a DC value and an amplitude value of the scan pulse.

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