EP0647894A2

EP0647894A2 - A circuit for providing a sink for majority charge carriers

Info

Publication number: EP0647894A2
Application number: EP19940202907
Authority: EP
Inventors: Neil Christopher Bird
Original assignee: Philips Electronics UK Ltd; Koninklijke Philips Electronics NV; Philips Electronics NV
Current assignee: Philips Electronics UK Ltd; Koninklijke Philips NV
Priority date: 1993-10-12
Filing date: 1994-10-07
Publication date: 1995-04-12
Also published as: GB9320991D0; JPH07234737A

Abstract

The first electrodes (d1 and d2) of first and second transistors (Q1 and Q2) of the same polarity are coupled to one (1) of first and second voltage supply lines (1 and 2). The second electrode (s1) of the first transistor (Q1) is coupled to the other (2) of the first and second voltage supply lines (1 and 2) by a reference current source (3) for supplying a reference current (I_r) through the first transistor (Q1) and the second electrode (s2) of the second transistor (Q2) is arranged to be coupled to the other (2) of the first and second voltage supply lines (1 and 2) by a load (RL) such that in operation of the circuit majority charge carriers flow through the first and second transistors (Q1 and Q2) in a direction away from the other (2) of the first and second voltage supply lines (1 and 2). The second transistor (Q2) has dimensions which are in a predetermined ratio with corresponding dimensions of the first transistor (Q1). An amplifying arrangement (4) has a negative input (4b) coupled to the second main electrode (s1) of the first transistor (Q1), a positive input (4a) coupled to the second main electrode (s2) of the second transistor (Q2) and an output (4c) coupled to the control electrodes (g1 and g2) of the first and second transistors (Q1 and Q2) for providing a negative feedback for causing, in use of the circuit, voltages at the positive and negative inputs (4a and 4b) of the amplifying arrangement (4) to be equal thereby causing the second transistor (Q2) to supply to the load (RL) coupled between the second main electrode (s2) of the second transistor (Q2) and the other voltage supply line (2) a current (I_o) related to the reference current (I_r) in accordance with the predetermined ratio. This circuit enables a constant output current (I_o) to be provided with a very high output impedance.

Description

This invention relates to a circuit for providing a sink for majority charge carriers, that is a source where the majority charge carriers are electrons and a current sink where the majority charge carriers are holes.
In the area of integrated circuit technology constant (that is high output impedance) current sources and sinks are important circuit elements. Generally current sinks can be realised relatively easily using an n type device such as a single n channel enhancement mode MOS transistor or cascoded n channel MOS transistors, while current sources can similarly be realised using p type devices such as p channel enhancement mode MOS transistors. However, there are some forms of integrated circuits where it is technologically difficult to provide both n channel and p channel enhancement mode MOS transistors so making it difficult to form current sources where only n channel devices are available and making it difficult to form current sinks where only p channel devices are available. This is the case, for example, in circuits formed by deposition of amorphous or polycrystalline semiconductor materials onto insulating substrates such as glass or plastics because the p channel enhancement mode thin film transistors (TFTs) that can currently be manufactured have unacceptably high threshold voltages in addition to very poor carrier mobility characteristics. Similarly in the area of smart power or power integrated circuit technology where a vertical power device is integrated with control or logic circuitry, the constraints of having to integrate the control or logic circuitry into the same substrate or semiconductor body as the power semiconductor device may make it extremely difficult to form usable p type devices, for example p channel enhancement mode MOS transistors, where the vertical power device is an npn bipolar transistor or n channel power MOSFET or to form usable n type devices, for example n channel enhancement mode MOS transistors, where the power device is a pnp bipolar transistor or a p channel vertical power MOSFET, without resorting to complicated processing technology.
Currently n channel TFT digital circuits requiring a current source or load transistor for, for example, use in a logic gate or shift register generally use a circuit of the form shown in Figure 1. As can be seen from Figure 1, the circuit comprises an n channel TFT N1 having its drain electrode coupled to a first voltage supply line 1, its gate electrode coupled to a gate voltage supply line G and its source electrode coupled to a second voltage supply line 2 via the device RL for which the current is to be supplied. The device RL shown in Figure 1 may be any suitable component of a circuit to which current is to be supplied. Thus, for example, the device RL may as shown be a further n channel enhancement mode TFT having its main current path, that is that between its source and drain electrodes, coupled in series with the source electrode of the TFT N1 and its control electrode coupled at the input I to an input voltage so that the two TFTs form an inverter circuit with the inverted voltage being provided at the output O.
Such an arrangement is not however suitable where a constant current source is required because any change in the output voltage V_o at the output O at the junction between the source electrode of the TFT N1 and the device RL modulates the gate-source voltage of the TFT N1 because the gate voltage is of course held at the constant potential applied to the gate voltage supply line G. If the transconductance of the TFT N1 is gm and the current through the device RL is i_o then the output impedance is given by:

and may typically be of the order of 10⁵ to 10⁶ ohms. In addition, the output impedance R_out depends upon the output voltage V_o (that is the source voltage of the TFT N1) because the transconductance is a function of the drain current. Moreover, the dependence of the output current i_o on the output voltage V_o means that the circuit cannot be used to provide a precise current source. In addition the gain of such an arrangement is given by:

where W and L are the width and length respectively of the conduction channel so that, for high gain, either TFT N1 has to be very small or TFT RL has to be very large which may present capacitance problems and, of course, means that the circuit will occupy a large area.
It is an aim of the present invention to provide a circuit for providing a sink for majority charge carriers which may be implemented in circumstances where there are constraints on the use of complementary, for example CMOS, technology.
According to one aspect of the present invention, there is provided a circuit for providing a sink for majority charge carriers, the circuit comprising first and second voltage supply lines, first and second transistors of the same polarity each having a control electrode and first and second main electrodes and the second transistor having dimensions which are in a predetermined ratio with corresponding dimensions of the first transistor, the first electrodes of the first and second transistors being coupled to one of the first and second voltage supply lines, the second electrode of the first transistor being coupled to the other of the first and second voltage supply lines by a reference current source for supplying a reference current through the first transistor and the second electrode of the second transistor being arranged to be coupled to the other of the first and second voltage supply lines by a load such that in operation of the circuit majority charge carriers flow through the first and second transistors in a direction away from the other of the first and second voltage supply lines, an amplifying means having positive and negative inputs and an output with the negative input coupled to the second main electrode of the first transistor, the positive input coupled to the second main electrode of the second transistor and the output coupled to the control electrodes of the first and second transistors for providing a negative feedback for causing, in use of the circuit, voltages at the positive and negative inputs of the amplifying means to be equal thereby causing the second transistor to supply to the load coupled between the second main electrode of the second transistor and the other voltage supply line a current related to the reference current in accordance with the predetermined ratio.
In use of a circuit in accordance with the invention, the negative feedback causes the output current to be related to the reference current in accordance with the predetermined ratio, that is the circuit acts like a current mirror, and in addition the output impedance is increased (relative to that of the known arrangements discussed above) by a factor determined by the gain of the amplifying means. Thus, the circuit provides a constant output current with a very high output impedance. Thus, the present invention provides a circuit which enables a sink for majority charge carriers to be formed without the need for complementary MOS or bipolar technology. For example the present invention enables a current source to be formed where only n channel enhancement mode MOS transistors are available. The first and second transistors are generally normally off devices that is devices such as bipolar transistors or enhancement mode MOS transistors which do not conduct until an appropriate voltage is applied to the control electrode of the device with appropriate voltages applied to the first and second main electrodes.
In a preferred example, the first and second transistors are n channel enhancement mode MOS transistors with the source electrode of the first n channel MOS transistor being coupled to the negative input of the amplifying means and the source electrode of the second n channel MOS transistor being coupled to the positive input of the amplifying means. In such a case, the present invention enables the formation of a current source using only n channel enhancement mode MOS transistors. Of course, it should be possible to utilise bipolar n type devices, that is npn bipolar transistors, in place of the n channel enhancement mode MOS transistors, if desired.
It should be understood that, as used herein, the term "n type" or "n type device" refers to a device such as an npn bipolar transistor or an n channel MOS transistor in which the majority charge carriers during conduction of the device are electrons while the term "p type" or "p type device" refers to a device such as a pnp bipolar transistor or p channel MOS transistor in which the majority charge carriers during conduction of the device are holes.
Although the first and second transistors may simply be similar to one another, preferably the first and second transistors are matched so that the output current is equal to the reference current. As used herein the term 'matched' means that the first and second transistors are manufactured using the same process to have the same dimensions and thus so far as possible the same operating characteristics so that for a given voltage they pass the same current whereas the term 'similar' means that the first and second transistors are manufactured using the same process to have dimensions in a predetermined ratio not equal to one so that the currents passed by the first and second transistors are in that predetermined ratio. In the case of MOS or TFT transistors the important dimensions are of course the channel length L and width W.
The amplifying means may comprise any suitable arrangement such as an inverting circuit comprising an input transistor arrangement coupled to the positive and negative inputs and a load device comprising a photosensitive element which is illuminated during operation of the inverting circuit.
For example, the amplifying means may comprise third, fourth and fifth transistors with each transistor having first and second main electrodes and a control electrode with the control electrode of the third transistor being coupled to the positive input, the control electrode of the fourth transistor being coupled to the negative input and the control electrode of the fifth transistor being coupled to a bias voltage supply, the third and fifth transistors being coupled in series between the first and second voltage supply lines and the fifth transistor also being coupled in series with the fourth or load transistor and the photosensitive element which is also coupled to the output of the amplifying means.
This provides an amplifying means with a high output impedance without having to use complementary transistors.
In one example, the photosensitive element may comprise a photosensitive non-linear resistive device coupled between the first main electrode of the fourth transistor and the first supply line. In such an arrangement, the photocurrent generated by the illumination of the photosensitive element can be independent of the reverse-bias voltage across the photosensitive device so that the amplifying means has a very high output impedance. The gain of the amplifying means is determined by the output impedance and may be in the order of 30.
In a second example, the photosensitive element may comprise at least one photosensitive device coupled between the second main electrode and the control electrode of a further transistor coupled in series with the fourth transistor for providing, when illuminated, a voltage between the second main and control electrodes of the further transistor. In this example, the gate-source voltage of the further transistor is not a function of the output voltage and so the amplifying means has an increased output impedance, giving a higher gain. In operation of such a circuit, illumination of the photosensitive element results in a small voltage across the photosensitive element which voltage is equal to the forward bias required to give a forward current equal in magnitude to the photocurrent.
Generally, but depending upon the characteristics of the photosensitive element, in this second example the photosensitive element will comprise a series of photosensitive devices to enable sufficient voltage to be provided to turn on the further transistor when the photosensitive element is illuminated. In this second example, the current flowing in the inverter circuit formed by the fourth transistor, the photosensitive element and the further transistor, that is the current which is available to charge the load capacitance, is not determined by the current flowing through the photosensitive element when the output voltage of the inverter circuit is rising. Accordingly, in the second example, larger capacitive loads can be driven at the same given slew rate by either increasing the channel width to length W/L ratio of the further transistor or by adding photosensitive devices to the series chain coupled between the control and first main electrode of the further or load transistor. It should not however be necessary to increase the size or area of the photosensitive devices because they are not required to produce an output current.
A circuit in accordance with the invention may be used in any situation where a constant current is required, for example in switched current circuits, and especially in those situations where other constraints make it difficult to provide complementary transistors, for example in smart or intelligent power devices or in thin film devices such as control circuitry for controlling access of the storage elements by means of row and column conductors of a two-dimensional array of storage elements arranged in rows and columns and individually accessible by the row and column conductors.
The present invention also provides an image sensor comprising at least one photosensitive element, a circuit in accordance with the first aspect, another transistor having first and second main electrodes and an insulated gate electrode, the said other transistor being coupled in series with the first transistor between the first and second voltage supply lines to provide the reference current source for the circuit, an additional transistor having first and second main electrodes and a control electrode, the additional transistor being coupled in series with the second transistor between the first and second voltage supply lines to provide the load for the circuit, an output provided at a junction between the second transistor and the additional transistor, and switching means for coupling the photosensitive element between a voltage supply line and the control electrode of the said other transistor to cause the said other transistor to provide a first current representing a first signal produced by the photosensitive element when the photosensitive element is not illuminated and for coupling the photosensitive element between the voltage supply line and the control electrode of the additional transistor to cause the additional transistor to provide a second current representing a second signal produced by the photosensitive element when the photosensitive element is illuminated for causing a third current representing the difference between the first and second signals to be provided at the output.
Although a circuit in accordance with the invention could be manufactured using bulk semiconductor technology, the present invention is particularly intended for use in thin film technology where the photosensitive element may comprise at least one thin film diode, for example a p-i-n diode, a Schottky diode or a metal-insulator-metal (MIM) device, while the or each transistor may comprise an n-channel thin film transistor.
It should of course be appreciated that it is known to try to improve the accuracy of a conventional current mirror arrangement in which a diode-connected first transistor and a second transistor have their control gates coupled so that the current through the first transistor is mirrored by the second transistor by incorporating an amplifying means into the feedback path of the diode to reduce the input impedance and increase the output impedance. As is well known in the art the term diode-connected means that the gate and drain of the transistor are coupled where the transistor is a MOS transistor or the collector and base are coupled where the transistor is a bipolar transistor. In such a circuit, as shown in for example US Patent No. 4,642,551 or EP-A-0523266, the path between the positive input of the amplifying means and the output of the amplifying means is inserted into the diode coupling and the negative input of the amplifying means is connected to the drain or collector electrode, as the case may be, of the second transistor. Such a circuit does not, however, enable the provision of a sink or majority carriers, that is a current source in the case of n channel devices, where only one conductivity type of transistor is available nor does it allow high gain inverters to be formed in such circumstances because these require an active load and an active load coupled to the output of the circuit of US Patent No. 4,642,551 or EP-A-0523266 would necessarily have a source (or emitter)-follower configuration and so would not enable the desired high gain to be achieved.
Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a circuit diagram illustrating a known form of circuit for providing an NMOS inverter;
Figure 2 is a circuit diagram of a circuit for providing a current source in accordance with the invention;
Figure 3 is a circuit diagram similar to figure 2 of a circuit for providing a current source in accordance with the invention but showing one possible form of amplifying means;
Figure 4 is a circuit diagram similar to Figure 3 of a circuit in accordance with the invention but showing a different form of amplifying means;
Figure 5 is an example of a switched current circuit within which a circuit for providing a current source in accordance with the invention may be used;
Figure 6 is a block schematic circuit layout for a device comprising a two-dimensional array of storage elements within which device one or more circuits in accordance with the invention may be used;
Figure 7 illustrates an example of the use of a circuit in accordance with the invention within an image sensor;
Figure 8 shows a cross-sectional view, part broken away, through part of an image sensor incorporating a circuit in accordance with the invention in the manner shown in Figure 7; and
Figure 9 illustrates part of a circuit layout for a two-dimensional image sensor incorporating a circuit in accordance with the invention in a manner similar to that shown in Figure 7.

It should of course be understood that the drawings are not to scale and that like reference numerals are used throughout the text to refer to like parts.
Referring now to Figure 2, 3 or 4 of the drawings, there is illustrated a circuit 10, 10a, 10b for providing a sink for majority charge carriers, in each of the examples shown a circuit for providing a current source, the circuit comprising first and second voltage supply lines 1 and 2, first and second transistors Q1 and Q2 of the same polarity each having a control electrode g1 and g2 and first and second main electrodes d1 and s1 and d2 and s2 and the second transistor Q2 having dimensions which are in a predetermined ratio with corresponding dimensions of the first transistor Q1, the first electrodes d1 and d2 of the first and second transistors Q1 and Q2 being coupled to one 1 of the first and second voltage supply lines 1 and 2, the second electrode s1 of the first transistor Q1 being coupled to the other 2 of the first and second voltage supply lines 1 and 2 by a reference current source 3 for supplying a reference current I_r through the first transistor Q1 and the second electrode s2 of the second transistor Q2 being arranged to be coupled to the other 2 of the first and second voltage supply lines 1 and 2 by a load RL such that in operation of the circuit majority charge carriers flow through the first and second transistors Q1 and Q2 in a direction away from the other 2 of the first and second voltage supply lines 1 and 2, an amplifying means 4 having positive and negative inputs 4a and 4b and an output 4c with the negative input 4b coupled to the second main electrode s1 of the first transistor Q1, the positive input 4a coupled to the second main electrode s2 of the second transistor Q2 and the output 4c coupled to the control electrodes g1 and g2 of the first and second transistors Q1 and Q2 for providing a negative feedback for causing, in use of the circuit, voltages at the positive and negative inputs 4a and 4b of the amplifying means 4 to be equal thereby causing the second transistor Q2 to supply to the load RL coupled between the second main electrode s2 of the second transistor Q2 and the other voltage supply line 2 a current I_o related to the reference current I_r in accordance with the predetermined ratio.
In such a circuit 10, 10a or 10b, the negative feedback causes the output current I_o to be related to the reference current I_r in accordance with the predetermined ratio, that is the circuit acts like a current mirror, and in addition the output impedance is increased by a factor determined by the gain of the amplifying means 4. A circuit is therefore provided which enables a sink for majority charge carriers to be formed without the need for complementary MOS or bipolar technology. For example, a current source can be formed where only n channel enhancement mode MOS transistors are available. The first and second transistors are normally off devices that is devices such as bipolar transistors or enhancement mode MOS transistors which do not conduct until an appropriate voltage is applied to the control electrode of the device in addition to voltages applied to the first and second main electrodes.
Referring now specifically to Figure 2, the first and second transistors Q1 and Q2 comprise, in this example, n channel enhancement mode thin film transistors (TFTs) of any suitable type, for example coplanar, inverted or inverted staggered TFTs, in which the conduction channel region is formed of a suitable semiconductor material such as amorphous or polycrystalline silicon. The structures of such TFTs are well known to the person skilled in the art and need not be described further here.
The drain electrodes d1 and d2 of the first and second TFTs Q1 and Q2 are coupled, as shown directly, to the first voltage (Vdd) supply line 1 while the gate electrodes g1 and g2 are coupled together and to the output 4c of the amplifying means 4. The source electrode s1 of the first TFT Q1 is coupled, as shown directly, to the second voltage (Vss) supply line 2 via a suitable reference current source 3 which may be provided by any suitable source. Thus, for example, the reference current source could be provided by a conventional separate constant current source (for example an external precision resistor) in known manner or may, where the circuit 10 forms part of a larger circuit, be provided by another part of the larger circuit. In some applications, two or more circuits 10 may be provided in the same larger circuit and the reference current for one of the two circuits 10 may then be provided by the output current of the other, if desired. The source electrode s2 of the second TFT Q2 is coupled to the second voltage supply line (Vss) 2 by the load impedance RL which may be any component or circuit for which a constant current I_o is desired.
The source electrode s1 of the first TFT Q1 is also coupled, as shown directly, to the negative input 4b of the amplifying means 4 while the source electrode s2 of the TFT Q2 is also coupled to the positive input 4a of the amplifying means 4. The output of the amplifying means 4 is coupled to the gate electrodes g1 and g2 of the first and second TFTs Q1 and Q2.
The amplifying means 4 may be of any suitable form which provides sufficient gain and examples of suitable amplifying means will be described below with reference to Figures 3 and 4.
The first and second TFTs Q1 and Q2 form the reference and output devices, respectively, of the circuit and in this example are matched so as to have the same channel length and widths and therefore so as to pass the same current in the circuit arrangement shown in Figure 2.
In operation of the circuit shown in Figure 2, the reference current source 3 forces a reference current I_r through the reference transistor Q1 which has gate and source voltages V_g and V_sr, respectively. The negative feedback provided by the amplifying means forces the voltages at the positive and negative inputs 4a and 4b of the amplifying means 4 to be equal so that the first and second TFTs Q1 and Q2 have the same operating conditions and thus their source voltages V_sr and V_so are equal. A current I_o equal to I_r thus flows through the second or output TFT Q2 and through the load RL. Any change in the output voltage, that is the source voltage V_so of the output TFT Q2, will be impressed upon the source voltage V_sr of the reference or first TFT Q1 by the action of the amplifying means 4 so that the reference and output TFTs Q1 and Q2 again have the same operating conditions. Thus, the output current I_o is always the same as the reference current I_r and the circuit acts as a current mirror.
In addition, the output impedance of he circuit 10 is increased by a factor equal to the gain of the amplifier. The output impedance may be calculated by small signal analysis. Thus, the gate voltage V_g of both TFTs Q1 Q2 is given by:

$V_{g} = A_{o} (Δ V_{so} - Δ V_{sr}) 1)$

where A_o is the high open-loop gain of the amplifying means 4 and the ' Δ' sign indicates a small change in the quantity concerned. The output impedance R_out is given by :

The output current I_o is determined by the mutual conductance gm of the output TFT Q2 and the gate-source voltage, therefore:

$Δ I_{o} = gm (Δ V_{g} - Δ V_{so}) 3)$

which gives:

The reference current I_r is defined as being from a reference constant current source 3 and is therefore constant. This means that the gate source voltage of the reference or first TFT Q1 does not change so that ${ΔV}_{g} {= ΔV}_{sr}$
which gives:

The voltage V_g is of course that at the output 4c of the amplifying means 4 so that the output impedance R_out is given by:

which for large amplifier gains becomes effectively:

Thus, as indicated above, the circuit 10 acts as a high output impedance current source which mirrors a given input current I_r.
Figures 3 and 4 are circuit diagrams of particular forms 10a and 10b of the circuit 10 shown in Figure 2, for illustrating some suitable forms for the amplifying means 4' and 4'' as shown inside the dashed boxes in Figures 3 and 4.
In both of the examples illustrated in Figures 3 and 4 the amplifying means 4 is in the form of a long-tailed pair making use of an example of an inverter circuit 5 comprising an input transistor arrangement and a load device comprising a photosensitive element which is illuminated during operation of the inverting circuit. Such an inverting circuit is described in our copending European Patent Application No.94201881.3 filed 30 June 1994 claiming priority of UK Patent Application No.9313842.8 filed on 5th July 1993 (our reference: PHB33857). As illustrated in Figures 3 and 4 the input transistor arrangement comprises third Q3, fourth Q4 and fifth Q5 transistors with each transistor having first and second main electrodes and a control electrode. The control electrode g3 of the third transistor Q3 is coupled to the positive input 4b of the amplifying means 4 while the control electrode g4 of the fourth transistor Q4 is coupled to the negative input 4b of the amplifying means 4. The third and fifth transistors Q3 and Q5 are coupled in series between the first and second voltage supply lines 1 and 2 and the fifth Q3 transistor is also coupled in series with the fourth transistor Q4 and the photosensitive element D1. The photosensitive element D1 is also coupled to the output 4c of the amplifying means 4. In the example illustrated in Figure 3, the transistors Q3 to Q5 are all n channel enhancement mode TFTs. The drain electrode d3 of the third TFT Q3 is coupled to the first supply line 1 while the source electrode s3 is connected to the source electrode s4 of the fourth TFT Q4 and to the drain electrode d5 of the fifth TFT Q5. The source electrode of the fifth TFT Q5 is coupled to the second supply line 2 while the drain electrode d4 of the fourth TFT Q4 is coupled to the anode of the photosensitive diode D1. The cathode of the photosensitive diode D1 is coupled to the first supply line 1.
The control gates g3 and g4 of the third and fourth TFTs Q3 and Q4 provide the positive and negative inputs 4a and 4b of the amplifying means 4' while a junction J2 between the anode of the diode D1 and the drain electrode d4 of the fourth TFT Q4 is coupled to the output 4c of the amplifying means 4. A bias voltage V_b is applied to the control electrode g5 of the fifth TFT Q5. The bias voltage V_b may be derived in any suitable manner and may, for example, be derived from the voltage between the first and second supply lines 1 and 2 using a suitable voltage divider, for example a series of diode-connected n channel TFTs with a tap off connection to the control gate of the fifth TFT Q5 at the position along the chain suitable for providing the required bias voltage. The use of a series of diode-connected n channel TFTs is advantageous in that they can be manufactured with the TFTs Q1 to Q5 using the same process with only a minor modification to the metallisation mask.
The inverter circuit 5 is inactive until the diode D1 is illuminated. The illumination of the photosensitive diode D1 generates a photocurrent which is independent of the reverse-biassing of the photosensitive diode D1. The photosensitive element D1 thus generates a photocurrent which is independent of the voltages to which the photosensitive element is subjected, that is the photosensitive element has a very high impedance and so the gain of the inverter circuit 5 is determined by the output impedance of the TFT Q3.
The amplifying means 4' shown in Figure 3 thus provides a high output which can give gains of the order of 30. The actual value of the gain may not be well defined as it depends upon a number of factors including the TFT Q4 performances and the diode D1 characteristics. However, in the present circuit, although an amplifier of higher gain is required, there is no necessity for the gain of the amplifier to be well defined.
The amplifying means 4'' shown in Figure 4 is also of a long tailed pair configuration but in this case the photosensitive element or diode D1 is replaced by a load or further transistor, again as shown an n channel enhancement mode TFT, Q6. The drain electrode d6 of the further TFT Q6 is coupled to the first supply line 1 while the source electrode s6 is coupled to the drain electrode d4 of the fourth TFT Q4.
A series or chain of photosensitive non-linear resistive devices D2, again in this example photosensitive p-i-n- diodes, is coupled between the control or gate electrode g6 and the first main or source electrode s6 of the load TFT Q6 so that each photosensitive diode D2 has its anode coupled to the cathode of the adjacent diode with the first diode D2 of the series having its anode coupled to the control electrode g6 and the last diode D2 of the series having its cathode coupled to the first main electrode s6 of the load transistor Q6 and via junction J3 to the output 4c of the amplifying means 4''.
In this example, in operation of the inverter circuit 5', the gate-source voltage of the load TFT Q6 is provided by the series or stack of photosensitive diodes D2 when the photosensitive diodes D2 are illuminated. As the gate-source voltage of the load TFT Q6 is not a function of the inverter output voltage the output impedance of the inverter circuit is increased.
The small voltage drop across each photosensitive diode D2 is equal to the forward bias required to give a forward current equal in magnitude to the photocurrent. The number of photosensitive diodes D2 required will depend upon the characteristics of the photosensitive diodes D2 and the particular required characteristics of the inverter circuit (for example there may only be one photosensitive diode d2) but should of course be sufficient to provide a sufficient gate-source voltage to turn on the load TFT Q6.
If even higher gains are required, then the amplifying means 4' and 4'', shown in Figures 3 and 4 could be modified by the addition of an inverting output stage to the long-tailed pair. Such an inverting output stage may be formed by one of the inverter circuits 5 or 5'.
Of course any other suitable form of amplifying means 4 may be used. The examples given in Figures 3 and 4 do however have advantages in enabling a high gain and output impedance using a circuit which requires only transistors of the same polarity as the transistors Q1 and Q2 which is of particular advantage in the present example because currently p channel TFTs with acceptable threshold voltages and operating characteristics are not available.
A current source circuit in accordance with the invention may be used in any circumstances where it is required to provide a constant current source and is particularly useful in those circumstances where the use of complementary transistors is not practically possible or would dramatically increase the complexity of the processing technology used to form the circuit, for example in thin film circuits or Smart Power integrated circuits as discussed above.
One area where constant or bias current sources are often required is in the area of switched current technology which is described in a text book entitled 'switched-currents an analogue technique for digital technology' edited by C Toumazou, J B Hughes and N C Battersby and published in the IEE circuits and systems series by Peter Peregrimus Ltd (ISBN 086341 2947) and will not be discussed in detail here. Briefly, however, the switched-current technique is a current mode signal processing technique which utilises the ability of an MOS transistor (which may be a TFT) to maintain its drain current, when the gate is open-circuited, through the charge stored on the gate oxide capacitance.
Such techniques allow for basis building components such as integrators, delay lines etc to be formed as described in the afore-mentioned text book. A circuit in accordance with the present invention may be used in any appropriate location in any switched-current circuit where a constant bias current is required. Figure 5 illustrates one example of a non-inverting loss-less integrator 20 in which the two current sources 21 and 20 may be provided by respective circuits in accordance with the present invention each designed to provide the appropriate bias currents, with the effective load RL of the circuits being provided by the n channel enhancement mode MOS transistors Q7 and Q8 and the n channel enhancement mode MOS transistor Q9, respectively. Each of these transistors Q7 to Q9 may be a TFT. The transistors Q7 and Q8 are matched while the transistor Q9 has a channel width to length ratio α₁ times that of the transistor Q7. The operation of the circuit 20 shown in Figure 5 is discussed in the afore-mentioned text book at pages 39 to 41 but briefly on phase φ2 of the clock period (n-1), the switches 23 and 24 (which may be of any suitable form, for example MOS transistors) are closed while the switch 25 is open so that transistor Q7 is diode-connected and receives current i(n-1) from the input plus 2J from the bias current source 21 plus $-(J-io(n-1)/α₁)$
from the transistor Q8. On the next phase φ1 of the clock period (n), the switches 23 and 24 are open and the switch 25 is closed so that the transistor Q8 is diode-connected and passes a current $I2 = 2J - I1$
while the output current i_out(n) is α₁(J-I1).
Such an integrator may of course be used in any appropriate circuitry, for example in video signal processing circuitry.
A circuit in accordance with the invention and switched-current circuits using such circuits may be of particular interest in relation to two-dimensional active matrix addressed array 10 devices formed using thin film technology. Figure 6 shows one example of such an array 30 which comprises an array of storage elements 31 arranged in rows and columns n and m. Each storage element 31 may be for example a display element where the array 30 forms an electro-optic, eg liquid crystal, display, a memory element such as a transistor, or a photosensitive element such as a p-i-n diode where the array forms an image sensor. Of course, the array 30 could combine two or more of these functions by providing different types of storage elements 31.
The storage elements 31 are illustrated simply as capacitances in Figure 6. This capacitance will be the capacitance of the display element in the case of a display, the intrinsic photodiode (plus any additional capacitance) capacitance in the case of an image sensor and the storage capacitance of a memory element in the case of a thin film memory.
In the example illustrated, one plate of each capacitance 31 is coupled to a common electrode held at a reference potential which may, as illustrated, be earth (ground) while the other plate is coupled to one of the main electrodes of an n-channel enhancement mode TFT switching element 32 which together with the storage element 31 forms an array element or pixel. The gate or control electrodes of all the TFTs 32 associated with a row n of storage elements 31 are coupled to the same row conductor 33 while the other main electrodes of all the TFTs associated with a column m of storage elements 32 are coupled to the same column conductor 34. Row and column addressing circuitry 35 and 36 are provided to enable each storage element to be accessed individually via the switching element TFTs 32. The actual nature of the row and column addressing circuits 35 and 36 will of course depend upon the precise nature of the array, for example whether it is a display or image sensor with, in the former case, the column addressing circuits being required to supply video signal information to the array and in the latter case to enable read-out of charge stored at the photosensitive elements. Examples of row and column addressing circuitry for these two instances may be found in many publications. Thus, for example, reference may be made to EP-A-391655 or GB-A-2186414 for examples of methods of driving a liquid crystal display while reference may be made, for example, to US-A-5003167 or US-A-4382187, or US-A-4945243, for example, for examples of methods of driving image sensors. It will be evident to those skilled in the art that other types of switching elements (diodes, TFTs etc) may be used (see, for example, US-A-4945243 or EP-A-233104) and that other circuit layouts may be possible. Also, although only a 3 by 3 active area 30a matrix array of storage elements 31 has been shown in Figure 4 in practice the array will consist of many more storage elements, with the actual number depending upon the desired application.
Although the row and column addressing circuitry of such array devices generally involves the use of shift registers and the like which do not normally require the use of current source circuits of the form shown in Figures 2 to 4, there is a move towards both the integration of the row and column driver circuitry onto the same substrate, generally a glass or plastics substrate, as the array 30 and moreover, particularly in the case of image sensor, to the incorporation of additional functionality into the image sensor array. Such functionality may include, for example, pixel level gain, analogue-to-digital (A/D) conversion and simple image processing operations such as nearest neighbour averaging. Many of these pixel level signal processing functions require means for manipulating the signals provided by the pixels which require constant (high output impedance) current sources which may advantageously be realised using a circuit in accordance with the present invention.
Figure 7 illustrates an example of a way in which a circuit 10 in accordance with the invention may be used within an image sensor. In this case, the circuit 10 is used to enable subtraction of the "black" signal, that is the signal produced by a photosensitive element of the image sensor when that photosensitive element is not illuminated, from the signal produced when the photosensitive element is illuminated so as to ensure that the output signal accurately represents the light sensed.
As illustrated in Figure 7, the circuit 10 is as shown in Figure 2 with, in this example, the reference current source 3 being provided by an n channel enhancement mode TFT Q7 and the load resistance RL by a further n channel enhancement mode TFT Q8. A respective capacitor C1 and C2 is coupled between the source and gate electrodes of each of the TFTs Q7 and Q8. The gate or control electrode of each of the TFTs Q7 and Q8 is coupled via a respective switch SW1 and SW2 to the photosensitive element D3 of a pixel or imaging element 41 of the image sensor 40. In this example, each of the switches SW1 and SW2 couples the gate electrode of the associated TFT Q7 or Q8 to the anode of a photosensitive diode D3 having its cathode coupled to a reference potential V_ref. The anode of the photosensitive diode D3 is also coupled via a third switch SW3 to a reset voltage V_rst. The switches SW1 to SW3 may be n channel TFTs controlled by the application of appropriate voltages to their respective gate electrodes in known manner.
In order to understand the operation of the black signal subtracting circuit shown in Figure 7, consider the situation when the photosensitive diode D3 has just been reset by closing (or rendering conducting) the switch SW3. The photosensitive diode D3 is first shielded from incident light and then the switch SW3 is opened (rendered non-conducting). The switch SW1 is then closed or rendered conducting for a predetermined time to couple the photosensitive diode D3 to the control electrode of the TFT Q7 to allow charge generated in the photosensitive diode while it is not illuminated (the "black" signal) to be stored on the capacitor C1. The switch SW1 is then opened (rendered non-conducting). If considered desirable, the photosensitive diode may be reset again before allowing the photosensitive diode to be illuminated. Light is then caused to fall on the photosensitive diode D3 with the switch SW2 closed or rendered conducting for the predetermined time to allow charge generated during the illumination of the photosensitive diode to be transferred to the insulated gate of the TFT Q8 which passes a current I_s+d representing the desired signal for the light sensed by the photosensitive diode during illumination plus the "black" signal. The TFT Q7, by virtue of the charge stored on the capacitor C1, passes a current I_d representing the "black" signal which provides the reference current for the circuit 10. The effect of the circuit 10 is to cause the same current I_d to flow through the TFTs Q1 and Q2. Of course, the TFT Q8 is passing a current I_s+d and so, to provide continuity of current at the output O, a current of I_s must, by Kirchhoff's law, flow into the junction J1. The output O thus provides a current signal I_s which is representative of the actual light sensed by the photosensitive diode, that is a signal from which the "black" signal has been subtracted.
The photosensitive diode D1 or D2 of the amplifier 4 of the circuit 10 need not be illuminated during the storage of charge representing the "black" signal on the capacitor C2 but is of course illuminated during the illumination of the photosensitive diode D3 to enable operation of the circuit 10. Although it would be possible to use the light illuminating the photosensitive diode D3 to illuminate the photosensitive diode D1 or D2, the light falling on the image sensor will of course vary and the use of a separate constant light source for the photosensitive diode D1 or D2 is desirable. This may be achieved by designing the photosensitive diode metallisation so that the photosensitive diodes D3 can only receive light incident on the top surface of the diode while the photosensitive diodes D2 or D3 can only receive light incident on the bottom surface of the diode.
Figure 8 illustrates a very schematic cross-section, part broken away, through an image sensor formed by thin film technology on an insulating, generally glass, substrate 42 to show an arrangement enabling different photosensitive diodes to receive light from different directions.
In particular, Figure 8 shows an example of a photosensitive diode D1 and an associated n channel enhancement mode TFT, for example the TFT Q4, plus an example of a photosensitive diode D3 and an associated n channel enhancement mode TFT which forms one of the switches SW1 to SW3. All of the TFTs may have the same structure.
Figure 8 shows an inverted staggered structure for the TFTs SW1 and Q4. Thus, each TFT has a, generally, chromium gate electrode g provided on a conductive track 43, generally chromium, which provides an appropriate connection to other parts of the circuit. A gate insulating layer 44, generally silicon nitride, covers the gate electrode g and is itself covered by an intrinsic (not-intentionally doped) semiconductor, generally polycrystalline silicon, conduction channel-forming layer 45 by conventional deposition and lithographic techniques. A conventional etch stop insulating region 46 is provided over a control area of the channel-forming layer 45 and then n conductivity doped semiconductor regions 47 and source and drain electrode (generally chromium) regions s and d are deposited and defined over which is provided an insulating layer 48 through which contact windows are formed to allow a metallisation layer, generally chromium plus aluminium, to be deposited and defined to provide the source and drain electrodes 48 which also provide connection to other parts of the circuit.
The metallisation forming one of the source and drain electrodes 49 also forms one electrode 50a or 50b of the associated photosensitive diode. In each case, the photosensitive diodes D1, D2 and D3 are generally formed as n-i-p diodes by depositing and patterning layers of appropriately doped semiconductor material, generally amorphous silicon. A further insulating layer 51, generally of silicon nitride, is then deposited and patterned and further metallisation deposited and patterned to provide the other electrodes 52a and 52b for the photosensitive diodes. As can be seen from Figure 8, the lower electrode 50a of a photosensitive diode D1 or D2 is provided with an opening to enable light from an appropriate back light BL to be incident on the photosensitive diode D1 or D2 while the lower electrode 50b of the photosensitive diode D3 shields the photosensitive diode D3 from direct illumination by the back light BL. In contrast, the top electrode 52a of a photosensitive diode D1 or D2 shields it from incident light while the top electrode 52b of a photosensitive diode D3 is formed to enable light to be incident on the top of the photosensitive diode D3. The image sensor may, as shown, be covered by a protective insulating layer 53 of a material such as polyimide onto which a document D to be sensed may be placed. In such a case, the document may be illuminated by a separate light source or by light from the back light BL passing through light transmissive portions of the image sensor 40. In such an image sensor, the "black" signal may be obtained simply by switching off the light source which is used to illuminate the photosensitive diodes D3.
Of course, where the object to be sensed is not placed in direct contact with the image sensor, then the ambient conditions may provide sufficient light to enable sensing of the object. In such a case, however, a suitable shutter, for example a mechanical or liquid crystal display shutter, will be required to shield the photosensitive diodes D3 from ambient light in order to obtain the "black" signal.
Although Figure 7 shows only one pixel 41, it will of course be appreciated by the person skilled in the art that the circuit shown in Figure 7 could be applied to a two-dimensional active matrix addressed image sensor array having a matrix array of pixels 41 in which individual pixels are accessed by row and column conductors 54 and 55 with, in this example, the cathodes of the photosensitive diodes D3 coupled to their respective row conductors 54. Also, with the appropriate use of additional switches, generally again n channel TFTs, it may be possible for a single circuit 10 to be shared by all the pixels in a column of the array. Figure 9 illustrates part of one column m of a two-dimensional array to show one possible arrangement in which each photosensitive diode D3 has its own capacitors C1 and C2 and switches SW1 to SW3 but in which only one TFT Q7 and one TFT Q8 is provided for each column of pixel. In this case, each capacitor C1 is coupled by a respective Switch SW4 to a first column conductor 55a coupled to the control electrode of the TFT Q7 and each capacitor C2 is coupled by a respective switch SW5 to a second column conductor 55b coupled to the control electrode of the TFT Q8. By the use of appropriate timing signals to control the operation of the switches SW1 to SW5, the charge stored on the capacitor C2 of a photosensitive diode D3 in row N may be being read while the photosensitive diode D3 in row N-1 is being reset and the photosensitive diodes D3 in the subsequent rows N+1 and so on are being illuminated to store charge on the associated capacitors C2. Depending upon the length of time for which the capacitors C1 can hold their charge and the time taken to read out the photosensitive diodes of the whole array, the "black" signal for each photosensitive diode D3 of the array may be obtained initially before any of the photosensitive diodes D3 are read out or may be obtained just before the particular photosensitive diode D3 is read out in the manner described above. The columns m of photosensitive diodes D3 may be read out simultaneously if a separate circuit 10 is provided for each column or a suitable multiplexing arrangement may be used so enabling the use of a single circuit 10 for the entire array.
As indicated above, the present invention enables the formation of a high output impedance circuit forming a sink for majority charge carriers which requires the use of only one polarity of transistor (n type, generally n channel enhancement mode MOS transistors, where a current source is required) and may be used to advantage in thin film technology circuits such as control circuitry for thin film displays , image sensors and memories and also in bulk semiconductor technology for example, Smart Power applications. Such majority charge carrier sinks may also be used to realise current mirrors and of course the value of the output current may be adjusted accordingly using known current mirroring techniques. The present invention could also be used to provide a constant voltage source across a suitable load.
Although in the examples described above, the transistors Q1 and Q2 are matched so as to pass the same current, these transistors may, with appropriate modification of the circuit, merely be similar and so pass currents in a predetermined ratio (not equal to one) to one another so that the output current I_o is in that predetermined ratio with the reference current I_r.
Generally all of the components of a circuit 10 in accordance with the invention will be integrated on or in the same substrate. However it may be possible for one or more (or indeed all of) the components to be provided as discrete components.
The present invention could of course in principle be applied to the situation where the available transistors are p type, for example pnp bipolar transistors or p channel enhancement mode MOS transistors, with appropriate changes of voltage polarity etc, to form a circuit providing a current sink which, as indicated above, is difficult to form where only p type devices are available. However, the circumstances where such a p type device circuit is required or desirable may only occur where, for example, logic circuitry requiring current sources is to be integrated with a p channel vertical power device for some specialist purpose.
Of course, the enhancement mode MOS transistors, except for the transistor Q6 in Figure 4, mentioned above could be replaced by appropriate polarity (that is npn bipolar transistors replacing n channel MOS transistors) bipolar transistors especially where the circuit is formed using bulk technology rather than thin film technology.
From reading the present disclosure, other modifications and variations will be apparent to persons skilled in the art. Such modifications and variations may involve other features which are already known in the art and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

A circuit for providing a sink for majority charge carriers, the circuit comprising first and second voltage supply lines, first and second transistors of the same polarity each having a control electrode and first and second main electrodes and the second transistor having dimensions which are in a predetermined ratio with corresponding dimensions of the first transistor, the first electrodes of the first and second transistors being coupled to one of the first and second voltage supply lines, the second electrode of the first transistor being coupled to the other of the first and second voltage supply lines by a reference current source for supplying a reference current through the first transistor and the second electrode of the second transistor being arranged to be coupled to the other of the first and second voltage supply lines by a load such that in operation of the circuit majority charge carriers flow through the first and second transistors in a direction away from the other of the first and second voltage supply lines, an amplifying means having positive and negative inputs and an output with the negative input coupled to the second main electrode of the first transistor, the positive input coupled to the second main electrode of the second transistor and the output coupled to the control electrodes of the first and second transistors for providing a negative feedback for causing, in use of the circuit, voltages at the positive and negative inputs of the amplifying means to be equal thereby causing the second transistor to supply to the load coupled between the second main electrode of the second transistor and the other voltage supply line a current related to the reference current in accordance with the predetermined ratio.
A circuit according to Claim 1 for providing a current source, wherein the first and second transistors comprise n-channel enhancement mode MOS transistors having their source electrodes coupled to the negative and positive inputs, respectively, of the amplifying means.
A circuit according to Claim 1, wherein the first and second transistors are matched.
A circuit according to Claim 1, 2 or 3, wherein the amplifying means comprises an inverting circuit comprising an input transistor arrangement coupled to the positive and negative inputs and a load device comprising a photosensitive element which is illuminated during operation of the inverting circuit.
A circuit according to Claim 4, wherein the input transistor arrangement comprises third, fourth and fifth transistors with each transistor having first and second main electrodes and a control electrode with the control electrode of the third transistor being coupled to the positive input, the control electrode of the fourth transistor being coupled to the negative input and the control electrode of the fifth transistor being coupled to a bias voltage supply, the third and fifth transistors being coupled in series between the first and second voltage supply lines and the fifth transistor also being coupled in series with the fourth transistor and the photosensitive element which is also coupled to the output of the amplifying means.
A circuit according to Claim 5 wherein the photosensitive element comprises a photosensitive non-linear resistive device coupled between the first main electrode of the fourth transistor and the first supply line.
A circuit according to Claim 5, wherein the photosensitive element comprises at least one photosensitive device coupled between the second main electrode and the control electrode of a further transistor coupled in series with the fourth transistor for providing, when illuminated, a voltage between the second main and control electrodes of the further transistor.
A switched current circuit comprising a current source circuit in accordance with any one of the preceding claims.
A device comprising a two dimensional array of storage elements arranged in rows and columns, row and column conductors for accessing individual ones of the storage elements and control circuitry for controlling access of the storage elements by the row and column conductors, the control circuitry comprising at least one circuit in accordance with any one of Claims 1 to 8.
An image sensor comprising at least one photosensitive element, a circuit in accordance with any one of Claims 1 to 7, another transistor having first and second main electrodes and an insulated gate electrode, the said other transistor being coupled in series with the first transistor between the first and second voltage supply lines to provide the reference current source for the circuit, an additional transistor having first and second main electrodes and a control electrode, the said additional transistor being coupled in series with the second transistor between the first and second voltage supply lines to provide the load source for the circuit, an output provided at a junction between the second transistor and the further transistor, switching means for coupling the photosensitive element between a voltage supply line and the control electrode of the said other transistor to cause the said other transistor to provide a first current representing a first signal produced by the photosensitive element when the photosensitive element is not illuminated and for coupling the photosensitive element between the voltage supply line and the control electrode of the additional transistor to cause the additional transistor to provide a second current representing a second signal produced by the photosensitive element when the photosensitive element is illuminated for causing a third current representing the difference between the first and second signals to be provided at the output.