JPH06230746A - Active-matrix liquid-crystal display system and operating method of said system - Google Patents

Abstract

PURPOSE: To provide the active matrix liquid crystal display system which includes a storage element and an MIM diode block element and its driving method. CONSTITUTION: The storage element 46 has its address specified through pairs of parallel row select address lines 12 and 12', 14 and 14', and column address lines 18 and 20. A couple of MIM devices 34 and 36 are connected between the row select address lines 12 and 12', and the storage element 46 is connected between a common node 38 and a column address line 18 which is applied with a charging potential. When the storage element is discharged, an operating potential, having the opposite polarity, is applied to the pairs of row select address lines, so that the two MIM devices are biased forward and backward, and consequently electric charges are held in the storage element.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to electronic matrix systems and methods of operating the systems. The present invention is particularly directed to a matrix system including a storage element and using a MIM diode blocking element,
And a driving means for promptly accumulating charges in a selected storage element and effectively storing the accumulated charges. The present invention is particularly useful in active matrix liquid crystal display systems in which the storage elements are in the form of display pixels.

[0002]

In many electronic matrix systems,
An array of storage elements, each having a single address, is used to store charge, and may be used, for example, in memory arrays and light sensitive displays.
ncing displays). In this light sensitive display device, the storage element is in the form of a pixel.
Pixels generally include a set of spaced and facing electrodes with the light sensitive material disposed therebetween. As a result, each pixel constitutes a capacitor capable of accumulating charges. When the charge is accumulated in the pixel,
A voltage potential traverses the electrodes and an electric field traverses the photosensitive material. By controlling the amount of stored charge, the properties of the photosensitive material can be controlled to obtain the desired photosensitive effect.

When the light-sensitive material is a liquid crystal material, alignment of the liquid crystal material molecules can be performed when the electric field applied to the material exceeds a certain threshold. As is well known, liquid crystal display systems generally include polarizers disposed on opposite sides of the system and alignment layers disposed on opposite sides of the liquid crystal display material. When the electric field across the liquid crystal display material exceeds a threshold value, the pixel may be light transmissive or light absorbing depending on the relative alignment of the polarizer and the alignment layer. When the electric field falls below the threshold, the opposite photosensitivity may be obtained. Since display systems generally include many pixels, an image can be formed by selectively controlling which pixels are light transmissive and which are light absorptive.

In a liquid crystal display system (LCD), it is necessary to update the condition of each pixel at regular intervals, for example at a frame rate of 30 frames / sec. This is necessary because the pixel can store or store the applied potential for a limited time. Renewal is also needed when nematic liquid crystal display materials are used.
Because the applied electric potential is an alternator to avoid such deterioration of the liquid crystal display material.
e) It must be reversed during the frame. Updates are also needed when the displayed image is expected to change regularly, for example when the displayed image is constantly moving. Therefore, the ability to quickly transfer and store charge to a pixel and to effectively store the stored charge for at least one frame period is important.

Active matrices have been used to accurately drive the pixels of liquid crystal display systems. In such an active matrix, each pixel is coupled to one or more threshold devices and the electric potential to be stored in the pixels is applied to the pixels through this threshold device. The threshold device was in the form of a field effect transistor or a pin diode. For example, various active matrices using differently configured threshold devices have been disclosed, for example, by Marlowe et al., US Pat. No. 3,654,606, Ring, which discloses a discrete crystalline silicon diode in an anode-cathode diode configuration. US Pat. No. 4,251,13 to Miner et al. Teaching a diode structure.
No. 6 and paper "Active Addressing"
for Flat Panel Display ”
(62 Japan Display 1986).

Active matrix liquid crystal display systems that use amorphous silicon diodes as threshold devices are described, for example, in Robert issued September 19, 1989.
tR. Johnson, Vincent D.M. Ca
It is disclosed in US Pat. No. 4,868,616 by Nnella and Zvi Yaniv. In at least one embodiment disclosed in this patent, each pixel includes a pair of pin diodes coupled in non-opposing anode-cathode relationship between a pair of address lines and a common node. I'm out. One electrode of the pixel is coupled to the common node and the other electrode is coupled to the other address line or data line to which a potential for charging the pixel is applied. The nematic liquid crystal display material is arranged between the electrodes. When a charging potential is applied to a pixel, one of the p-i-n diodes is biased into an off state and the other p-i-n diode is biased by the potential applied to the pair of address lines and the data line. Will be turned on. Therefore, a charging potential is applied through one of the p-i-n diodes to charge the pixel. As a result, in order to provide the pixel with sufficient current to charge the pixel, the non-linear characteristics of the on-state pin diode must be overcome. In order to provide this current, the voltage drop across the p-i-n diode must be overcome and the charging potential must also be p-.
It must be provided for a time sufficient to adjust the series resistance provided by the in diode. During the next frame, the diode states are reversed to coordinate the reversal of the polarity of the charging potential. This may change the voltage at the common node. Such distribution of potentials at common nodes can present difficulties in controlling the maximum voltage at which a pixel is charged and can adversely affect grayscale operation of the display system.

Among others, the pin diode has a characteristic capacitance associated with it. This capacitance can reduce the operation of the pixel. p-i
As an example of the unfavorable effect of the capacitance of a -n diode, imparting an opposite polarity to the charge stored in the capacitance of a liquid crystal pixel can reduce the sensitivity of the pixel to the charge imparted to the pixel. Substantially all of the methods conventionally used for addressing (ie, applying a series of electrical pulses to a liquid crystal matrix array to charge and discharge individual pixels in an active matrix liquid crystal display system). The above effect has been confirmed and is commonly known as the "capacitive kick" effect. When a p-i-n diode is switched from an off or blocking state to an on or conducting state so as to store or dissipate the charge on the pixel by recharging the capacitance associated with this diode. , The current required to dissipate the charge present on the p-i-n diode cannot be distinguished from the current required to recharge the pixel capacitance. In this situation, the liquid crystal pixels can be charged improperly. It was just a problem that diode devices were used to prevent it. Examples of these types of driving methods are disclosed, for example, in Marlowe et al., U.S. Pat. No. 3,654,606 and Pankratz et al., U.S. Pat. No. 3,765,747.

At the end of the charging period when the p-i-n diode is switched from the on or conducting state to the off or blocking state, a possibly more serious similar problem known as "capacitive kick" occurs.
Normally, the p-i-n diode at this point causes a considerable voltage drop across the electrode of the diode carrying the current.
Due to this voltage drop, a considerable charge can be transferred from the capacitance of the liquid crystal element of the pixel to the capacitance of the isolation device. Due to this charge transfer, no voltage is maintained through the liquid crystal element, and this transfer cannot be easily distinguished from the current stored in the liquid crystal element. This adversely affects the accuracy of the information stored in the liquid crystal element.

In conventional arrays of liquid crystal elements, the "capacitive kick" effect is always present and always adversely affects the signal to noise ratio of the liquid crystal element. The magnitude of the "capacitive kick" or "capacitive kickback" problem is directly related to the relative size difference between the pin diode and the liquid crystal element (and thus the ratio of the capacitances of these elements). . This is because the capacitance of the circuit element is directly related to the physical dimensions of the circuit element. In order to prevent the above-mentioned charge transfer from hindering the accumulation of the video voltage on the liquid crystal element, the dimension ratio of the conventional liquid crystal element: the p-i-n diode should be at least 5: 1.
It has been desired to maintain at (preferably at a ratio of 10: 1 or higher).

"Capacitive kick" has become a serious problem and severely limits the performance of high resolution liquid crystal display systems containing relatively small area liquid crystal elements. The problem of "capacitive kick" in such arrays is increased because the ratio of liquid crystal element area to blocking element area is considerably smaller. Greater than desired ratios cannot be maintained. This is because processing has a lower limit on the size of the blocking element, especially in wide area display systems where there are physical constraints on lithography, and productivity problems become much more serious when the minimum external dimensions of lithography become smaller. This is because it is set. As a result, absolute sensitivity and operating speed have traditionally decreased as the resolution of liquid crystal display systems increased.

A driving method which avoids the aforementioned problems associated with "capacitance kick and capacitance kickback" is the only one disclosed in Baron et al., US Pat. No. 4,731,610. However, this patent is limited to the teachings of LCDs that use pin diodes and field effect transistors as blocking elements located around a common node. As discussed in more detail below, these types of devices have their own drawbacks when used in LCDs. These drawbacks are solved by this patent.

In particular, the FET and the p-i-n diode, when used in an LCD, are each manufactured 7 times.
Or requires mask steps up to 4 and requires a critical alignment of 1 micrometer. Therefore, these complex structures reduce the productivity of the components available to the manufacturing process and thus increase production costs. Moreover, the FETs require the address lines to be crossed on a common substrate, which reduces shorts and further reduces productivity. Instead, the LCD device disclosed in this patent specification is metal-insulator-that can be manufactured with as few mask steps as two times.
It is equipped with a metal (MIM) type blocking element, which further simplifies manufacturing and increases productivity.
Furthermore, by driving an LCD having a MIM, which will be described later, by the above-mentioned balanced drive addressing method, the myriad of problems (that is, capacitance kick, etc.) described above can be avoided. LCD equipped with MIM device which is a conventional technology
Even though it includes MIM, there is only one MIM arranged in series with the liquid crystal pixel. as a result,
1) image instability due to device instability, storage effects reduce image quality, 2) large device capacitance causes the aforementioned "kickback effect", and 3) device non-uniformity in the display area. A display system defect is characterized by a lack of gray scale control and gray scale uniformity.

In addition to the problems mentioned above, it has been difficult to manufacture wide area electronic matrices, such as wide area display systems, ie devices having exactly the same IV characteristics with respect to the total length and width of the matrix. Thus, a voltage applied to one pixel to reach a particular grayscale effect or level will have exactly the same grayscale effect or level, especially when applied to another pixel located some distance from the first pixel. It cannot happen.

Therefore, the structure of the active matrix LCD,
There is a need for an addressing method that simplifies the manufacture of threshold devices, such as MIM and MIM, while eliminating their inherent limitations.

[0015]

SUMMARY OF THE INVENTION The present invention provides an active matrix liquid crystal display system for rapidly accumulating and effectively storing charge in a selected one of a plurality of liquid crystal pixels. To do. The system intersects the address line pairs at an angle and is spaced from the address line pairs to form a plurality of substantially parallel address line pairs and intersections with the address line pairs. Included are a plurality of substantially parallel additional address lines disposed and a set of threshold devices serially coupled to a common node between pairs of address lines coupled at the intersections. The threshold device used in the present invention cuts off the current at a low bias (ie voltage 5) regardless of polarity.
V at a current ^{10 -11} A) and passing a current at a high bias (i.e. limited by the voltage 15V current ¹⁰ -6 A) MIM type devices. This is because the MIM device is bidirectional, so the IV curve of the device is symmetrical with respect to polarity.

Each liquid crystal pixel is coupled between one of the common nodes and one of the additional address lines. The system further comprises a substantially equal magnitude and opposite polarity second bias to bias the threshold device to a conductive state to facilitate charge storage in a storage element coupled to the pair of address lines. First means for applying an operating potential of 1 to the pair of address lines, and for providing charge to be stored to the selected storage element while the first operating potential is applied to the pair of address lines. And second means for applying a potential to a selected one of the additional address lines.

Since the MIM device is of a type that provides a high impedance with respect to the flow of current at a low bias, the first potential applying means can easily store the charge accumulated in the pixels coupled to the pair of address lines. In order to achieve the above, a second operating potential substantially equal to or lower than the voltage for energizing the MIM device is applied between the pair of address lines.

The present invention further includes an active matrix, including a MIM device, for rapidly accumulating and effectively storing charge in a selected one of a plurality of pixels in a display system. A method of operating an LCD is provided.
The method provides a plurality of pairs of address lines that are substantially parallel, intersects the pair of address lines at an angle and is spaced apart from the pair of address lines to form a plurality of intersections with the pair of address lines. Providing a plurality of substantially parallel additional address lines that are placed side by side and having a set of MIs
The step of coupling the M devices together at the common node between the address lines coupled at the intersections. The MIM device is a type that cuts off current with a low bias and passes current with a high bias regardless of polarity. This is because the MIM device is bidirectional, and thus the IV characteristic of this device is symmetrical with respect to polarity. The method further includes the common node 1
One of the additional address lines and one of the additional address lines to facilitate storage of charge in the storage element coupled to the address line (substantially equal in magnitude and opposite in polarity). ) A first operating potential is applied between the address lines, and while the first operating potential is applied to the pair of address lines in order to accumulate charges in the selected pixel,
The step of applying a charging potential to a selected one of the additional address lines is included.

Since the MIM device is of the type that provides high impedance to current flow at low bias, the method further facilitates storage of the charge stored in the pixels coupled to the address line pairs. A second of substantially equal magnitude to bias the MIM device in the second state.
Of operating potentials between the pairs of address lines.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is an illustration in the form of a schematic circuit diagram showing an active matrix liquid crystal display system 10 according to the present invention. The system 10 includes two substantially parallel to each other.
Book row select lines 12, 12 ', 14, 14', and 1
It includes three pairs of address lines 6 and 16 'and two additional or column address lines 18 and 20 which are substantially parallel to each other. The column address lines 18 and 20 intersect the row select address line pair at a given angle without touching the address line pair to form a plurality of intersections. Preferably, the column address line 18
And 20 intersect the row select address line pair substantially at right angles.

System 10 also has one pixel at each intersection defined by the intersection of the row select lines and the column address lines. That is, the system 10 has pixels 22, 2
4, 26, 28, 30 and 32 are included. Although only six pixels are shown, system 10 includes a larger number of row select line pairs and column address lines as shown, with correspondingly more than the six pixels shown arranged in a matrix, which is useful. It should of course be understood that a display system is realized having a sufficient number of pixels to form an image.

Since the pixels are preferably substantially equivalent to each other, only pixel 22 will be described in detail herein.
Pixel 22 has a pair of threshold devices 34 and 3 connected together at a common node 38, as seen in FIG.
Including 6. Threshold devices 34 and 36 are metal-insulator-metal (MIM) devices, both connected between lines 12 and 12 'of a row select address line pair.
These MIM devices provide a high impedance to the current through the device when biased (or unbiased) with a small bias, ie, a current of 10 ⁻¹¹ A at a voltage of 5 V, and a current of 10 ⁻ at a voltage of 15 V. ^It is characterized by a low impedance when a large bias of ⁶ A is applied. Moreover, this feature is independent of the polarity of the applied bias, because the MIM device is bidirectional and therefore the IV characteristic is symmetrical with respect to polarity. This MIM, in which two MIM devices are arranged symmetrically with respect to a common node electrically associated with the first electrode of the pixel
The M configuration provides significant operational advantages over conventional display pixels that include only one MIM device. This advantage will be described later in detail.

Pixel 22 also includes a pair of spaced electrodes 40 and 42 opposite each other. A light-influencing material 44 is arranged between the electrodes 40 and 42. The "light-affecting material" is intended to include any luminescent material and any material capable of selectively changing the intensity, phase, or polarization of reflected or transmitted light. According to a preferred example,
The light-influencing material 44 is a display liquid crystal material such as a nematic liquid crystal material.

Electrodes 40 with a display liquid crystal material 44 sandwiched therebetween
And 42 constitute a storage element 46 or a capacitor capable of storing charges. The storage element 46 includes a common node 38 between the MIM devices 34 and 36 and a column address line 1
It is connected between 8 and.

The MIM devices 34 and 36 are preferably composed of a deposited layer of metallic or metallic and insulating material. In particular, the MIM device used in the present invention typically includes a first metallic material layer of a transparent conductive oxide material such as indium tin oxide (ITO). On top of the first layer is deposited a layer of an insulating material such as SiN _x or Ta ₂ O ₅ , preferably a SiN _x layer, on top of which a third layer of metal, preferably chromium, is provided. Has been deposited. The chrome deposit layer typically must be etched to form, for example, address lines, electrical interconnects, businesses, and the like. However, in a preferred example, the SiN _x layer may be formed substantially transparent (ie, 90% transparent), thus requiring additional masking and etching steps because the amorphous semiconductor layer is not transparent, eg pin type. Unlike in the case of a display device using a diode, it is not necessary to etch the SiN _x layer. Of course, the SiN _x layer becomes yellow when its Si content is high and requires etching. Moreover, the Si-rich layer is relatively sensitive to light, thus requiring a separator masking step to form a light blocking film.

System 10 includes lines 12, 12 ', 14, 14', 16 and 16 'of row select address line pairs.
Outputs R ₁ , R ₁ ′, R ₂ , respectively connected to
Also included is a row select driver 50 having R ₂ ′, R ₃ and R ₃ ′. The row selection driver 50 generates a driving signal at its outputs R ₁ , R ₁ ′, R ₂ , R ₂ ′, R ₃ and R ₃ ′ to select the first operating potential with a large bias as described later. A voltage is applied between the two lines of the address line pair, which brings the MIM device into a conductive state, and as a result, it becomes easy to store charges in the storage element connected to the device. The row selection driver 50 also applies a small bias second operating potential between the two lines of the row selection address line pair to generate M.
The IM device is brought into a non-conducting state, whereby the electric charge stored in the storage element connected to the MIM device is easily retained.

Finally, the system 10 includes a column driver 52. The column driver 52 includes column address lines 18 and 2
It has outputs C ₁ and C ₂ respectively connected to 0. The column driver 52 applies a charging potential to a column address line selected so that charges are stored in the selected storage element when the first operating potential is applied to the row selection address line pair by the row selection driver 50. Apply.

The symmetric MIM (SMIM) configuration is particularly sensitive to changes in the operating characteristics of MIM devices.
It is especially important that it is not sensitive compared to the usual display pixel configuration that only includes the device. Normal single MIM
In the equivalent circuit of a display device, the voltage applied to the MIM device decreases as the pixel is charged, that is, the charging potential is applied to the pixel. As a result, the MIM current is weakened and the charging speed is reduced, so that the charging is not saturated. In this case, the final voltage at the end of the scan time strictly depends on the IV characteristics of the MIM device. Within the symmetrical MIM circuitry there is a reserve current path to the second MIM diode in the same scan mode. The high current is maintained until the end of the scan cycle and the charge saturates. That is, the final voltage applied to the LC at the end of the scan time is I of the MIM device.
The dependence on the V-curve is much smaller (see Figure 4). Si
Image holding in the N _x display device is realized by lowering the charging characteristic K of the device of the pixel that has been in the ON state for a longer period than the surrounding pixels in the OFF state. K
Also varies due to device non-uniformity (eg, due to the fact that the thickness of the SiN _x layer is not precisely controlled over the display area). Since the holding voltage does not depend on K in the SIMM configuration, this configuration can be used to avoid the effects of device degradation and non-uniformity. The capacitance kickback (described in detail later) is also SM
It is excluded in IM pixels because the kickbacks for the two diodes have opposite polarities in the same scan mode and compensate each other.

2A-2C show a first set of waveforms showing how charge is stored in the storage element 46 of the pixel 22 and then held therein. That is, FIG. 2A shows a waveform of a signal emitted from the output C ₁ of the column driver 52, FIG. 2B shows a waveform of a signal emitted from the output R ₁ of the row selection driver 50, and FIG. 2C shows a row selection driver. 5 shows the waveform of the signal emanating from the output R ₁ ′ of 50.

At time t ₀ , the row selection driver 50 has a row selection line 12 of -15V and a row selection line 12 'of + 15V.
To bias MIM devices 34 and 36,
Make it conductive. By biasing the MIM devices 34 and 36 in this way, the charge previously stored in the storage element 46 is retained in this element 46. If charge should be stored in the storage element 46 again in the next frame,
The column driver 52 outputs + 3V from the output C ₁ connected to the column address line 18 at time t ₁ . In that time t ₂ immediately after, 0V is applied to also be the row select line 12 'to the row select driver 50 row select lines 12. That is, row select driver 50 biases MIM devices 34 and 36 at time t ₂ by applying an operating potential of substantially equal magnitude and opposite polarity to the address line pair consisting of lines 12 and 12 ′. , Non-conducting state. MIM
Such biasing of devices 34 and 36 causes + 3V applied to electrode 42 of storage element 46 to extend from column address line 18 to storage element 46 and MI.
A storage element 46 via a current path passing through the M device 36.
To charge.

At time t ₃ , the storage element 46 is sufficiently charged to exceed the threshold voltage of the display liquid crystal material 44, and the row selection driver 50 sets the row selection line 12 to −1.
At 5V, the row select line 12 'is returned to + 15V, biasing diodes 34 and 36 into their conducting state.
In that time t ₄ immediately after, the column driver 52 terminates the output of the charging potential of + 3V, column address lines 18 is applied to -3 V. All storage elements in the row defined by the row select address line pair consisting of lines 12 and 12 'are charged in parallel so that as soon as these storage elements are charged, they are defined by row select lines 14 and 14'. The next row is selected by the row selection driver 50,
The MIM device connected between lines 14 and 14 'is preferably biased to its non-conducting state.
That is, while the storage elements in the row defined by the row select lines 12 and 12 'are being charged, the other row select lines select the operating potential that biases the MIM devices connected between the lines to their conducting state. Received from the driver 50. Thus, row select lines 14 and 16 receive -15V from row select driver 50 and row select lines 14 'and 16' receive + 15V when storage element 46 is charged.

According to a preferred example, the display liquid crystal material 44
Is a nematic liquid crystal material, so the direction of the potential applied to the material is preferably reversed in the subsequent frame. The MIM device pair associated with the storage element need only be biased to allow current to flow, and
It should be understood by those skilled in the art that the IM device pair establishes a common node voltage that is maintained at approximately 0V when the associated storage element is charged, which constitutes a basic advantage of the present invention.

3A-3E show a second set of waveforms showing how charge is stored in the storage element 46 of the pixel 22 and then held therein. That is, E of FIG. 3 shows the waveform of the signal emitted from the output C ₁ of the column driver 52, A of FIG. 3 shows the waveform of the signal emitted from the output R ₁ of the row selection driver 50, and FIG. Row selection driver 50 for B
3 shows the waveform of the signal emitted from the output R ₁ ′ of the same, the waveform of the signal emitted from the output R ₂ of the row selection driver 50 is shown in C of FIG. 3, and the output R of the row selection driver 50 is shown in D of FIG. ₂ shows a waveform of a signal emitted from ₂ '. Among the important features of this driving method is the use of a holding voltage that minimizes leakage during the frame time, and the voltage change at the end of the scan time is the difference between two Ms contained in one display pixel.
It is equal between IM devices and thus no voltage kickback from MIM devices occurs.

At time t ₀ , the row select driver 50 maintains the row select lines 12 and 12 'at their holding voltage, which is both -2V. From time _{t 0} to time _{t 1,} line 'row select address line pair consisting of, that is, the output _{R 1} and _{R 1'} 12 and 12 rows addressed by the applied selection voltage to the output _{R 1} and _{R 1} ' To be selected. The voltage applied to the output R ₁ by the row selection driver 50 at time t ₀ is 17V. The voltage applied to the output R ₁ ′ at time t ₀ is −13V.
By applying such a voltage, MIM devices 34 and 36 are biased into their conducting state. With the MIM devices 34 and 36 biased conductive,
If the charge is accumulated in the storage element 46, the charge is held in the element 46. Therefore, from the time t ₀ to the time t ₁ , the voltage changed from + 2V to −2V is applied to the column address line 18 from the output C ₁ . Thus, the storage element 46 is selected for the period up to the time point t _1, but the storage element 46 is selected.
If it is not desired to select the storage element 46 to hold the charge stored on or applied to the element 46, the voltage applied to the outputs R ₁ and R ₁ ′ must be removed. . This removal is accomplished by reducing the + 17V voltage applied to the output R ₁ to + 2V and at the same time increasing the −13V voltage applied to the output R ₁ ′ to + 2V. From this, the output R ₁
And R ₁ ′ by setting the holding voltage at the end of the scanning time such that the voltage changes with respect to the outputs R ₁ and R ₁ ′ at that time are equal (that is, both are 15 V). The capacitance kickbacks from 36 are equal to each other, ie cancel each other,
Therefore, it is clear that the kickback phenomenon is eliminated. During the remaining time that is the non-selection period, that is, at time t
_{From 1} to t ₆ , the outputs R ₁ and R ₁ ′ are maintained at their holding voltage which is 2V. As mentioned earlier, the hold voltage is applied to both scan lines to minimize the voltage across the two MIM devices during the frame time and thus the leakage of those devices.

At time t ₁ when the outputs R ₁ and R ₁ ′ are returned to their holding voltage, the storage element 46 is “turned off”,
The electric charge applied to the element 46 is held until the next row is selected. From time t ₁ to time t _2, the storage element of pixel 26 is addressed to store the charge applied from the output C ₁ of the column driver 52 via the column address line 18. As can be seen from FIGS. 3C and 3D, the voltage at the outputs R ₂ and R ₂ ′ is a holding voltage of 2V until time t ₁ . Since storage element of the pixel 26 is to be selected, the voltage -17V output _{R 2,} voltage + 13V is applied to the output _{R 2} '. These voltages are
The output from the output C ₁ of the column driver 52 to the column address line 18 is maintained for one frame time of + 2V so that the charge is stored in the storage element of the pixel 26. Pixel 2
At the time t ₂ when charge storage in the storage element of 6 is complete, the voltage applied to the outputs R ₂ and R ₂ ′ has to be removed. This removal changes the voltage of the output R ₂ from -17V to -2V.
The holding voltage of V is increased and the voltage of R ₂ 'is increased to + 13V at the same time.
To -2V holding voltage. From this fact, the holding voltages of the outputs R ₂ and R ₂ ′ are equal to each other, and further, the two MIs included in the pixel 26.
It can be seen that the voltage changes associated with the M device are + 15V and -15V at the end of this scan time, of equal magnitude, and therefore the voltage kickbacks from the MIM device cancel each other out. Using the driving method shown in FIGS. 3A to 3E, the waveform for driving the pixels of the active matrix liquid crystal display system is repeated every four selection scans. That is, after the fourth selection, the voltage of the output R ₁ is −2V.
Return to the holding voltage of. Thus, the same waveform as shown in FIG. 3A is repeated. Similarly, the repetition of the waveforms shown in B, C and D of FIG. 3 also begins after the fourth selected scan time for each row.

The drive method shown in FIGS. 3A-3E has several advantages over prior art drive methods. Among those advantages are, for example: (1) a holding voltage applied to both scan lines that minimizes the voltage across the two MIM devices during the frame time, and thus the leakage of these devices; (2) The video and LC polarities are alternated row by row to eliminate flicker and gray scale non-uniformities, and (3) the video signal amplitude is kept small to reduce crosstalk from columns. That, (4)
That the voltage changes at the end of the scan time of the paired output 1 and output 2 for a given row are equal to each other, so that the voltage kickbacks from the MIM devices contained in the pixel cancel each other, (5) the given row The drive levels of the output 1 and the output 2 which are paired in relation to each other are exactly the same, so that the degradation of the two MIM devices occurs in exactly the same way, and the center point voltage is not affected. Is difficult to eliminate, is not affected by the slight residual asymmetry in the IV characteristics of the MIM device, and (7) the averaged DC component does not appear in the column address line or the row select line, Thus, the passivation layer that occurs on these lines may be eliminated or its thickness may be reduced, and so on.

The curve 66 shown in FIG. 4 indicates that the MIM devices 34 and 36 of the pixel 22 shown in FIG.
6 shows dramatically the excellent behavior of the matrix according to the invention when biased non-conducting during the retention of the charge stored in 6. The curve 66 is, for example, the MIM device 34.
, Line 12 is maintained at -10V and storage element 4
6 is a current-voltage characteristic when the impedance of 6 is assumed to be 0Ω. As can be pointed out, when the voltage V _v is more positive than −10 V on line 23, the current through diode 34 is represented only by leakage current, which is usually very weak (eg diode conduction current). Has many orders of magnitude less than the value of). Curve 66 also represents the current-voltage characteristics of MIM device 34 when line 12 is maintained at + 10V and the impedance of storage element 46 is assumed to be 0Ω. If the voltage applied to element 46 has a positive value on line 12 of less than 10V, the current through diode 34 is still represented by a very weak leakage current. Such characteristics are substantially uniform in all MIM devices, so that the voltages applied to the storage element 46 are + 10V and -10.
Very little current flows out of the charge storage device 46 between V (or any other suitable voltage value), i.e. the system effectively retains the charge stored in the charge storage device 46.

For example, in a high resolution display system having a plurality of pixels, charging can theoretically take about 1 to 2 microseconds of charging time, which is normally sized as the active matrix element of each pixel. Much shorter than the charging time that can be achieved in a conventional transistor active matrix display in which thin film field effect transistors are used.

Although the invention has been described herein by its preferred examples, the scope of the invention is not limited by this description, but only by the claims.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of an example of an active matrix liquid crystal display system according to the present invention.

2A is an explanatory diagram showing the waveform of the signal provided at the output C ₁ of the column drivers of Figure 1.

2B is an explanatory diagram showing waveforms of row selecting signals emanating from the output R ₁ of the row selection driver of FIG.

2C is an explanatory diagram showing a waveform of a row selection signal emitted from an output R ₁ ′ of the row selection driver in FIG. 1. FIG.

[Figure 3] is an explanatory view showing a second set of signal waveforms, A is explanatory diagram showing the waveform of the row selecting signal generated from the output R ₁ of the row selection driver of FIG. 1, B is the row select driver of FIG. 1 2 is an explanatory view showing the waveform of the row selection signal emitted from the output R ₁ ′ of FIG. 1, C is an explanatory view showing the waveform of the row selection signal emitted from the output R ₂ of the row selection driver of FIG. 1, and D is the row selection of FIG. 3 is an explanatory diagram showing a waveform of a row selection signal emitted from an output R ₂ ′ of the driver, and E is an explanatory diagram showing a waveform of a signal emitted from an output C of the column driver of FIG. 1. FIG.

FIG. 4 is a graph showing current-voltage curves to further facilitate understanding of the operation of the device according to the invention and the method of the invention.

[Description of Reference Signs] 10 active matrix liquid crystal display system 12, 12 ', 14, 14', 16, 16 'row selection line 18, 20 column address line 22, 24, 26, 28, 30, 32 pixels 34, 36 MIM Device 38 Nodes 40, 42 Electrode 44 Liquid crystal material for display 46 Storage element 50 Row selection driver 52 Column driver

Claims (7)

[Claims] 1. An active matrix liquid crystal display system for rapidly accumulating and effectively storing charge in a selected one of a plurality of storage elements, the system comprising: A plurality of pairs of address lines parallel to each other and intersecting the pair of address lines at an angle and spaced apart from the pair of address lines to form a plurality of intersections with the pair of address lines. Coupled to a common node between a plurality of substantially parallel additional address lines and the pair of address lines coupled at the intersections, blocking current with low bias and being highly biased And a set of MIM devices of the type that provide low impedance to current flow, coupled between one of the common nodes and one of the additional column address lines. Each pixel element being coupled to a pair of address lines, the biasing of the MIM device to a low impedance state to facilitate charge storage in the pixel element coupled to the pair of address lines is substantially equal in magnitude and polarity. Means for providing opposite first operating potentials to the pair of address lines and a charge to be accumulated while the first operating potential is provided to the pair of address lines. Second means for providing a charging potential to the selected one of the additional address lines to provide a storage element. 2. The MIM device further provides a high impedance to current flow when highly biased, and the first means further stores in a storage element coupled to a pair of address lines. A second operating potential of substantially equal magnitude and opposite polarity to bias the MIM device to a second state to facilitate storage of the stored charge. The system of claim 1 including means for interposing. 3. A multi-layer device, wherein the MIM device comprises a first layer of transparent conductive oxide material and a layer of substantially insulating material overlying a layer of substantially insulating material. The system of claim 1, wherein: 4. The first layer is an oxide of indium tin and the layer of substantially insulating material is SiNx.
The system of claim 3, wherein the metallic material layer is chromium. 5. A method of operating an active matrix liquid crystal display system for rapidly accumulating and effectively storing charge in a selected one of a plurality of pixel elements in a matrix system. , The method provides a plurality of pairs of substantially parallel address lines, intersects the pair of address lines at an angle and forms a plurality of intersections with the pair of address lines, and Is a type that provides a plurality of substantially parallel additional address lines spaced apart from the pair and provides a low impedance to current flow when forward biased to a first on state. A set of MIM devices are serially coupled together to a common node between the columns of the address lines coupled at the intersections, with each screen between one of the common nodes and one of the additional address lines. Substantially equal magnitude and opposite polarities for biasing the threshold device into the first on-state to couple the elementary elements and facilitate the storage of charge in the storage elements coupled to the address lines. A first operating potential between the columns of address lines, and the additional address is applied while applying the first operating potential to the pair of address lines for accumulating charge in a selected storage element. A method comprising applying a charging potential to a selected one of the lines. 6. The MIM device is further of a type that provides a high impedance to current flow when reverse biased to an off state, and the method further comprises the steps of: coupling to a pair of address lines. To facilitate storage of charge stored in the storage element, a second operating potential of substantially equal magnitude and opposite polarity is biased to reverse bias the threshold device to a second off state. The method of claim 5 including the step of applying between pairs of address lines. 7. The step of applying the first operating potential comprises starting the application of the first operating potential after starting the application of the charging potential and before ending the application of the charging potential. 7. The method of claim 6 including terminating the application of an operating potential of 1.