JPH0572995A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the liquid crystal display device which can remove a switching noise without making the device large in size nor complex. CONSTITUTION:This device is equipped with a thin film transistor T11 whose source is connected to a picture element electrode, a gate line G1 and a data line Dr which control the thin film transistor T11, a bus line B1 provided between gate lines connected to a low power source potential VCSL, a storage capacitor CS11 provided between the bus line B1 and a liquid crystal layer LC11, parallel connected thin film transistors T1a and T1b which have their common drain connected to the storage capacitor body CS11 and also connected to a high power source potential VCSH through a resistance body R1, have the common source connected to a low power source potential VCSL and have their two gates connected to the bus line B1 connected to gate lines G1 and G2 adjoining to the bus line B1, and the resistance body R1 which is connected to the bus line B1 and also connected to the high power source potential VCSH.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, it relates to an active matrix type liquid crystal display device using a thin film transistor.

[0002]

2. Description of the Related Art Liquid crystal display devices are thin and lightweight, can be driven at low voltage, and can be easily colored. In recent years, they have been used in personal computers, word processors, etc. It is used as a display device. Above all, a so-called active matrix type liquid crystal display device, in which a thin film transistor is provided as a switching element for each pixel, has no deterioration in contrast, response, etc. even if the number of pixels is large.
Since it can display halftones, it is the most suitable system as a display device for full-color television and OA.

This active matrix type liquid crystal display device has a basic structure composed of two flat glass substrates (array substrate and counter substrate) and a liquid crystal layer sandwiched between these substrates. On one of the glass substrates, that is, the counter substrate, a color filter array corresponding to each pixel and transparent electrodes (counter electrodes) are formed. On the array substrate, transparent arrays arranged in a matrix are formed. A pixel electrode formed of an electrode and a thin film transistor in which a source electrode is connected to each pixel electrode are provided. The gate electrode of the thin film transistor is connected to the gate line provided in the X direction, and the drain electrode is connected to the data line provided in the direction orthogonal to the gate line.

In the liquid crystal display device constructed as described above,
By applying an electric signal to the gate line and the data line at a timing called a line-sequential system, a voltage corresponding to the display of each pixel electrode can be selectively applied. The orientation of the liquid crystal, that is, the light transmittance can be controlled by the potential difference between the counter electrode and the pixel electrode, which enables arbitrary display. For details, see T.W. P. Reference by Brody et al. (IEEE
Tvans on Select. Deu. Vol ED
-20, Nov. 1973, pp. 995-1001)
Are described in.

However, in such a liquid crystal display device, when the thin film transistor is controlled from the on state to the off state and from the off state to the on state due to the parasitic capacitance of the liquid crystal layer and the parasitic capacitance of the thin film transistor, Since non-linear switching noise is superimposed on the electrode potential,
There are problems that the display characteristics are deteriorated and the liquid crystal layer is deteriorated due to the DC component.

As a method of removing such switching noise, there is a compensation driving method. FIG. 5A is an equivalent circuit diagram showing the configuration of the main part of a liquid crystal display device for implementing this method, and FIG. 5B is an applied voltage waveform of the liquid crystal display device. In the figure, V _COM represents the counter electrode potential.

The characteristic of this liquid crystal display device is that compensation capacitors C ₁₁ , C ₂₁ , ... are inserted between the gate lines G ₁ , G ₂ , ... and the liquid crystal layers LC ₁₁ , LC ₂₁ ,. , And the gate lines G ₁ , G ₂ , ... As shown in FIG.
Pulse signals V _G1 , V _G2 , ... As a result, the gate pulse signal V _G1 ,
When V _G2 , ... Is applied to the respective gate lines G ₁ , G ₂ , ... And the thin film transistors T ₁₂ , T ₂₁ , ... Are sequentially turned on, for example, the pixel electrodes of the storage capacitor C _S12 are connected. The potential, that is, the pixel electrode potential V _S , temporarily drops at the trailing edge of the gate pulse signal V _G2 (from V _GS to −V _E ), but rises at the pulse signal V _G1 (from −V _E to 0).
At that time, since the voltage is applied through the compensation capacitor C ₁₂ , the potential V _S rises and is maintained at a predetermined level. For details, see K. Suzuki et al. ("Compe
nation Addressing for Sw
etchingDistortion in a-Si
TFT LCD ”, Processings 7 + h
IDRC, PP107-110, Sept. 198
7).

However, in such a compensation driving method, for example, the rise of the pulse signal V _G1 (0 to V _GS )
At that time, the voltage is superimposed as the switching noise N on the pixel electrode potential V _S via the compensation capacitor C ₁₂ . For this reason, there are problems that the removal of the DC component becomes insufficient, the reliability of the liquid crystal layer is lowered, and that low-frequency noise is generated in the liquid crystal layer to cause flicker and image sticking. FIG. 6 is an equivalent circuit diagram showing a configuration of a main part of a liquid crystal display device for explaining another compensation driving method.

The characteristic of this compensation driving method is that the bus lines B ₁ , B ₂ , ... Are provided, and the storage capacitor C is provided through these bus lines.
_The purpose is to apply a compensation pulse signal to _S11 , C _S12 , ... To cancel the switching noise. Since these compensation capacitors are not connected to the gate lines G ₁ , G ₂ , G ₃ , ...
Does not occur.

However, in such a method, the data
The number of output terminals of the driving IC 10 for the gate lines D ₁ , D ₂ , D ₃ , ... Is the same as that of the previous method, but the gate lines G ₁ , G ₂ , G
_3, ... the output terminal of the driving IC11 of the bus line B _1,
It is necessary to increase the number of B ₂ , ... And generate two kinds of voltages of a gate pulse and a compensation pulse. Therefore, the chip size of the driving IC 11 becomes large and complicated due to the increase in the number of terminals. Problems such as a decrease in reliability due to an increase in the number of mounting steps of the IC 11 and a sophistication of connection technology due to a narrow pitch occur.

[0011]

As described above, in the liquid crystal display device using the conventional thin film transistor as the switching element, the switching noise caused by the parasitic capacitance of the thin film transistor and the parasitic capacitance of the liquid crystal layer is removed by the compensation driving method. Although attempts have been made, there are problems that the removal of the DC component is insufficient, the gate line driving IC becomes large and complicated, and the reliability decreases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal display device capable of removing switching noise without increasing the size of the device.

[0013]

The essence of the present invention is to generate a compensating pulse signal by a circuit composed of a thin film transistor using a gate pulse signal.

In other words, in order to achieve the above object, the liquid crystal display device of the present invention has a liquid crystal layer in which the alignment of the liquid crystal is controlled by the potential of the pixel electrodes arranged in a matrix, and a source on the pixel electrodes. A thin film transistor as a connected switching element, a gate line connected to the gates of the thin film transistors in the same row, a data line connected to the drains of the thin film transistors in the same column, and a gate line. A bus line provided between and connected to the low potential power source, a storage capacitor provided between the bus line and the pixel electrode, and a common source provided on the bus line and having the low potential power source. And a common drain connected to the storage capacitor, two gates connected in parallel to a gate line adjacent to the bus line, and a thin film transistor connected in parallel. It is connected to the common drain of the thin film transistor, and the other end is provided with a resistor that is connected to the high-potential power supply.

[0015]

In the liquid crystal display device of the present invention, the two gates of the thin film transistors connected in parallel are adjacent to each other.
Since it is connected to the gate line, the potential of the common drain changes in synchronization with the gate pulse signal. The potential of the common drain can be adjusted by the voltage difference between the high potential power source and the low potential power source.

Therefore, the switching noise generated in synchronization with the gate pulse signal due to the parasitic capacitance between the gate and the source of the thin film transistor as the switching element is caused by the voltage between the high potential power source and the low potential power source. If the difference is adjusted and the potential of the common drain is set to a level capable of canceling the switching noise, it is removed. Further, since the compensation capacitor connected between the gate lines is not used, switching noise due to this does not occur.

Furthermore, since no extra wiring or circuit for controlling the gate of the commonly connected thin film transistors is required, the number of output terminals of the gate line driving IC increases and the device becomes large in size as in the prior art. , The problem of complication does not occur.

[0018]

Embodiments will be described below with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a main configuration of a liquid crystal display device according to an embodiment of the present invention.

This liquid crystal display device is roughly classified into a gate.
The thin film transistor T _XY (XY = 11, 12, ...) As a switching element provided at the intersection of the data line G _X and the data line D _X (X = 1, 2, ...) And the storage capacitor C _SXY ( S
XY = S11, S12, ...) and a pixel electrode, and a liquid crystal layer LC _XY (XY = 11, 12, 12, in which the liquid crystal orientation (light transmittance) is controlled by the potential of the pixel electrode of this pixel.
,) And a compensation pulse generation circuit PG _X (X = 1, 2, ...) For compensating the potential of the pixel electrode. In the figure, each liquid crystal layer LC _XY is connected to the counter electrode potential V _COM .

The compensating pulse generating circuit PG ₁ is composed of thin film transistors T _1a and T _1b and a resistor R ₁ which are connected in parallel. The resistance value of the resistor R ₁ is preferably sufficiently larger than the on resistance values of the thin film transistors T _1a and T _1b .

The gates of the thin film transistors T _1a and T _1b are connected to the gate lines G ₁ and G ₂ , respectively, the common source is connected to the low power supply potential V _CSL , and the common drain is connected to the bus line B ₁ . Are connected to the storage capacitors C _S11 , C _S12 , ... Through the resistor R ₁ and to the high power supply potential V _CSH .

Other Compensation Pulse Generation Circuit PG_X(X = 2
3 ...) is similarly configured. In this example,
Thin film transistor for switching and compensation pulse generator
N as the material of the active layer of the star and the material of the resistor⁺ Ammo
Rufus silicon is used.

In the liquid crystal display device constructed as described above,
As shown below, high power supply potential V _CSH , low power supply potential V _CSL
Switching noise can be removed by adjusting.

FIG. 2 is a diagram showing an applied voltage waveform of the liquid crystal display device. The gate line G ₁ has a pulse amplitude ΔV (= V _GH −
V _GL ), pulse width T _G , and pulse interval T _F of the gate pulse signal V _G1 . Where V _GH is the selection potential,
V _GL is a non-selection potential. When the potential of the gate pulse signal V _G1 becomes the selection potential V _GH , the thin film transistor T ₁₁ is turned on. As a result, since the voltage of the data line D ₁ is applied to the pixel electrode of the liquid crystal layer LC ₁₁ , the pixel electrode potential V
_p11 goes up from V _SL to V _SH . Next, when the potential of the gate pulse signal V _G1 changes from the selection potential V _GH to the non-selection potential V _GL , the switching noise ΔV _p is _added to the pixel electrode potential V _p11.
Are superimposed. This switching noise ΔV _p is expressed by the following equation. ΔV _p = C _GS · ΔV _G / (C _S + C _LC + C _GS ) where C _GS is the parasitic capacitance between the gate and the source of the thin film transistor T ₁₁ , C _S is the capacitance of the storage capacitor C _S11 , C _LC is the capacity of the liquid crystal layer LC ₁₁ .

On the other hand, since the compensation pulse generating circuit PG ₁ is also connected to the gate line G _1, when the potential of the gate pulse signal V _G1 becomes the selection potential V _GH , the thin film transistor T _1a is turned on and the bus T _1a is turned on. The potential V _CS1 of the line B ₁ becomes equal to the low potential power supply V _CSL . Therefore, the low potential power supply V _CSL is applied to the storage capacitor C _S11 . When the potential of the gate pulse signal V _G1 changes from the selection potential V _GH to the non-selection potential V _GL , the selection potential V _GH is applied to the _gate line G ₂ and the thin film transistor T _1b is turned on. Therefore, the potential V _CS1 bus line B ₁ represents remains low-potential power supply V _CSL, the storage capacitor element C _S11 the low-potential power supply V _CSL is applied. After that, the pulse signal V _G2 changes from the selection potential V _GH to the non-selection potential V _GH.
When changed to _GL , the thin film transistors T _1a and T _1b are turned off together, so that the high potential power supply V _CSH is applied to the storage capacitor C _S11 via the resistor R ₁ . As a result, the compensation pulse generation circuit PG ₁ applies the compensation pulse signal V _cp represented by the following equation to the pixel electrode potential V _p11 . V _cp = C _S · V _Z / (C _S + C _LC + C _GS ) Here, V _Z = V _CSH −V _CSL . Therefore, Δ
If V _p = V _cp , switching noise can be removed.

That is, the high power supply potential V _CSH and the low potential power supply V _CSL may be set so that V _Z = C _GS · ΔV _G / C _S. In this implementation, V _CSH is 6.0 [V], V _CSL
Is set to 2.5 [V], and the counter electrode potential V _COM is set to 6.0.
[V], an AC display signal (maximum amplitude is 5) of which the polarity is inverted for each frame centered on 6 [V] on the data line D _X.
[V]) is applied. In this embodiment, since the compensation capacitor connected to the gate line is not used unlike the conventional case, the switching noise N as shown in FIG. 4 does not occur. Similarly, other thin film transistors T _XY ( _XY =
12, 13, ...) Switching noise is also removed.

Further, since the thin film transistors T _Xa and T _{Xb and the} resistor R _X of the compensation pulse generating circuit PG _X can be formed in the same process as the thin film transistor T _{XY of the} switching element, the disadvantage that the number of manufacturing processes increases increases. Absent.

Further, since the same pulse signal as that of the thin film transistor T _{XY of the} switching element is applied to the thin film transistors T _Xa and T _Xb of the compensation pulse generating circuit PG _X , its reliability is about the same as that of the thin film transistor T _XY. is there.

The inventors of the present invention have found that the threshold voltage of the thin film transistors T _Xa and T _Xb can be maintained even if they are operated for a long time under the condition of 480 gate lines (duty ratio 1/500) and ΔV _G = 26 [V]. It was confirmed that the fluctuation ΔV _TH of _Δ was very small. For example, in continuous operation at 70 ° C. for 1000 hours, the ΔV _TH amount of the threshold voltage of the thin film transistor T _XY is 4.0 [V], while the thin film transistors T _Xa and T _Xa
It was found that the value of _Xb was 5.0 [V] or less, and was sufficiently practical.

Further, in this embodiment, the signal necessary for generating the compensation pulse signal can be generated only by the gate pulse signal without giving a large number of external control signals.
Due to the increase in the number of output terminals of the gate line driving IC as in the past, the chip size of the driving IC becomes large and complicated, and the reliability decreases due to the increase in the mounting process of the driving IC and the narrow pitch. There will be no problems such as sophistication of connection technology.

As described above, in this embodiment, switching is performed by the compensation pulse generating circuit which can be controlled only by the gate pulse signal without increasing the number of manufacturing processes and without giving a large number of control signals from the outside. It is possible to remove noise, thereby preventing the reliability of the liquid crystal layer from being deteriorated by the DC voltage and preventing flicker and image sticking due to low frequency noise.

In this embodiment, the resistor R _X is n ^+. It was made of amorphous silicon, but other materials such as
A gate wiring material, a data wiring material, a transparent electrode material, a thin film transistor, etc. may be used. However, even in this case,
It is desirable that the resistance value of the resistor R _X be sufficiently higher than the ON resistance values of the thin film transistors T _Xa and T _Xb . This is because when the thin film transistors T _Xa and T _Xb are on, it is necessary to suppress the potential rise of the low power supply potential V _CSL due to the high power supply potential V _CSH .

FIG. 3 is a schematic view of a main part of a liquid crystal display device using a thin film transistor as the resistor R _X. This is a view showing only a portion different from the liquid crystal display device of FIG. This differs from the liquid crystal display device of FIG. 1 in that the resistor R
₁ , R ₂ , ... Are thin film transistors TR ₁ , TR, respectively.
_It was replaced by ₂ , ... Here, the on-resistance of the thin film transistors TR _1a , TR _1b , ...
The resistance of the thin film transistors TR ₁ , TR ₂ , ... _Is made sufficiently smaller than the on resistance of R ₁ ,.
If it is increased by the threshold voltage V _{TH of} the bus line B when the thin film transistors TR _1a , TR _1b , ... _Are off.
A potential of V _CSH −V _TH is applied to ₁ , B ₂ , ..., And when the thin film transistors TR _1a , TR _1b , ... _{Are on,} V V _CSL is applied to the bus lines B ₁ , B ₂ ,.
The desired motion can be obtained. With such a configuration, all the elements can be formed by thin film transistors of the same process, no special process is added, and the magnitude relation of the resistance value can be determined by the pattern size, so that it can be manufactured with high yield. it can.

FIG. 4 is an equivalent circuit diagram showing a main configuration of a liquid crystal display device according to another embodiment of the present invention. The parts corresponding to those of the liquid crystal display device of FIG. 1 are designated by the same reference numerals as those of FIG. 1, and detailed description thereof will be omitted. The liquid crystal display device of this embodiment is different from that of the previous embodiment in that a thin film transistor is used as a resistor.

Thin film transistors T _1a and T ₁ connected in parallel
The common drain of _1b is the storage capacitor C as in the previous embodiment.
_S1Y (S1Y = S11, S12, ...) And the high power supply potential V through the thin film transistor T _1e.
Connected to _CSH . On the other hand, the thin film transistor T _1a ,
The common source of T _1b is connected to the low power supply potential V _CSL .

The gate of the thin film transistor T _1e is connected to the power supply potential V ₁ via the resistor R _1e and is connected to the power supply potential V ₂ via the thin film transistors T _1c and T _1d connected in parallel. ing. The resistance value of the resistor R _1e is preferably sufficiently higher than the on resistance values of the thin film transistors T _1c and T _1d . Similarly, another thin film transistor T _xa , T _xb (x = 2, 3, ...) Connected in parallel is also connected with a resistor made up of a thin film transistor.

Further, the high power supply potential V _CSH and the low potential power supply V
_{The CSL} is set as in the case of the previous embodiment. In this embodiment, the high power source potential V _CSH and the low potential power source V _CSL are set to 6 [V] and 2.5 [V], respectively, the gate pulse signal amplitude is 26 [V], and the counter electrode potential V _COM is 6 [V]. .0
[V] and the number of gate lines was 480. In the liquid crystal display device thus configured, switching noise can be eliminated by setting the power supply potentials V ₁ and V ₂ as follows.

When a selection potential is applied to the gate line G ₁ (gate line G ₂ ), the thin film transistors T _1a (T _1b ) and T _{1c are formed.}
Turns on. When the thin film transistor T _1c is turned on,
The power supply potential V ₂ is applied to the _gate of the thin film transistor T _1e . At this time, as in the previous embodiment, the low power supply potential _CSL
Need only be applied to the storage capacitor C _S11 . Therefore, the power supply potential V ₂ is set so that the thin film transistor T _1e does not turn on.

On the other hand, when a non-selection potential is applied to the gate lines G ₁ and G ₂ , the thin film transistors T _1a ,
T _1b , T _1c and T _1d are turned off. As a result, the resistor R _1e
The power supply potential V ₂ is applied to the _gate of the thin film transistor T _1e via the. At this time, it is necessary to apply the high power supply potential V _CSH to the storage capacitor C _S11 as in the previous embodiment.
Therefore, the power supply potential V ₁ is set so that the thin film transistor T _1e is turned on.

By setting the power supply potentials V ₁ and V ₂ as described above, when the potential of the gate line G ₂ changes from the selected potential to the non-selected potential, the storage capacitor C _S11 via the bus line B ₁
Since the same compensation pulse signal as in the previous embodiment can be applied to
Switching noise can be removed. In this embodiment, the power supply potential V ₁ is 12 [V] and the power supply potential V ₂ is 0.0 [V].

Further, in this embodiment, since the thin film transistor is used as the resistor, the rising and falling of the compensation pulse signal can be improved. This is because the ON resistance of the thin film transistor is small.

Also in this embodiment, since the thin film transistor of the compensating pulse generating circuit and the thin film transistor as the switching element can be driven by the same gate pulse signal, practically sufficient reliability can be obtained as in the previous embodiment. it can.

The thin film transistors T _1e , T _2e , ...
Is turned on most of the time, but its gate voltage is 12 [V] (= V ₂ ) and _source voltage (= V _CSH ) is 6.0 [V]. .Source voltage V
_GS has an extremely low value of 12-6.0 = 6.0 [V]. The variation amount ΔV _TH of the threshold voltage is V _GS ⁿ (N = 2
Since it is proportional to 3), the gate-source voltage V _GS is 6.
In the case of 0 [V], the film transistor T _XY is in the ON state.
Since the bias voltage is sufficiently smaller than the operating voltage of 25 [V], there is no practical problem even if it is used for a long time.

The inventors of the present invention have found that the threshold voltage variation Δ of the thin film transistor T _1e during the operation at 70 ° C. for 1000 hours.
When V _TH was examined, the value was as low as 3.0 [V], and it was confirmed that sufficient reliability was obtained.

In order to stabilize the operation, a capacitor is provided between the common drain of the thin film transistors T _XC and T _XD connected to the _gate of the thin film transistor T _Xe and the power supply potential V ₁ or the power supply potential V _2. It may be provided.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the compensation pulse to the bus lines B ₁ , B ₂ , ... Has two levels has been described, but this embodiment can be applied to the case of multiple levels of three levels or more. In this case, a plurality of compensation pulse generation circuits may be provided. It is also possible to generate an electrical signal other than the switching noise compensation pulse signal. Other,
Various modifications can be made without departing from the scope of the present invention.

[0047]

As described in detail above, according to the present invention, the parasitic capacitance of the liquid crystal layer, the capacitance of the storage capacitor, and the source of the thin film transistor as a switching element are not brought about without complicating or increasing the size of the device. -Since switching noise caused by parasitic capacitance between drains can be removed, a liquid crystal display device with high reliability and display performance can be obtained.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a main configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an applied voltage waveform of a liquid crystal display device.

FIG. 3 is an equivalent circuit diagram showing a main configuration of a liquid crystal display device when a thin film transistor is used instead of a resistor.

FIG. 4 is an equivalent circuit diagram showing a main configuration of a liquid crystal display device according to another embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a configuration of a main part of a conventional liquid crystal display device.

FIG. 6 is an equivalent circuit diagram showing a main part configuration of a conventional liquid crystal display device.

[Explanation of symbols]

T _1a , T _1b , T _1c , T _1e , T ₁₁ , T ₁₂ , T ₂₁ , T ₂₂ ... Thin film transistor, R ₁ , R ₂ , R _e1 , R _e2 ... Resistor, C
_S11 , C _S12 , C _S21 , C _S22 ... Storage capacitor, LC ₁₁ ,
LC ₁₂ , LC ₂₁ , LC ₂₂ ... Liquid crystal layer, V _COM ... Counter electrode potential, V _CSH ... High power supply potential, V _CSL ... Low potential power supply, V ₁ ,
V ₂ ... Power supply potential.

Claims (1)

[Claims] 1. A liquid crystal layer in which the orientation of liquid crystal is controlled by the potentials of pixel electrodes arranged in a matrix, a thin film transistor as a switching element having a source connected to the pixel electrode, and a thin film transistor of the thin film transistors in the same row. A gate line connected to the gate, a data line connected to the drains of the thin film transistors in the same column, a bus line provided between the gate lines and connected to a low potential power supply, A storage capacitor provided between a line and the pixel electrode; and a bus line, a common source connected to the low-potential power supply, and a common drain connected to the storage capacitor. The gates are connected in parallel to the gate lines adjacent to the bus lines and connected in parallel. One end is connected to the common drain of the thin film transistor and the other end is connected to the high drain. A liquid crystal display device, comprising: a resistor connected to a potential power source.