EP0729188A2 - Dispositif semi-conducteur avec transistors à effet de champ à junction - Google Patents

Dispositif semi-conducteur avec transistors à effet de champ à junction Download PDF

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Publication number
EP0729188A2
EP0729188A2 EP96102470A EP96102470A EP0729188A2 EP 0729188 A2 EP0729188 A2 EP 0729188A2 EP 96102470 A EP96102470 A EP 96102470A EP 96102470 A EP96102470 A EP 96102470A EP 0729188 A2 EP0729188 A2 EP 0729188A2
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Prior art keywords
layer
type
gate
diffusion layer
semiconductor
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EP96102470A
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German (de)
English (en)
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EP0729188A3 (fr
Inventor
Nobutaka Nagai
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

Definitions

  • the present invention relates to a semiconductor device having junction field effect transistors, and, more particularly, to a semiconductor device having junction field effect transistors, which can have the desired electric characteristics and do not affect other circuit elements on the same substrate.
  • Fig. 1A is a plan view showing the structure of a conventional junction field effect transistor (FET), and Fig. 1B is a cross-sectional view along the line IB-IB in Fig. 1A.
  • FET junction field effect transistor
  • An N type epitaxial layer 22 having a thickness of approximately 3 ⁇ m is grown on a P type semiconductor substrate 21.
  • a P + type insulative isolating layer 28 is selectively formed on the surface of the N type epitaxial layer 22 in such a way as to reach the P type semiconductor substrate 21. This insulative isolating layer 28 defines a device region 20 where a junction FET is to be formed.
  • N + type source diffusion layer 23, an N + type drain diffusion layer 24 and a P + type gate diffusion layer 25 are selectively formed on the N type epitaxial layer 22.
  • An insulating film 36 is formed on the N type epitaxial layer 22 and the insulative isolating layer 28.
  • a source contact hole 32, a drain contact hole 33 and a gate contact hole 34 are selectively formed in the insulating film 36 at the positions which match with the N + type source diffusion layer 23, N + type drain diffusion layer 24 and P + type gate diffusion layer 25.
  • a source electrode 29, a drain electrode 30 and a gate electrode 31 are respectively formed on the N + type source diffusion layer 23, N + type drain diffusion layer 24 and P + type gate diffusion layer 25 at those portions exposed by the contact holes 32, 33 and 34. Therefore, the source electrode 29, drain electrode 30 and gate electrode 31 are electrically connected to the N + type source diffusion layer 23, N + type drain diffusion layer 24 and P + type gate diffusion layer 25 via the contact holes 32, 33 and 34 formed in the insulating film 36.
  • N + type source diffusion layer 23 and N + type drain diffusion layer 24 are so determined as to satisfy the breakdown voltage (e.g., 10 V) that is demanded of this junction FET.
  • junction FET 20 when a DC voltage is applied to the source electrode 29 and drain electrode 30, a current flows between both electrodes 29 and 30 because those electrodes are electrically connected via the N type epitaxial layer 22.
  • a depletion layer region 27a on the side of the gate electrode 31 and a depletion layer region 27b on the side of the P type semiconductor substrate 21 expand by the field effect.
  • the width L of the N type channel region 26 becomes narrower, making it difficult for the current to flow.
  • the migration of electrons between the source electrode 29 and drain electrode 30 can be controlled by changing the level of the voltage to be applied to the gate electrode 31.
  • the depth of the P + type gate diffusion layer 25 formed between the N + type source diffusion layer 23 and the N + type drain diffusion layer 24 to isolate them from each other is an important factor for the performance of the junction FET 20. More specifically, as the P + type gate diffusion layer 25 becomes deeper, the width L of the N type channel region 26 becomes narrower and the current I DSS that flows when a constant voltage is applied between the source electrode 29 and the drain electrode 30 becomes smaller. When the voltage to be applied to the source electrode 29 and the drain electrode 30 is constant, the gate voltage V GS necessary to turn off the junction FET becomes smaller.
  • the width L of the N type channel region 26 also varies greatly by a variation in the thickness of the epitaxial layer 22. Because the uniformness of the thickness of the epitaxial layer 22 is poor, the electric characteristics of the device are significantly influenced by a change in film thickness.
  • the first prior art needs a step of checking the electric characteristics by a monitor device or the like during the fabrication of the junction FET and adjusting the depth of the gate diffusion layer 25 by a heat treatment or the like to provide the desired channel region width L.
  • the device manufacturing process suffers not only an increase in the number of steps but also the influence on the electric characteristics of other devices in the case of an LSI circuit on which those devices are simultaneously manufactured.
  • the impurity concentration of the P type silicon substrate 21 should be set as low as approximately 1 x 10 15 cm -3 to reduce the collector capacitances of the NPN bipolar transistors. This scheme can improve the operation speed of the device and the collector breakdown voltage.
  • the impurity concentration of the P type silicon substrate 21 is set low, it becomes difficult to increase the depletion layer region 27b to the desired range.
  • the impurity concentration of the P type silicon substrate 21 is lower than that of the N type epitaxial layer 22, so that the depletion layer formed by the PN junction between the P type silicon substrate 21 and the N type epitaxial layer 22 mainly expands toward the P type silicon substrate 21 and does not expand toward the N type epitaxial layer 22 much. Therefore, the mutual conductance (g m ) representing the amount of a change in drain current ( ⁇ I DS ) with respect to the amount of a change in gate voltage ( ⁇ V G ) becomes smaller. In other words, even if the gate voltage to be applied is changed greatly, there is a small change in drain current so that the current control efficiency becomes poor.
  • junction FET with another structure a junction FET with a vertical structure which has the source electrode and drain electrode formed on the top and back surfaces of a substrate is disclosed in, for example, Unexamined Japanese Patent Publication No. Sho 63-128769.
  • Fig. 2 is an exemplary cross-sectional view showing the structure of a junction FET with a vertical structure. This junction FET will be called "second prior art.”
  • a drain region 42 made of an N type semiconductor is formed on the entire back surface of an N type semiconductor substrate 41, and a plurality of grooves 47 are formed inward from the surface of the N type semiconductor substrate 41 at the depth not deep enough to reach the drain region 42.
  • a P type impurity is doped inside the N type semiconductor substrate 41 from all the grooves 47, forming P + type gate diffusion layers 44 in such a way as to surround the grooves 47.
  • N + type source diffusion layers 43 are formed on the top surface of the N type semiconductor substrate 41 between the P + type gate diffusion layers 44 in such a way as not to contact the individual P + type gate diffusion layers 44.
  • An insulating film 48 is formed on the N type semiconductor substrate 41, and gate electrode holes 48a and source electrode holes 48b are respectively formed in the insulating film 48 at the positions matching with the openings 47a of the individual grooves 47 and the N + type source diffusion layers 43.
  • all the grooves 47 are filled with gate electrodes 46 which slightly protrude from the surface of the insulating film 48.
  • Source electrodes 45 are formed on the source diffusion layers 43 which is exposed by the source electrode holes 48b. Like the gate electrodes 46, those source electrodes 45 slightly protrude from the surface of the insulating film 48. Therefore, the gate electrodes 46 are electrically connected to the P + type gate diffusion layers 44, and the source electrodes 45 to the N + type source diffusion layers 43.
  • the thus constituted junction FET has substantially the same operation as the first prior art except that the direction of the current flow differs from that of the first prior art.
  • a DC voltage is applied to the source electrodes 45 and the drain region 42, a current flows between the source electrodes 45 and the drain region 42 because they are electrically connected via the N type semiconductor substrate 41.
  • the minus gate voltage is applied to each gate electrode 46, the width of a channel region 49 between the adjoining gate electrodes 46 become narrower by the field effect, making it difficult for the current to flow.
  • the migration of electrons between the source electrodes 45 and drain region 42 can likewise be controlled by changing the level of the voltage to be applied to the gate electrodes 46.
  • the width of the channel region 49 between the adjoining gate electrodes 46 is not influenced by the film thickness of the N type semiconductor substrate 41, so that the electric characteristics can be improved.
  • the substrate potential varies when this junction FET is turned on or in an operation mode where a high current flows through the substrate 41.
  • circuit elements like NPN bipolar transistors besides the junction FET are formed on the same substrate, the NPN bipolar transistors or the like may malfunction.
  • this source diffusion layers 43 prevent the interval between the grooves 47 or the width of the channel region 49 from becoming narrower than a certain value, which is a design restriction. Further, when the depths of the grooves 47 become uneven, the lengths of the channel regions 49 in the depth direction of the grooves 47 also become uneven, thus causing a variation in the electric characteristics of the junction FET.
  • a semiconductor device having a junction FET comprises: a semiconductor layer of first conductivity type.
  • a source diffusion layer of first conductivity type is selectively formed on a surface of said semiconductor layer.
  • a drain diffusion layer of first conductivity type is selectively formed on said surface of said semiconductor layer, apart from said source diffusion layer in first direction.
  • a plurality of gate diffusion layers of a second conductivity type are formed between said source diffusion layer and said drain diffusion layer, apart from one another in a direction perpendicular to said first direction, with channel regions formed between said gate diffusion layers.
  • This semiconductor device further may have an insulating film formed on the semiconductor layer, the insulating film having first gate contact holes at positions matching with the gate diffusion layers; and a gate electrode film in contact with all of the gate diffusion layers via the first gate contact holes.
  • the source diffusion layer and drain diffusion layer may be so formed as to extend in a direction perpendicular to said first direction, and the gate diffusion layers may be so formed as to extend in said first direction.
  • the semiconductor layer may have a flat surface so that the source diffusion layer, drain diffusion layer and gate diffusion layers can be formed inward of said semiconductor layer from the surface thereof.
  • This semiconductor device may further have a semiconductor substrate of second conductivity type on which the semiconductor layer is formed by an epitaxial layer or a well region of first conductivity type.
  • the gate diffusion layers may be so formed as to reach the semiconductor substrate from the surface of the semiconductor layer.
  • an insulative isolating layer of second conductivity type may be formed inward of the semiconductor layer from the surface thereof in such a way as to surround the source diffusion layer, drain diffusion layer and gate diffusion layers.
  • the insulating film may have a second gate contact hole at a position matching with the insulative isolating layer, and the gate electrode film may be in contact with the insulative isolating layer via the second gate contact hole, thereby allowing channel region to be formed between the gate diffusion layer and the insulative isolating layer of second conductivity type.
  • the semiconductor device having a junction FET comprises: a semiconductor layer of first conductivity type.
  • a source diffusion layer of first conductivity type is selectively formed on a surface of the semiconductor layer.
  • a drain diffusion layer of first conductivity type is selectively formed on the surface of the semiconductor layer, apart from the source diffusion layer in first direction.
  • a gate diffusion layer of second conductivity type is formed between the source diffusion layer and the drain diffusion layer.
  • An insulative isolating layer of second conductivity type is so formed as to surround the source diffusion layer, drain diffusion layer and gate diffusion layers, with channel regions formed between the insulative isolating layer and the gate diffusion layer.
  • the width and shape or the like of the channel regions can easily be controlled, thereby providing a junction FET having the desired electric characteristics.
  • the channel width can be set freely in accordance with the desired characteristics.
  • the drain current is controlled only by the gate diffusion layers or the depletion layer extending from the gate diffusion layers and P + type insulative isolating layer, and the depletion layer extending from the substrate or the like at the bottom hardly affects the drain current. Even in the case where other circuit elements are formed on the same substrate, therefore, a predetermined high mutual conductance can be acquired irrespective of the impurity concentration of the substrate that is needed for the circuit elements.
  • the substrate potential does not vary by the ON current (drain current) that is produced when this junction FET is turned on, and the electric characteristics of the other circuit elements are not affected.
  • Fig. 3 is a plan view of an N channel junction FET according to the first embodiment of the present invention
  • Fig. 4 is an exemplary cross-sectional view along the line IV-IV in Fig. 3
  • Figs. 5A through 5C are cross-sectional views illustrating a step-by-step method of fabricating the N channel junction FET according to the first embodiment of this invention.
  • Fig. 5C is a cross-sectional view taken along the line VC-VC in Fig. 3.
  • an N - type epitaxial layer (semiconductor layer) 2 with an impurity concentration of, for example, 5 x 10 16 cm -3 is formed 2 ⁇ m thick on a P type semiconductor substrate 1 having an impurity concentration of, for example, 1 x 10 15 cm -3 .
  • a P type impurity is diffused from the surface of the N - type epitaxial layer 2 to reach the P type semiconductor substrate 1, thereby forming a P + type insulative isolating layer 8 having an impurity concentration of, for example, 5 x 11 19 cm -3 to define a device forming region 18.
  • a plurality of P + type gate diffusion layers 5 are formed in the device forming region 18. As shown in Figs.
  • the P + type gate diffusion layer 5 has a plate-like shape extending toward the P type semiconductor substrate from the surface of the N type epitaxial layer 2.
  • a plurality of such gate diffusion layers 5 are formed in parallel to and apart from each other.
  • the P + type insulative isolating layer 8 and the P + type gate diffusion layers 5 may be formed in separate steps so that they can have their own predetermined shapes and impurity concentrations. Thereafter, the entire surfaces of the device forming region 18 and the P + type insulative isolating layer 8 are covered with an insulating film 17.
  • a resist film (not shown) is formed on the insulating film 17 and openings are selectively formed in the resist film on those area which are apart from both ends of the gate diffusion layers 5 and with such a shape as to extend vertically with respect to the gate diffusion layers 5, as shown in Fig. 5B.
  • N type impurity ions are injected into the surface of the N - type epitaxial layer 2, and then an N + type source diffusion layer 3 and an N + type drain diffusion layer 4 are formed by thermal diffusion.
  • N + type source diffusion layer 3 and N + type drain diffusion layer 4 are apart from both ends of the P + type gate diffusion layers 5 at predetermined distances, respectively, and are separated from the P + type insulative isolating layer 8 and the P type single crystalline silicon substrate 1 at predetermined distances, so that the desired characteristics of breakdown voltage are acquired. Then, the resist film and the insulating film 17 are removed and an insulating film 16 is again formed on the N - type epitaxial layer 2 and P + type insulative isolating layer 8, etc.
  • a source contact hole 12, a drain contact hole 13 and first gate contact holes 14 are formed in the insulating film 16 at the positions matching with the source diffusion layer 3, drain diffusion layer 4 and gate diffusion layers 5, as shown in Fig. 5C.
  • a second gate contact hole 14a is formed in the insulating film 16 at the position matching with the P + type insulative isolating layer 8, in parallel to and in the same direction as the first gate contact holes 14, as shown in Figs. 3 and 4.
  • a source electrode 9 and a drain electrode 10 are respectively formed on the source diffusion layer 3 and drain diffusion layer 4, which have been exposed by the contact holes 12 and 13.
  • a gate electrode 11 is so formed as to entirely cover all of the first gate contact holes 14 and the second gate contact hole 14a. Accordingly, the gate electrode 11 is connected to the gate diffusion layers 5 via the first gate contact holes 14 and to the P + type insulative isolating layer 8 via the second gate contact hole 14a.
  • the long sides of three P + type gate diffusion layers 5 which extend in one direction are formed to be, for example, 4 ⁇ m, and those gate diffusion layers 5 are formed in parallel in a direction perpendicular to this one direction at predetermined distances therebetween. That is, there are four split channel regions 6 between the P + type gate diffusion layer 5 closest to the P + type insulative isolating layer 8 and this P + type insulative isolating layer 8 and between the individual P + type gate diffusion layers 5, respectively. Those channel regions 6 have the same width.
  • the depletion layer 7 in the channel region 6 expands from the P + type gate diffusion layers 5 and P + type insulative isolating layer 8 to control the drain current as shown in Fig. 4. While the depletion layer 7 also expands from the P type semiconductor substrate 1 in this embodiment, this depletion layer hardly affects the width of the channel region.
  • the depletion layer 7 which expands from the P + type gate diffusion layers 5 is dominant in the channel region located between the P + type gate diffusion layers 5, while the depletion layer 7 which expands from the P + type gate diffusion layer 5 and P + type insulative isolating layer is dominant in the channel region located between the P + type gate diffusion layer 5 and P + type insulative isolating layer 8.
  • the drain current is determined by the diffusion resistance of the epitaxial layer, whereas when a positive voltage is applied to the source electrode, the channel region 6 is filled with the depletion layer 7, stopping the further flow of the drain current.
  • the voltage (V GS (off)) by which the depletion layer fills the channel region to stop the current flow when a reverse bias voltage is applied between the source and gate is determined by the width of the channel region, and V GS (off) becomes higher as that width is greater.
  • Fig. 6 is a graph showing a change in V GS (off) with respect to the thickness of the epitaxial layer, with V GS taken on the vertical scale and the thickness of the epitaxial layer taken on the horizontal scale.
  • the characteristic of the semiconductor device of the first prior art is shown as a comparative example.
  • the size L of the semiconductor device in the depth direction becomes the width of the channel region, so that the width of the channel region depends on the thickness of the epitaxial layer, by which V GS (off) changes.
  • the distances between the P + type gate diffusion layers 5 and between the P + type gate diffusion layer 5 and the P + type insulative isolating layer 8 become the widths of the respective channel regions 6. Even if the thickness of the epitaxial layer 2 changes, therefore, the width of the channel region 6 does not change so that V GS (off) is hardly affected by the thickness of the epitaxial layer 2.
  • the conventional junction FET should live with such a degree of variation in the device characteristics.
  • a variation in the horizontal expansion of the gate diffusion layers 5 is approximately 5%, it is possible to provide a junction FET whose characteristics vary less than the conventional one.
  • the width of the channel region 6 between the gate diffusion layers 5 can be set freely in accordance with the desired characteristics. Further, the depletion layer 7 expanding from the gate diffusion layers 5 affects the channel region 6 most, and the depletion layer 7 expanding from the substrate 1 is substantially negligible, so that the desired mutual conductance can be acquired regardless of the impurity concentration of the substrate that is needed for other circuit elements.
  • the ON current of this junction FET does not affect the other circuit elements.
  • Fig. 7 is an exemplary cross-sectional view showing the structure of the second embodiment of this invention.
  • the second embodiment differs from the first embodiment only in that an N type well 102 is formed instead of the N type epitaxial layer 2 as a semiconductor layer, and the other portion of the second embodiment has the same structure as that of the first embodiment.
  • N type well 102 is formed instead of the N type epitaxial layer 2 as a semiconductor layer
  • the other portion of the second embodiment has the same structure as that of the first embodiment.
  • like or same reference numerals are given to those components in Fig. 7 which are the same as the corresponding components in Figs. 3 through 5.
  • an N type well (semiconductor layer) 102 is formed on the surface of a P type semiconductor substrate 101, and an N + type source diffusion layer 3, an N + type drain diffusion layer 4 and a P + type gate diffusion layer 5 are formed in the N type well 102, as shown in Fig. 7.
  • An insulating film 16 is formed on the top of those diffusion layers and contact holes 12, 13 and 14 are selectively formed therein.
  • a source electrode 9, a drain electrode 10 and a gate electrode 11 are respectively formed on the N + type source diffusion layer 3, N + type drain diffusion layer 4 and P + type gate diffusion layers 5 where exposed by the contact holes 12, 13 and 14.
  • the depletion layer likewise fills the channel region (not shown), so that the drain current can be controlled as per the first embodiment.
  • the substrate 1 or 101 is formed by P type single crystalline silicon, and the N - type epitaxial layer 2 or the N type well 102 can be made to an N type silicon epitaxial layer or N type silicon region.
  • the substrate, layers, regions and so forth may be formed of compound semiconductors, and the P type may be changed to the N type, or vice versa, to provide a P channel junction FET.
  • the P + type gate diffusion layers 5 is so formed as to reach the P type semiconductor substrate 1 by the direct diffusion from the flat top surface of the N type epitaxial layer 2.
  • the N type epitaxial layer 2 has a thickness of about 5 ⁇ m or greater, or when the width of the channel region 6 becomes narrower than the predetermined value by the horizontal diffusion of the P + type gate diffusion layers 5, however, the P + type gate diffusion layers 5 may be formed by forming a groove vertically from the flat top surface of the N type epitaxial layer 2 and diffusion a P type impurity from the sides and bottom of that groove.
  • the P + type gate diffusion layers 5 can be so formed as not to reach the P type single crystalline silicon substrate 1. In this case, it is necessary to make the thickness of N type epitaxial layer 2 directly under the P + type gate diffusion layers 5 significantly smaller than the width of the channel region 6 between the P + type gate diffusion layers 5 to prevent the thickness of the epitaxial layer 2 from affecting the electric characteristics.
  • a single P type gate diffusion layer may be formed in the N type device region defined by the P + type insulative isolating layer and an N type source diffusion layer and N type drain diffusion layer may be formed in the device regions on both sides of the P type gate diffusion layer to form a channel region between the insulative isolating layer and the gate diffusion layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP96102470A 1995-02-21 1996-02-19 Dispositif semi-conducteur avec transistors à effet de champ à junction Withdrawn EP0729188A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32175/95 1995-02-21
JP7032175A JP2713205B2 (ja) 1995-02-21 1995-02-21 半導体装置

Publications (2)

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EP0729188A2 true EP0729188A2 (fr) 1996-08-28
EP0729188A3 EP0729188A3 (fr) 1997-09-17

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EP (1) EP0729188A3 (fr)
JP (1) JP2713205B2 (fr)
KR (1) KR100232383B1 (fr)

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FR2818013A1 (fr) * 2000-12-13 2002-06-14 St Microelectronics Sa Transistor a effet de champ a jonction destine a former un limiteur de courant
WO2008021919A1 (fr) * 2006-08-10 2008-02-21 Dsm Solutions, Inc. Jfet intégrant une grille arrière dans du silicium sur isolant ou brut

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EP0981166A3 (fr) * 1998-08-17 2000-04-19 ELMOS Semiconductor AG Transistor JFET
JP3925253B2 (ja) * 2002-03-15 2007-06-06 住友電気工業株式会社 横型接合型電界効果トランジスタおよびその製造方法
JP4623923B2 (ja) * 2002-10-01 2011-02-02 三洋電機株式会社 接合型ｆｅｔおよびその製造方法
US7417270B2 (en) * 2004-06-23 2008-08-26 Texas Instruments Incorporated Distributed high voltage JFET
JP2007005395A (ja) * 2005-06-21 2007-01-11 Mitsubishi Electric Corp 薄膜トランジスタ
JP4963120B2 (ja) * 2006-02-14 2012-06-27 独立行政法人産業技術総合研究所 光電界効果トランジスタ，及びそれを用いた集積型フォトディテクタ
JP2008053534A (ja) 2006-08-25 2008-03-06 Sanyo Electric Co Ltd 接合型ｆｅｔおよびその製造方法
JP2008282878A (ja) * 2007-05-08 2008-11-20 Rohm Co Ltd 半導体装置およびその製造方法
JP5307991B2 (ja) 2007-07-27 2013-10-02 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP2009043923A (ja) 2007-08-08 2009-02-26 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5879694B2 (ja) * 2011-02-23 2016-03-08 ソニー株式会社 電界効果トランジスタ、半導体スイッチ回路、および通信機器
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor

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WO2008021919A1 (fr) * 2006-08-10 2008-02-21 Dsm Solutions, Inc. Jfet intégrant une grille arrière dans du silicium sur isolant ou brut
US7557393B2 (en) 2006-08-10 2009-07-07 Dsm Solutions, Inc. JFET with built in back gate in either SOI or bulk silicon
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KR960032771A (ko) 1996-09-17
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EP0729188A3 (fr) 1997-09-17
JPH08227900A (ja) 1996-09-03
US6020607A (en) 2000-02-01

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