EP0704551A1 - Procédé pour traiter un substrat dans une chambre de traitement sous vide - Google Patents

Procédé pour traiter un substrat dans une chambre de traitement sous vide Download PDF

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Publication number
EP0704551A1
EP0704551A1 EP95115168A EP95115168A EP0704551A1 EP 0704551 A1 EP0704551 A1 EP 0704551A1 EP 95115168 A EP95115168 A EP 95115168A EP 95115168 A EP95115168 A EP 95115168A EP 0704551 A1 EP0704551 A1 EP 0704551A1
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Prior art keywords
chamber
sih4
substrate
semiconductor wafer
vacuum processing
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German (de)
English (en)
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EP0704551B1 (fr
Inventor
Meng Chu Tseng
Mei Chang
Ramanujapuram A. Srinivas
Klaus-Dieter Rinnen
Moshe Eizenberg
Susan Telford
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
    • C23C16/4408—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber by purging residual gases from the reaction chamber or gas lines
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0209—Pretreatment of the material to be coated by heating
    • C23C16/0218—Pretreatment of the material to be coated by heating in a reactive atmosphere
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42—Silicides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/905—Cleaning of reaction chamber

Definitions

  • the present invention relates to an improved chemical vapor deposition process, such as a process for the deposition of tungsten silicide (WSi x ) from tungsten hexafluoride (WF6) and dichlorosilane (DCS).
  • WSi x tungsten silicide
  • WF6 tungsten hexafluoride
  • DCS dichlorosilane
  • Tungsten silicide (WSi x ) thin films have been deposited by low pressure chemical vapor deposition (LPCVD) onto semiconductor substrates using silane (SiH4) and tungsten hexafluoride (WF6) as the precursor gases.
  • LPCVD low pressure chemical vapor deposition
  • SiH4 silane
  • WF6 tungsten hexafluoride
  • the WSi x thin film is deposited onto a semiconductor wafer having a layer of silicon oxide beneath a polysilicon layer. The foregoing process, however, has proven less than completely satisfactory.
  • the deposited coating is not as conformal over stepped topographies as is desired.
  • films so deposited have a high residual fluorine content that adversely affects device performance. For example, when the wafer is exposed to elevated temperatures, e.g., about 850°C or higher, as during annealing, the excess fluoride ions migrate through the underlying polysilicon layer and into the underlying silicon oxide layer. The effective thickness of the silicon oxide layer thus appears to increase. This effective thickness increase in turn leads to an adverse change in electrical properties of semiconductor devices including such layers.
  • the substrate to be coated with tungsten silicide first is cleaned using a fluorine plasma scrub to remove native oxide from the polysilicon layer.
  • the cleaned substrate is then transferred into a substrate transfer chamber.
  • This transfer chamber has a nitrogen or argon atmosphere (subatmospheric) to prevent re-oxidation of the substrate, and contains a robot to transfer the substrate into a processing chamber, e.g., a tungsten deposition chamber, through a slit valve having an O-ring seal.
  • This CVD process has become the standard for depositing tungsten silicide from SiH4 and WF6.
  • the above problems of step coverage and residual fluorine using this deposition process have become critical limitations for future applications.
  • the DCS process described above typically includes a purge step employing DCS as the purge gas.
  • the present invention intends to overcome the abovementioned problems.
  • the object is solved by the method of independent claims 1, 5, 21, 25, 26, and 27 and further by the semiconductor wafer of independent claims 32,33,34,35,36,37,38,39 and 40 and further by a vacuum processing apparatus of independent claims 42 and 46.
  • the present invention provides a process including a novel silane (SiH4) purge step subsequent to deposition of WSi x on a substrate.
  • the present invention further provides a process including a novel SiH4 soak step prior to deposition of WSi x on a substrate.
  • a substrate such as a semiconductor wafer
  • a substrate is processed in a chamber of a vacuum processing apparatus by depositing a material on a surface of the substrate using a gas mixture, and purging the chamber of residual gases remaining from the depositing step by flowing SiH4 into the chamber.
  • WSi x is deposited on a surface of a semiconductor wafer using a mixture comprising WF6, dichlorosilane and a noble carrier gas, and the chamber is subsequently purged of residual WF6 and dichlorosilane by flowing SiH4 into the chamber.
  • an optional DCS partial purge is carried out after WSi x deposition and prior to the SiH4 purge.
  • SiH4 is employed to condition a vacuum processing chamber prior to a deposition process.
  • the SiH4 conditioning step can be employed independently of, or in combination with, the foregoing SiH4 purge step as part of a method for processing substrates in a vacuum deposition chamber.
  • semiconductor wafers processed according to the foregoing processes are also provided.
  • the wafers so produced are characterized by reduced variation in sheet resistance, and are further characterized by reduced film stress as deposited.
  • a vacuum processing apparatus comprising a chamber, means for depositing a material, such as WSi x , on a surface of a substrate disposed within the chamber, and means for purging the chamber with SiH4.
  • Preferred means for depositing the material on the substrate surface include a source of at least one reactive gas and means for introducing the reactive gas into the chamber.
  • the apparatus includes sources of WF6, DCS and a noble carrier gas, and means for combining the gases to form a reactive gas mixture.
  • Means for purging the chamber with SiH4 preferably include a source of SiH4 and means for introducing the SiH4 into the chamber.
  • Methods according to the invention can, if desired, be carried out employing conventional chemical vapor deposition (CVD) systems used to practice the known DCS processes, without the need for modifications to the vacuum deposition chamber.
  • CVD chemical vapor deposition
  • a method of the invention can be carried out using the apparatus provided by Applied Materials, Inc. as described by Chang et al. in U.S. application Serial No. 08/136,529.
  • the methods of the present invention are not to be considered to be confined in their application to the use of such apparatus.
  • the methods of the present invention may be carried out using a multichamber processing system rather than a single chamber processing system.
  • a CVD system 10 comprises deposition chamber 12, vacuum exhaust system 14, gas combining assembly generally indicated at 16, diffuser 18, wafer lift 20, baffle plate 22, lift fingers 24 and susceptor lift 26.
  • Heating means 32 maintains a uniform temperature during processing of the susceptor 30 and the substrate 28 mounted thereon.
  • the deposition or reaction zone 34 lies above the substrate.
  • heating means 32 is an external array of 1000 watt lamps directing collimated light through quartz window 36. Other known heating means can also be employed. A particularly useful heating means 32 comprises resistive heating means rather than lamps. When resistive heating means are employed, quartz window 36 can be omitted. Thus, use of resistive heating means obviates the need for periodic cleaning and/or replacement of the quartz window, with attendant maintenance and downtime expenses.
  • Gas combining assembly 16 can include a gas box or plenum and one or more valves for controlling the flow of the various process gases, including purge gases, carrier gases, reactive gases for deposition of WSi x or other materials, and cleaning gases such as NF3 for periodic chamber cleaning processes.
  • gas mixing assembly 16 may be omitted and all process gases delivered directly to chamber 12 via diffuser 18. This alternative may, however, result in greater non-uniformity and thus may be less preferred for certain applications.
  • FIG. 2 illustrates an exemplary gas combining assembly 16.
  • Feed lines 38 and 40 deliver process gases into plenum 42 and subsequently into chamber 12 via diffuser 18.
  • Feed lines 38 and 40 are linked by mixing lines 44 and 46, which in turn are joined by divert line 48.
  • Valves 50 and 52 are disposed between mixing lines 44 and 46 on feed lines 38 and 40, respectively.
  • Inlet mixing valves 54 and 56 are disposed on mixing line 44 as shown, and outlet mixing valves 58 and 60 are correspondingly disposed on mixing line 46.
  • Divert valve 62 is disposed on divert line 48.
  • Sources of process gases are connected to feed lines 38 and 40.
  • fluorine-containing gas sources are connected to one of feed lines 38 and 40, while silicon-containing gas sources are connected to the remaining feed line.
  • WF6 source 64 and NF3 cleaning gas source 66 are connected to feed line 38 via supply valves 68 and 70, respectively.
  • DCS source 72 and SiH4 source 74 similarly are connected to feed line 40 via supply valves 76 and 78, respectively.
  • Noble gas source 80 which preferably is a source of argon, is connected to feed lines 38 via supply valve 82.
  • valves 50 and 52 are open; all other valves are closed.
  • the deposition process begins with the entry of process gases (i.e., reaction and carrier gases) into the deposition chamber 12 via gas combining assembly 16 and "showerhead", type diffuser 18.
  • a conventional process mixture includes DCS, WF6 and argon.
  • Gas combining assembly 16 mixes the process gases upstream of diffuser 18, ensuring that the gas mixture is of uniform composition before being supplied to the diffuser 18.
  • the diffuser 18 has numerous openings over an area corresponding to that of the substrate 28 beneath it. The spacing between the diffuser 18 and the substrate 28 can be adjusted to from about 5-25 mm (200-1000 mils) to define the reaction zone 34.
  • the diffuser 18 feeds the combined process gases to the reaction zone 34.
  • the area of the chamber below the plane of the susceptor 30 is purged via bottom purge line 88 with a noble gas, preferably argon, to prevent reactive gases from extending into the area of the chamber 12 below the susceptor 30.
  • a noble gas preferably argon
  • the base pressure in the chamber is about 1.33 Pa (10 millitorr).
  • Exhaust system 14 is fitted with a throttle valve 86 which can regulate the pressure of the chamber.
  • a noble carrier gas e.g., argon
  • WF6 is introduced from source 64 into gas combining assembly 16 through feed line 38 by opening supply valve 68.
  • the WF6 preferably is introduced into gas combining assembly 16 together with the noble carrier gas, which is delivered from source 80 by opening supply valve 82.
  • Dichlorosilane from source 72 is introduced into gas combining assembly 16 through feed line 40 by opening supply valve 76.
  • the noble carrier gas preferred herein for reasons of economy is argon, but other noble gases can also be used.
  • nitrogen should not be used in accordance with the present process and should be excluded from the process.
  • Mixing of the process gases is effected in gas combining assembly 16 by closing valves 50 and 52 and outlet mixing valves 58 and 60, and opening inlet mixing valves 54 and 56 and divert valve 62.
  • the gases partially mix in mixing line 44, and initially flow through divert line 48 to exhaust system 14 until the flow is stabilized. After stabilization, divert valve 62 is closed and outlet mixing valves 58 and 60 are opened.
  • the partially mixed gases return through mixing line 44 to feed lines 38 and 40, then enter plenum 42 where mixing is completed.
  • the mixed process gases subsequently enter chamber 12 via diffuser 18.
  • the tungsten silicide deposition is generally carried out at from about 500-600°C, preferably at about 550°C.
  • the pressure during deposition can be from about 39.99-1333.2 Pa (0.3-10 torr), but preferably is carried out at about 93.33-199.98 Pa (0.7-1.5 torr).
  • the flowrates of process gases into chamber 12 are related to the volume of the chamber.
  • a typical chamber volume is about 6 L.
  • a semiconductor wafer having a diameter of 150mm (6") can also be processed in a chamber of this volume.
  • an appropriate flowrate of WF6 is about 1-6 sccm, preferably about 3.5 sccm.
  • Dichlorosilane is passed into chamber 12 at a flowrate of about 130-300 sccm, preferably at about 175 sccm.
  • Argon is used as the carrier gas and is passed into chamber 12 via line 38 at a flowrate of about 100-1000 sccm, preferably at 300-600 sccm.
  • This argon flowrate is exclusive of the bottom purge flowrate, about 100-500 sccm, preferably about 300 sccm.
  • the various flowrates are adjusted so as to obtain a WSi x layer having a resistivity of between 700 and 1400 ⁇ -cm, preferably about 800 ⁇ -cm. Deposition is most preferably carried out at 550°C and 133.32 Pa (1torr).
  • the optional DCS purge step is carried out by simply closing supply valve 68 to stop the flow of WF6 into the deposition chamber 12, while maintaining the previously established flow of DCS and argon into chamber 12.
  • the optional DCS purge is carried out for 0 to about 5 seconds, preferably about 2-3 seconds.
  • the DCS flowrate during this optional purge step is about 130 to 300 sccm, preferably about 175 sccm. Preferred temperatures are as indicated for the deposition step.
  • the optional DCS purge helps to remove any remaining WF6 from gas combining assembly 16. This ensures that WF6 does not come into contact with the subsequent flow of SiH4 in gas combining assembly 16.
  • the SiH4 purge, or "cap” step is carried out.
  • Supply valve 76 is closed, ending the flow of DCS from source 72 into chamber 12. If supply valve 68 was not previously closed to end the flow of WF6, it is closed at this time. All mixing valves 54, 56, 58 and 60 are closed, and both valves 50 and 52 are opened.
  • Supply valve 78 is opened, allowing SiH4 to flow from source 74.
  • Supply valve 82 preferably remains open, continuing the flow of argon from source 80. Argon preferably also continues to flow into deposition chamber 12 through bottom purge line 88.
  • SiH4 from SiH4 source 74 flows through feed line 40 and valve 52 into plenum 42 and thence into chamber 12. Direct flow of the SiH4 through valve 52 again helps to ensure that the SiH4 does not come into contact with, and react with, any WF6 which may remain in gas combining assembly 16.
  • plenum 42 of gas combining assembly 16 be maintained at a temperature between about 10°C and 15°C, in order to prevent the SiH4 from decomposing.
  • Preferred cooling means include a water jacket (not shown). Other cooling means may also be employed.
  • the SiH4 purge step is preferably carried out for a time from about 10 to 30 seconds, more preferably about 15 seconds.
  • the total flowrate of SiH4 into deposition chamber 12 is preferably about 100 to 500 sccm, more preferably about 300 sccm.
  • the total chamber pressure within deposition chamber 12 preferably is maintained at about 66.66-133.32 Pa (0.5 to 1.0 torr), more preferably about 93.33 Pa (0.7 torr).
  • the temperature during the SiH4 purge preferably is about 500-600°C, more preferably about 550°C. Preferably the temperature is approximately the same as the temperature at which the deposition step is carried out.
  • SiH4 Upon completion of the SiH4 purge step, SiH4 is removed from the deposition chamber 12, gas combining assembly 16 and feed lines 38 and 40. Valve 52 is closed, and mixing valve 56 and divert valve 62 are opened. DCS, preferably combined with argon, is passed through feed line 40 and out divert line 48 to exhaust system 14 for about 5 to 10 seconds, preferably about 5 seconds, to purge residual SiH4. DCS does not enter deposition chamber 12 during this step.
  • DCS preferably combined with argon
  • deposition chamber 12 Next, argon flow is maintained into deposition chamber 12 for about 5 to 10 seconds, preferably about 5 seconds, to remove residual SiH4 from the chamber. Finally, deposition chamber 12 and all reactive gas feed lines are pumped out to the base pressure of the pump employed (preferably about 0.6666-1.9998 Pa (5 to 15 millitorr)).
  • base pressure of the pump employed preferably about 0.6666-1.9998 Pa (5 to 15 millitorr).
  • chamber 12 may be cleaned any by conventional means, such as by a plasma cleaning process employing a gas such as NF3.
  • the cleaning gas may be supplied to chamber 12 from source 66 by opening supply valve 70, closing mixing valves 54 and 58, and flowing the cleaning gas through valve 50.
  • the cleaning gas may, if desired, be combined with a noble carrier gas in the usual manner.
  • SiH4 can be introduced into a chamber of a vacuum processing apparatus prior to deposition as well as subsequent to deposition.
  • This initial chamber conditioning step, or "silane soak" step, prior to the deposition step preferably is carried out by introducing SiH4 into deposition chamber 12 via line 40.
  • Valve 52 is opened, and all other valves remain closed.
  • an argon bottom purge is carried out simultaneously with the SiH4 step.
  • the argon flowrate preferably is about 100 to 500 sccm, more preferably about 300 sccm.
  • the SiH4 soak step preferably is carried out after the semiconductor substrate 28 is introduced into deposition chamber 12.
  • SiH4 is preferably introduced into deposition chamber 12 in combination with the same noble carrier gas, e.g. argon, used in carrying out the subsequent deposition and SiH4 purge steps.
  • the SiH4 soak step is preferably carried out for about 15 seconds to 1 minute, more preferably about 30 seconds.
  • the flowrate of SiH4 into deposition chamber 12 preferably is about 100 to 500 sccm, more preferably about 300 sccm, assuming a chamber volume of about 6 L.
  • Chamber pressure during the conditioning step is preferably about 133.32-1333.2 Pa (1 to 10 torr), more preferably about 266.64 Pa (2 torr).
  • Conditioning times will depend on both the SiH4 flowrate and the chamber pressure. Thus, 15 seconds is the preferred minimum time for a SiH4 flowrate of 500 sccm at a chamber pressure of 1333.2 Pa (10 torr). About 30 seconds is sufficient for a flowrate of 300 sccm at 266.64 Pa (2 torr).
  • the temperature during the conditioning step typically is the same employed for the deposition step, about 500-600°C, more preferably about 550°C. However, no minimum temperature is required for the conditioning step, since SiH4 readily decomposes even at room temperature (25°C).
  • the conditioning step can be carried out in combination with, or independent of, the SiH4 purge step.
  • the SiH4 may serve as a catalyst to initiate deposition, and also may add a thin polysilicon layer to the surface of the semiconductor wafer prior to the DCS deposition process. Carrying out a SiH4 soak step therefore is very preferred. However, when the DCS deposition process is carried out at an elevated temperature, for example above about 650°C, the SiH4 soak step may be omitted.
  • two 200 mm (8") semiconductor wafers were deposited with layers of WSi x .
  • the first wafer was processed according to a conventional silane method without a silane cap.
  • the second wafer was processed according to a DCS method with preceding SiH4 soak and subsequent SiH4 capping steps according to the present invention, as follows.
  • the wafer was introduced into a 6 L vacuum deposition chamber, and SiH4 (300 sccm) was introduced into the chamber together with argon (300 sccm) as carrier.
  • the bottom of the chamber was simultaneously purged with argon (300 sccm).
  • the SiH4 soak step was carried out for 30 sec at 266.64 Pa (2 torr).
  • the wafer was heated to 565°C in the chamber.
  • WF6 3.5 sccm
  • DCS 175 sccm
  • argon 600 sccm
  • the bottom of the chamber was purged with argon (300 sccm).
  • Chamber pressure was 106.65 Pa (0.8 torr).
  • WSi x deposition was carried out for 110 seconds.
  • a silane capping step was carried out for 15 seconds.
  • the total process time was 3 minutes.
  • Comparison of Figures 3 and 4 shows the unexpected improvement in film stress achieved according to the present invention.
  • the exemplary film produced according to the inventive process shows significantly lower stress than does a comparison film formed according to the previously known DCS process over a range of temperatures including the range (about 500-600°C) in which the deposition process typically is carried out.
  • WSi x films produced according to both the known and the inventive methods exhibit hysteresis in the stress measured during film annealing and subsequent cooling.
  • the stress as determined during heating is lower than the stress determined during cooling over the temperature range from about room temperature to about 600°C. Stress varied slightly between about 400° and 600°C.
  • the stress as determined during heating becomes higher than that determined during cooling at about 200°C, and remains higher up to at temperature of about 675°C.
  • the exemplary film of Figure 4 also differs from the comparison film of Figure 3 in that the film stress exhibits a negative value over a range of temperatures from about 400 to about 500°C. That is, the exemplary film exhibits compression rather than tension over the foregoing temperature range, while the comparison film always exhibits tension.
  • the exemplary film exhibits a local maximum in stress at about 600°C, similarly to the comparison film. However, in the exemplary film, the measured stress at this temperature is much lower than the stress in the comparison film. Furthermore, both the rate of change in stress and the total reduction in stress shown by the comparison film during heating in the temperature range above about 600°C are much greater than those shown by the exemplary film. That is, the exemplary film shows a much smoother transition in stress in this temperature range.
  • WSi x films are mixtures of two phases, hexagonal and tetragonal. During annealing, as the temperature is increased over the range from about 400°C to 700°C, the hexagonal phase transforms into the tetragonal phase. By about 900°C, the films are comprised substantially completely of the tetragonal phase. From this point, whether produced by conventional methods or methods according to the invention, WSi x films will behave similarly on cooling.
  • the reduction in stress shown by films produced in accordance with methods of the invention may be accomplished as follows.
  • the processed semiconductor wafers remain in the chamber while SiH4 purges the chamber.
  • SiH4 reacts with residual tungsten atoms present on the surface of the wafers, and with residual WF6, thus forming a silicon-rich WSi x layer having a thickness of approximately 0.1-0.2nm (1-2 ⁇ ) on top of the layer formed during the DCS deposition process (hence the alternate reference to the SiH4 purge step as a "cap" step).
  • the reaction adds silicon to the films at the grain boundaries of the films and fills pores in the films, thus releasing stress in the films. It is further believed that the SiH4 purge may actually result in a slight increase in sheet resistance.
  • Sheet resistance was measured in semiconductor wafers processed according to the conventional and inventive processes described in Example 1, above. The value of the sheet resistance was measured at 49 different sites over the surface of the wafers, and the average value and standard deviation of the measured values were calculated. The standard deviation is denoted herein as the "uniformity" of the sheet resistance. A high "uniformity" value thus indicates a large variation of sheet resistance from site to site over the surface of the wafer.
  • Figures 6A and 6B show the short-term drift in sheet resistance, measured in ⁇ /square ( ⁇ ), and uniformity ( ⁇ ) in %, over 25 wafers for the conventional process and the inventive process, respectively.
  • Sheet resistance as measured for the conventional process varied from 31 to 29 ⁇ /square, for a decrease of about 2 ⁇ /square (about 6.5%).
  • the sheet resistance varied from 44.4 to 44.6 ⁇ /square, within experimental error.
  • Uniformity for the conventional process varied from about 1.7% to 2.4%; for the inventive process, the variation was from about 1.83% to 1.75%.
  • the inventive process affords significantly reduced short-term downward drift in sheet resistance.
  • Figures 6C and 6D show corresponding long-term drifts in sheet resistance and uniformity over 500 wafers for the conventional process and the inventive process, respectively.
  • Sheet resistance was measured for the first wafer in each batch of 25 wafers. After 25 wafers were processes, the vacuum deposition chamber was cleaned, and the process was repeated for the next 25 wafers.
  • sheet resistance varied from 31 to 27 ⁇ /square, for a decrease of about 4 ⁇ /square (about 13%).
  • the sheet resistance varied from 44.5 to 43 ⁇ /square, for a decrease of about 1.5 ⁇ /square (about 3%).
  • Uniformity for the conventional process was observed to increase from about 2% to 3.5%; for the inventive process, the variation was from about 1% to 1.8%, with no trend upward or downward observed.
  • the inventive process thus affords significantly reduced long-term downward drift in sheet resistance as compared to the conventional process, as well as improved uniformity.
  • the conventional process required an upward adjustment of the pressure during deposition, to about 159.97 Pa (1.2 torr), in order to produce deposited films having acceptable sheet resistance. No such upward adjustment was required in the inventive process.
  • the invention has been illustrated primarily with reference to a DCS deposition process, the invention is not limited in its applicability to DCS processes or processes which deposit WSi x on a substrate.
  • the SiH4 conditioning and purge steps can be used with other deposition processes, particularly those which deposit a crystalline material on a substrate.
  • Such materials include, for example, TiSi x , CoSi x , TiCoSi x , etc.
  • Processing semiconductor wafers in accordance with the present invention results in a significant reduction in short- and long-term downward drift in sheet resistance, and enables production of more uniform wafers.
  • the present invention in addition results in processed semiconductor wafers having significantly reduced film stress.

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EP95115168A 1994-09-27 1995-09-26 Procédé pour traiter un substrat dans une chambre de traitement sous vide Expired - Lifetime EP0704551B1 (fr)

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EP0960435A1 (fr) * 1996-12-03 1999-12-01 Genus, Inc. Appareil et procedes permettant de reduire au maximum la contrainte lors du depot dans des films au siliciure de tungstene
EP0960435A4 (fr) * 1996-12-03 2001-12-19 Genus Inc Appareil et procedes permettant de reduire au maximum la contrainte lors du depot dans des films au siliciure de tungstene
EP0857795A1 (fr) * 1997-02-06 1998-08-12 Siemens Aktiengesellschaft Procédé pour le revêtement d'une surface
US6194314B1 (en) 1997-02-06 2001-02-27 Infineon Technologies Ag Process for chemical vapor deposition layer production on a semiconductor surface with absorbing protective gasses
KR100353210B1 (ko) * 1997-02-06 2002-10-19 지멘스 악티엔게젤샤프트 표면상의층제조방법
US6221771B1 (en) 1998-01-14 2001-04-24 Mitsubishi Denki Kabushiki Kaisha Method of forming tungsten silicide film, method of fabricating semiconductor devices and semiconductor manufactured thereby
WO2000070121A1 (fr) * 1999-05-19 2000-11-23 Applied Materials, Inc. IMPREGNATION ET PURGE AU SiH4 UTILISEES DANS DES PROCESSUS DE DEPOT
WO2001024238A1 (fr) * 1999-09-30 2001-04-05 Applied Materials Inc. Procede de formation de films de siliciure de tungstene et procede de fabrication de transistors metal-isolant-semi-conducteur
US7455884B2 (en) * 2002-03-05 2008-11-25 Micron Technology, Inc. Atomic layer deposition with point of use generated reactive gas species
WO2004007794A2 (fr) * 2002-07-12 2004-01-22 Applied Materials, Inc. Depot a nucleation pulsee de couches de tungstene
WO2004007794A3 (fr) * 2002-07-12 2004-04-29 Applied Materials Inc Depot a nucleation pulsee de couches de tungstene

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KR100214910B1 (ko) 1999-08-02
SG42803A1 (en) 1997-10-17
US6193813B1 (en) 2001-02-27
JP3990792B2 (ja) 2007-10-17
US5817576A (en) 1998-10-06
DE69518710D1 (de) 2000-10-12
JP3167100B2 (ja) 2001-05-14
KR960012331A (ko) 1996-04-20
DE69518710T2 (de) 2001-05-23
US5780360A (en) 1998-07-14
JPH08236464A (ja) 1996-09-13
JPH10212583A (ja) 1998-08-11

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