EP0647357A1 - Unhüllungsverfahren für halbleiterchips, daraus gewonnene teile und verwendung für die dreidimensionale verdrahtung. - Google Patents

Unhüllungsverfahren für halbleiterchips, daraus gewonnene teile und verwendung für die dreidimensionale verdrahtung.

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Publication number
EP0647357A1
EP0647357A1 EP94913654A EP94913654A EP0647357A1 EP 0647357 A1 EP0647357 A1 EP 0647357A1 EP 94913654 A EP94913654 A EP 94913654A EP 94913654 A EP94913654 A EP 94913654A EP 0647357 A1 EP0647357 A1 EP 0647357A1
Authority
EP
European Patent Office
Prior art keywords
pellets
conductors
pads
washer
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94913654A
Other languages
English (en)
French (fr)
Inventor
Christian Val
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of EP0647357A1 publication Critical patent/EP0647357A1/de
Withdrawn legal-status Critical Current

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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Definitions

  • the subject of the present invention is a method of encapsulating semiconductor wafers as well as the resulting device, each of the wafers containing for example an electronic component, an integrated circuit or a sensor. It also relates to the application of such encapsulation to the three-dimensional interconnection of these pellets.
  • the pellets are stacked after having been provided with connection wires oriented towards the lateral faces of the stack, then they are made integral with one another, for example using a resin; the interconnections of the pellets are then made on the faces of the stack.
  • the object of the present invention is to modify this process in particular to make it easier to integrate into a semiconductor factory and to reduce its cost.
  • cables are conductors, wires for example, directly on a semiconductor washer carrying a large number of pads; the washer being glued on an elastic film, the washer is sawn to individualize the pellets and then the film is stretched so as to spread the pellets; we then join all the pellets and the wires in an insulating material, polymerizable resin for example, then, after polishing, metallic deposits are produced above the wires so as to connect the latter to the sides of the pellets; the assembly is then cut so as to separate the pellets: we then obtain pellets encapsulated in a coating forming a housing, provided with connections.
  • FIG. 1 therefore represents an embodiment of the method according to the invention.
  • the first step, marked 10 consists in fixing (for example gluing), on an elastic film, a washer of semiconductor material (also known by the English name of "wafer"), in which a large number of pads (usually in the order of several hundred), each containing an integrated circuit or discrete component; the film is for example a self-adhesive polymer type.
  • the second step, marked 11, consists in wiring electrical conductors, wires or ribbons, on each of the connection pads of each of the pads contained in the washer.
  • FIG. 2 The result of these operations is illustrated in FIG. 2.
  • a semiconductor washer 1 has been shown in which a pad 21 has been identified.
  • the washer 1 is mounted on the elastic film, marked 2.
  • conductors 23, for example wires are connected vertically using the technique called "bail bonding" and consisting of melting the end of the wire 23 to obtain a small ball 24, facilitating its connection to the pad 22.
  • Other techniques can be used, as illustrated for example below in FIG. 7.
  • the wires 23 are each cut at a predetermined height, which can for example be 150 to 200 ⁇ m, for a wire diameter of about 25 to 30 ⁇ m, a thickness of washer of the order of 500 ⁇ m and of film 2 of the order of 200 ⁇ m, for example.
  • the next step (12, Figure 1) consists in sawing the washer 2 preferably over its entire thickness, so as to individualize the pellets such as 21.
  • the next step, marked 13, consists in uniformly stretching the elastic film (2); this has the effect of spreading the pellets (21) from each other and, this, regularly. It should be noted that the step 11 of wiring the wires on the washer (1) can, in an alternative embodiment, be carried out only after this step 13 of stretching the elastic film (2).
  • the next step, marked 14 consists of joining the pellets and their connection wires and coating the whole in an electrically insulating material, for example an organic resin, epoxy or polyimide, by a casting or molding technique for example, the the material then being, where appropriate, polymerized.
  • an electrically insulating material for example an organic resin, epoxy or polyimide
  • the next step, marked 15, consists in polishing the upper face (27, FIG. 3) of the coating material 25, so as to obtain a flat surface on which the sections of the wires 23 are flush.
  • the thickness of the coating material 25 depends on that of the washer 1 and of the materials concerned, in particular for thermo-mechanical reasons. For example, for a washer 400 to 500 ⁇ m thick, the material 25 can be approximately 150 ⁇ m.
  • the next step (16, Figure 1) is to remove the elastic film 2.
  • the rear face of the assembly, marked 28 in FIG. 3, is polished, that is to say the face opposite to face 27 to remove the film 2 and / or to thin the pellets 21 in order to reduce the thickness and size, which can be particularly advantageous in the application described below of stacking the pellets encapsulated in three dimensions.
  • the elastic film 2 is not removed, which then makes it possible to isolate and / or protect the rear face 28 of the patch.
  • the next step, marked 17, consists in making connections connecting each of the conductors 23 to what will become the lateral face of the pads after separation, these connections being made by metallizations on the upper face 27 above the inter-pad interval .
  • FIGS 4a and 4b illustrate this step, seen respectively in section and from above.
  • FIG. 4a represents the pellets 21 with their wires 23 embedded in the material 25.
  • the upper face 27 of the assembly carries metallizations 30 above the wires 23, metallizations which connect each of the wires 23 to the gap 26 between pads.
  • These metallizations can take different forms as illustrated in the top view of FIG. 4b: they can connect a wire 23 to the inter-pad area 26, connect two wires 23 of different pads together or further connect a wire 23 to an area 31, used later for testing the pellets for example.
  • connections 30 can be made by any known means, for example depositing a metal layer and subsequent etching of this layer.
  • the deposit can be a metallic deposit such as gold, nickel and gold, nickel-copper and gold, copper and gold, carried out for example under vacuum by cathodic sputtering, optionally recharged electrochemically.
  • the subsequent engraving may for example be a photoengraving.
  • a so-called reverse photoengraving that is to say leaving the metal everywhere except around the conductors, the latter making it possible in addition to produce electromagnetic shielding.
  • the last step in the production of the encapsulated pellets (step 18, in FIG. 1) consists in the separation of the pellets. This separation is carried out by cutting the material 25 between the pellets, for example using a diamond saw. Semiconductor wafers are then obtained, each coated on five of their faces in an insulating material forming a housing, the latter being provided with connections (metallizations 30), which can be tested and manipulated.
  • step 19, Figure 1 When we want to achieve with pellets thus encapsulated a three-dimensional stack (step 19, Figure 1), we have the boxes in a slide allowing to align two of the side faces of the boxes, thus simplifying the problems of relative positioning of the boxes . Between the housings are arranged layers of adhesive material, such as a polymerizable resin for example. Then the assembly is pressed and optionally it is polymerized, so as to secure it.
  • adhesive material such as a polymerizable resin for example
  • FIG. 5 where there are the pellets 21 and their coating material 25, separated from each other by an adhesive layer 32.
  • the film is used elastic 2, an adhesive material - or made adhesive by an appropriate treatment - which is left in place, thus avoiding the interposition of the layers 32.
  • On each of the end faces of the stack there is also a closing layer 42 non-adhesive, which is fixed by means of a layer 32.
  • the closure layers 42 can be adhesive on one of their faces, thus avoiding the layer 32.
  • the metallizations 30 connect each of the conductors 23 to the edge 35 of the stack.
  • the next step (20, FIG. 1) consists in interconnecting the various pellets of the stack and in connecting them, if necessary, to pads, called stack pads, allowing their connection to external circuits. These interconnections are made on the faces of the stack, for example as described in the aforementioned French patent application.
  • Figure 5 there is shown by way of example the different connections 30 all connected together using a metallization 33 disposed on the face of the stack and extending (34) for example on one or on both of the end faces of the stack. In the latter case, one of the faces can be used for the test while the other is used for mounting the stack on a printed circuit for example.
  • the cooling of the pellets in operation can be improved by the insertion of thermal drains between the housings, possibly connected to a radiator.
  • a heat sink 38 metallic layer for example, of copper or nitride aluminum, or even diamond, is placed between each pellet 21 by means of a layer of glue 36.
  • the left lateral face of the stack is for example glued, by means of a layer of glue 39, preferably thermally conductive, to a radiator 37, which is thus in thermal contact with the drains 38.
  • glue 39 preferably thermally conductive
  • step 11 of Figure 1 shows, in sectional view, an alternative embodiment of step 11 of Figure 1, namely the wiring of conductors on the washer.
  • the washer 1 mounted on its elastic film 2 and carrying pads 22, on which one wishes to wire conductors 23.
  • the upper face of the washer 1 is provided with pieces of substrate of the circuit type printed 39, preferably at least one per patch, the printed circuit 39 being fixed on the washer using for example a layer of glue 40.
  • the printed circuit 39 carries at least one metallization 41.
  • the conductor 23 is no longer cut but it is curved so as to be moreover connected to the metallization 41 carried by the printed circuit 39.
  • the conductor 23 can be connected vertically to the pad 22 as shown in the preceding figures or as shown in FIG. 7, connected horizontally as in metallization 41.
  • the method described above, as well as the devices obtained, have a certain number of advantages among which the fact that it is possible to process a large number of pellets simultaneously (all those which belong to the same washer) and, this , with techniques known in the semiconductor industry, easily integrated into a production line for semiconductor circuits, which considerably reduces the cost of the encapsulated chip and which makes it possible, by the techniques used, to obtain very small dimensions, in particular by the coating material, which can typically represent an increase in the area (of the pellet) of less than 1%.
  • the encapsulation mode is well suited to a "three-dimensional" stack, which can be carried out collectively and simply, with the cost advantages which result therefrom.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
EP94913654A 1993-04-27 1994-04-15 Unhüllungsverfahren für halbleiterchips, daraus gewonnene teile und verwendung für die dreidimensionale verdrahtung. Withdrawn EP0647357A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9304962 1993-04-27
FR9304962A FR2704690B1 (fr) 1993-04-27 1993-04-27 Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.
PCT/FR1994/000427 WO1994025987A1 (fr) 1993-04-27 1994-04-15 Procede d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procede et application a l'interconnexion de pastilles en trois dimensions

Publications (1)

Publication Number Publication Date
EP0647357A1 true EP0647357A1 (de) 1995-04-12

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EP94913654A Withdrawn EP0647357A1 (de) 1993-04-27 1994-04-15 Unhüllungsverfahren für halbleiterchips, daraus gewonnene teile und verwendung für die dreidimensionale verdrahtung.

Country Status (4)

Country Link
EP (1) EP0647357A1 (de)
JP (1) JPH07509104A (de)
FR (1) FR2704690B1 (de)
WO (1) WO1994025987A1 (de)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124354A (ja) * 1998-10-21 2000-04-28 Matsushita Electric Ind Co Ltd チップサイズパッケージ及びその製造方法
JP3235586B2 (ja) * 1999-02-25 2001-12-04 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP3065309B1 (ja) 1999-03-11 2000-07-17 沖電気工業株式会社 半導体装置の製造方法
AU6001599A (en) * 1999-10-01 2001-05-10 Hitachi Limited Semiconductor device and method of manufacture thereof
DE10023539B4 (de) * 2000-05-13 2009-04-09 Micronas Gmbh Verfahren zum Herstellen eines Bauteils
DE60115437T2 (de) * 2000-06-20 2006-07-27 Nanonexus, Inc., Fremont Testsystem von integrierten schaltungen
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
DE10137184B4 (de) 2001-07-31 2007-09-06 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil
DE10149689A1 (de) 2001-10-09 2003-04-10 Philips Corp Intellectual Pty Elektrisches oder elektronische Bauteil und Verfahren zum Herstellen desselben
KR100886292B1 (ko) * 2003-09-09 2009-03-04 산요덴키가부시키가이샤 회로 소자를 포함하는 반도체 모듈과 반도체 장치, 그들의 제조 방법 및 표시 장치
US7915085B2 (en) 2003-09-18 2011-03-29 Cree, Inc. Molded chip fabrication method
EP1668745B1 (de) * 2003-09-30 2011-08-31 International Business Machines Corporation Flexible baugruppe gestapelter chips
US20050104027A1 (en) * 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7217583B2 (en) 2004-09-21 2007-05-15 Cree, Inc. Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
EP1963743B1 (de) 2005-12-21 2016-09-07 Cree, Inc. Beleuchtungsvorrichtung
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US9159888B2 (en) * 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9024349B2 (en) * 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
JP5763924B2 (ja) 2008-03-12 2015-08-12 インヴェンサス・コーポレーション ダイアセンブリを電気的に相互接続して取り付けられたサポート
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
CN102067310B (zh) 2008-06-16 2013-08-21 泰塞拉公司 带有边缘触头的晶片级芯片规模封装的堆叠及其制造方法
US8461542B2 (en) 2008-09-08 2013-06-11 Koninklijke Philips Electronics N.V. Radiation detector with a stack of converter plates and interconnect layers
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
EP2406821A2 (de) 2009-03-13 2012-01-18 Tessera, Inc. Gestapelte mikroelektronische baugruppen mit sich durch bondkontaktstellen erstreckenden durchgangslöchern
KR101715426B1 (ko) 2009-06-26 2017-03-10 인벤사스 코포레이션 지그재그 구조로 적층된 다이용 전기 인터커넥트
WO2011056668A2 (en) 2009-10-27 2011-05-12 Vertical Circuits, Inc. Selective die electrical insulation additive process
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
WO2018100005A1 (en) * 2016-12-01 2018-06-07 Ecole Polytechnique Federale De Lausanne (Epfl) Engineering reversible elasticity in ductile or brittle thin films and products resulting from said engineering
US10615057B1 (en) 2018-12-11 2020-04-07 Northrop Grumman Systems Corporation Encapsulation process for semiconductor devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257119B1 (de) * 1986-08-22 1991-02-20 Ibm Deutschland Gmbh Integriertes Verdrahtungssystem für sehr hochintegrierte Schaltungen
US5098305A (en) * 1987-05-21 1992-03-24 Cray Research, Inc. Memory metal electrical connector
DE3719742A1 (de) * 1987-06-12 1988-12-29 Siemens Ag Anordnung und verfahren zur ordnungserhaltenden vereinzelung der in einem wafer enthaltenen halbleiterchips
FR2645681B1 (fr) * 1989-04-07 1994-04-08 Thomson Csf Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication
WO1991000619A1 (en) * 1989-06-30 1991-01-10 Raychem Corporation Flying leads for integrated circuits
WO1992017901A1 (en) * 1991-03-27 1992-10-15 Integrated System Assemblies Corporation Multichip integrated circuit module and method of fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9425987A1 *

Also Published As

Publication number Publication date
FR2704690B1 (fr) 1995-06-23
WO1994025987A1 (fr) 1994-11-10
FR2704690A1 (fr) 1994-11-04
JPH07509104A (ja) 1995-10-05

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