WO2002047151A2 - Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree - Google Patents
Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree Download PDFInfo
- Publication number
- WO2002047151A2 WO2002047151A2 PCT/FR2001/003846 FR0103846W WO0247151A2 WO 2002047151 A2 WO2002047151 A2 WO 2002047151A2 FR 0103846 W FR0103846 W FR 0103846W WO 0247151 A2 WO0247151 A2 WO 0247151A2
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- wafer
- chip
- dielectric layer
- substrate
- pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
Definitions
- the invention relates to the field of handling wafers comprising a semiconductor material, for example comprising silicon, these wafers being commonly called "wafers".
- the "manipulation” covers all operations of maintaining, moving, transforming, storing, processing, or the like of the wafers and of the chips originating from these wafers, these operations being carried out with a view to the production of electronic devices.
- the invention relates to the manufacture of an electronic device intended to constitute, or to be inserted into, an intelligent portable object such as a smart card, electronic label or the like.
- Such a device is in embodiments an electronic module to be integrated into the body of the destination portable object.
- the electronic devices mentioned here comprise at least: an integrated circuit called a chip, a substrate on which the chip is transferred; a contact pad secured to the substrate electrically connected to an input / output interface; and connections electrically connecting contact pads on the chip to these contact pads.
- the input / output interface includes one or more elements such as ohmic terminal block, antenna, accumulator, control member such as button or keyboard, display, sensor such as biometric or the like.
- semiconductor tracks are engraved on a wafer, the latter being subsequently cut into individual chips.
- the manufacturing stages range from “raw” wafer where chips are still grouped together, until an electronic device is obtained.
- Such a vehicle or handle therefore acts as a rigid if ication assembly during the processing steps and / or transfers between these steps.
- a wafer is mounted on this handle by means of an adhesive degradable to ultraviolet rays.
- the wafer is then manipulated, the handle ensuring its rigidity, then cut together with its handle in order to produce chips, each of which is mounted on an individual portion of handle.
- the adhesive is finally degraded and the handle portions separated from their respective chip in order to carry each chip into an electronic device.
- the invention aims to improve the usual handles.
- a method according to the invention allows the production of an electronic device by dispensing with the step of separating the stiffening handle and the chip as well as the step of cleaning the chip before mounting.
- stiffening handle is a dielectric layer intended to be left in place on the chip, this being all the more advantageous insofar as the two stages mentioned are delicate and costly to carry out.
- this protective layer associated with the adhesive for fixing the chip on its substrate, provides sufficient protection to dispense with the operation commonly called “glob top” consisting in covering with an insulating material the chip fixed on the substrate and its connections.
- FIG. 1 is a side half-view in elevation section of a wafer and a solid dielectric layer according to the invention, before their mutual fixing;
- FIG. 2 is similar to Figure 1, the dielectric layer comprising perforated access recesses;
- - Figure 3 shows the elements of Figure 1 assembled and the perforation operation of the dielectric layer;
- - Figure 4 shows the elements of Figure 2 once fixed mutually;
- FIG. 5 is a sectional elevation view on the one hand (left) an assembly comprising the dielectric layer and a so-called thick wafer; and on the other hand (on the right) the same elements, the wafer having been thinned;
- FIG. 6 is a half-view in elevation section of an assembly of Figure 3 or 4 after an individualization operation consisting of cutting the wafer into individual chips;
- Figure 7 is a sectional elevation view similar to Figure 6 and showing an operation of removing a chip after cutting
- FIG. 8 is an elevational sectional view showing a chip fixed on a substrate
- Figure 9 shows the assembly of Figure 8 after a connection operation between the chip and the substrate, forming an electronic device according to the invention.
- FIG. 10 is a schematic representation of equipment for manufacturing electronic devices according to the invention.
- FIGS 8 and 9 show an electronic device 1 as targeted by the invention.
- This device 1 comprises a chip 2 fixed by bonding 3 to a substrate 4, a deposit of conductive material 5 connecting the pads 6 for connecting the chip 2 to the contact pad 7 of the substrate 4.
- the substrate 4 comprises on its free surface a contact interface, for example made of copper, (not shown) which, in if the device 1 is mounted in a smart card, are intended to be flush with the surface of the card.
- this electronic device 1 is intended to be inserted into a card body (see FIG. 10, step 25), thus forming a smart card.
- the substrate 4 may comprise, as an alternative to the contact pad 7, holes (commonly called “via”) for the direct connection of the connection pads 6 to an input / output interface.
- the device 1 is mounted in the intelligent portable object in question, and the contact pad of the substrate 4 is connected to an antenna thus allowing the sending and receiving electromagnetic signals.
- the chip 2 is conventionally formed of an etched silicon portion. It is integral with a dielectric layer 8 so as to form an assembly having sufficient rigidity pl> ur to be handled during the steps, described below, of the manufacture of the electronic device 1.
- the fabrication of a chip 2 is based on a semiconductor wafer 9, commonly called “wafer”, on which a plurality of semiconductor tracks have been previously etched at locations intended to form 2 unit chips after cutting.
- These semiconductor tracks include pads 6 intended for connection with elements external to the chip 2, in particular the components of the electronic device 1 a
- the wafer 9 has on its active face a passivation layer which is not shown: the dielectric layer 8 is applied to this passivation layer.
- a layer of dielectric material 8 is superimposed on the active face of the wafer 9 and the assembly of these elements is carried out definitively, for example by gluing.
- the dielectric layer 8 can be a dielectric polymer film, this film being unwound from a distribution reel to be secured to the wafer 9.
- This dielectric layer 8 is, for example, a film consisting of a polymer belonging to the family of poly imides, such as Kapton.
- the thickness of the film is at least equal to that of the wafer 9 after a thinning step (FIG. 5) described in more detail in the following description.
- the dielectric layer 8 can be a polymeric and initially viscous dielectric material, applied by screen printing.
- FIG. 3 represents the step subsequent to that of FIG. 1: a laser beam 10 is used to form projections 11 in the dielectric layer 8, facing the pads 6 for connecting the wafer 9.
- Figures 2 and 4 show a variant of the steps of Figures 1 and 3: the dielectric layer 8 comprises recesses 11 formed prior to attachment to the wafer 9 taking into account the arrangement of the pads 6 for connecting the wafer 9. The assembly of the dielectric layer 8 on the active face of the wafer 9 is carried out by aligning the recesses 11 on the pads 6.
- the recesses 11 formed in the dielectric layer 8 can be produced by laser drilling 10, as in the case of FIG. 3, but also by punching or any other known technique for removing material.
- the recesses 11 are formed during screen printing, for example by using a screen with a masking area to prevent the deposition of screen printing material on the connection pads 6.
- the dielectric layer is also made of polymeric and initially viscous dielectric material, such as ink or polymer adhesive, but is here applied by jet of material.
- a matrix of nozzles with a section of the order of 20 ⁇ m launches material 8 on the wafer 9, except at the location of the recesses 11. This is obtained by programming when projecting the jets.
- the material 8 applied can be an epoxy resin.
- the assembly obtained is a wafer 9 whose active face is covered by the dielectric layer 8, with the exception of connection pads 6.
- An implementation with the application of an initially viscous material by screen printing or ink jet provides, for example before sawing, a step of polymerization by thermal, photonic, chemical or the like.
- the dielectric layer 8 fixed to the wafer 9 gives it sufficient rigidity to prevent excessive bending or breakage, so that the wafer 9 can be handled from one station to another in a production line.
- the term "rigid” only refers here to this property or aptitude for handling; however in some applications the chip and / or the wafer have a certain flexibility.
- the deferred chip has an aptitude for elastic deformation, in particular for bending.
- the stiffened wafer 9 is thus gripable by any known means of wafer manipulation, such as a suction handle (not shown). It is in this way mounted on a thinning support 31 (see Figure 5).
- the wafer 9 subsequently undergoes a thinning operation represented in FIG. 5 and consisting in reducing its thickness by removing material using a thinning means 30.
- Figure 6 shows the next step in which the wafer 9 was mounted on a cutting support 12 and then cut.
- the cutting support 12, visible in section in FIG. 7, comprises a metal ring 13, of a diameter greater than the dimensions of the wafer 9, in which a film 14 of flexible material is stretched.
- the wafer 9 is mounted on the cutting support 12 in a removable manner, for example by using a degradable adhesive with ⁇ ⁇ x ultraviolet rays, the film 14 of flexible material being in this case permeable to such rays.
- This cutting support 12 constitutes an assembly for positioning the wafer at the cutting station.
- the cutting is carried out by any known means suitable for semiconductor materials, for example by sawing with a circular saw.
- Sawing is carried out by following the arrangement of the chips 2 engraved on the wafer 9 and has the purpose of transforming the wafer 9 into a plurality of these chips 2.
- FIG. 6 is a half view of a cutting support 12 holding unit chips 2 after cutting the wafer 9.
- the dielectric layer 8 being integral with the wafer 9, it is cut together with the latter, thus forming chips 2 provided with their individual stiffening handle 8.
- the chips 2 thus obtained are separated from their cutting support 12 by exposure to ultraviolet radiation.
- FIG. 7 illustrates the unloading of the chips 2.
- a pushing finger 15 deforms the cutting support 12 at the level of a chip which is simultaneously gripped by a handling instrument 16 such as a suction cup, a gripper with pliers or the like.
- the suction cup 16 is placed in position against the dielectric layer 8 and a vacuum is created so as to press the assembly formed by the dielectric layer 8 and the chip 2 against the suction cup 16.
- the chip 2 does not undergo the deteriorations caused by the manipulation, nor even the deteriorations due to the contact of the suction cup 16.
- FIGS 8 and 9 show the steps for mounting the electronic device 1 itself.
- the chip 2 is transferred onto a substrate 4 by joining them definitively by bonding, the chip 2 retaining its stiffening handle formed by the dielectric layer 8.
- the operation of fixing the chip 2 to the substrate 4 is called “carryover”.
- the glue 3 is applied to the rear face of the chip 2 and goes up on its lateral parts (called “edges").
- the adhesive 3 it is useful for the adhesive 3 to cover the entire surface of the edges of the chip 2 so as to electrically insulate them. Nevertheless, the glue 3 must not pollute the active face of the chip 2, this is why the dielectric layer 8, in addition to its function of permanent stiffening handle, forms barriers 17 for stopping the glue 3, allowing thus not to overflow on the active face.
- FIG. 9 shows the electronic device 1 in the final manufacturing phase, the connection between the pads 6 of the chip and the contact pad 7 of the substrate 4 having been made.
- overlap it is meant that the conductive material of the connection is in contact with the pad 6, the layer 8, the insulation of the edge of the chip 2, the substrate 4 and the pad 7. It is in fact deposited by “wire deposition” or by material jet, on these parts of the device 1.
- FIG. 10 schematically represents a manufacturing equipment 18 intended for producing electronic devices 1 for intelligent portable objects.
- This equipment 18 includes: - A station 20 for depositing a dielectric layer 8 forming a stiffening handle on a wafer 9;
- a station 21 for thinning the wafer 9 and mounting the wafer 9 on a cutting support 12; - A station 22 for cutting the wafer 9 into chips 2;
- a station 24 for depositing a conductive material 5 for connection between a chip 2 and the substrate 4 supporting it so as to form an electronic device 1.
- This equipment also includes a station 25 for mounting an electronic device 1 in an intelligent portable object, for example in a smart card 19.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002216182A AU2002216182A1 (en) | 2000-12-05 | 2001-12-05 | Method for making a semiconductor chip using an integrated rigidity layer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR00/15941 | 2000-12-05 | ||
FR0015941A FR2817656B1 (fr) | 2000-12-05 | 2000-12-05 | Isolation electrique de microcircuits regroupes avant collage unitaire |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2002047151A2 true WO2002047151A2 (fr) | 2002-06-13 |
WO2002047151A3 WO2002047151A3 (fr) | 2003-02-13 |
WO2002047151B1 WO2002047151B1 (fr) | 2004-02-26 |
Family
ID=8857387
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2001/003846 WO2002047151A2 (fr) | 2000-12-05 | 2001-12-05 | Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree |
PCT/FR2001/003834 WO2002047161A2 (fr) | 2000-12-05 | 2001-12-05 | Barriere anti debordement de colle fixation d'une puce semi-conductrice |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2001/003834 WO2002047161A2 (fr) | 2000-12-05 | 2001-12-05 | Barriere anti debordement de colle fixation d'une puce semi-conductrice |
Country Status (3)
Country | Link |
---|---|
AU (2) | AU2002216182A1 (fr) |
FR (1) | FR2817656B1 (fr) |
WO (2) | WO2002047151A2 (fr) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007096017A1 (fr) | 2006-02-20 | 2007-08-30 | Siemens Aktiengesellschaft | Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits |
EP1936677A3 (fr) * | 2006-12-22 | 2009-11-11 | TDK Corporation | Structure de câblage de carte de circuit imprimé et son procédé de fabrication |
EP2357875A1 (fr) * | 2010-02-16 | 2011-08-17 | Gemalto SA | Procédé pour fabriquer un boîtier électronique |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2845805B1 (fr) * | 2002-10-10 | 2005-06-03 | Gemplus Card Int | Adhesif d'encartage formant navette |
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JPS5760844A (en) * | 1980-09-30 | 1982-04-13 | Nec Corp | Semiconductor device |
US5144407A (en) * | 1989-07-03 | 1992-09-01 | General Electric Company | Semiconductor chip protection layer and protected chip |
JPH0521597A (ja) * | 1991-07-15 | 1993-01-29 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JPH0555278A (ja) * | 1991-08-23 | 1993-03-05 | Sony Corp | 半導体装置 |
US5753901A (en) * | 1995-06-12 | 1998-05-19 | Solaic | Chip for an electronic card coated with a layer of insulating material, and an electronic card including such a chip |
DE19845296A1 (de) * | 1998-09-03 | 2000-03-16 | Fraunhofer Ges Forschung | Verfahren zur Kontaktierung eines Schaltungschips |
FR2806189A1 (fr) * | 2000-03-10 | 2001-09-14 | Schlumberger Systems & Service | Circuit integre renforce et procede de renforcement de circuits integres |
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JPS535970A (en) * | 1976-07-07 | 1978-01-19 | Toshiba Corp | Semiconductor device |
JPS53120271A (en) * | 1977-03-29 | 1978-10-20 | Mitsubishi Electric Corp | Semiconductor device |
FR2779272B1 (fr) * | 1998-05-27 | 2001-10-12 | Gemplus Card Int | Procede de fabrication d'un micromodule et d'un support de memorisation comportant un tel micromodule |
FR2779851B1 (fr) * | 1998-06-12 | 2002-11-29 | Gemplus Card Int | Procede de fabrication d'une carte a circuit integre et carte obtenue |
FR2791471B1 (fr) * | 1999-03-22 | 2002-01-25 | Gemplus Card Int | Procede de fabrication de puces de circuits integres |
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2000
- 2000-12-05 FR FR0015941A patent/FR2817656B1/fr not_active Expired - Fee Related
-
2001
- 2001-12-05 WO PCT/FR2001/003846 patent/WO2002047151A2/fr not_active Application Discontinuation
- 2001-12-05 WO PCT/FR2001/003834 patent/WO2002047161A2/fr not_active Application Discontinuation
- 2001-12-05 AU AU2002216182A patent/AU2002216182A1/en not_active Abandoned
- 2001-12-05 AU AU2002216172A patent/AU2002216172A1/en not_active Abandoned
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JPS5760844A (en) * | 1980-09-30 | 1982-04-13 | Nec Corp | Semiconductor device |
US5144407A (en) * | 1989-07-03 | 1992-09-01 | General Electric Company | Semiconductor chip protection layer and protected chip |
JPH0521597A (ja) * | 1991-07-15 | 1993-01-29 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JPH0555278A (ja) * | 1991-08-23 | 1993-03-05 | Sony Corp | 半導体装置 |
US5753901A (en) * | 1995-06-12 | 1998-05-19 | Solaic | Chip for an electronic card coated with a layer of insulating material, and an electronic card including such a chip |
DE19845296A1 (de) * | 1998-09-03 | 2000-03-16 | Fraunhofer Ges Forschung | Verfahren zur Kontaktierung eines Schaltungschips |
FR2806189A1 (fr) * | 2000-03-10 | 2001-09-14 | Schlumberger Systems & Service | Circuit integre renforce et procede de renforcement de circuits integres |
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PATENT ABSTRACTS OF JAPAN vol. 006, no. 136 (E-120), 23 juillet 1982 (1982-07-23) -& JP 57 060844 A (NEC CORP), 13 avril 1982 (1982-04-13) * |
PATENT ABSTRACTS OF JAPAN vol. 017, no. 292 (E-1376), 4 juin 1993 (1993-06-04) -& JP 05 021597 A (OKI ELECTRIC IND CO LTD), 29 janvier 1993 (1993-01-29) * |
PATENT ABSTRACTS OF JAPAN vol. 017, no. 356 (E-1394), 6 juillet 1993 (1993-07-06) -& JP 05 055278 A (SONY CORP), 5 mars 1993 (1993-03-05) * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007096017A1 (fr) | 2006-02-20 | 2007-08-30 | Siemens Aktiengesellschaft | Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits |
US8191243B2 (en) | 2006-02-20 | 2012-06-05 | Siemens Aktiengesellschaft | Method for making contact with a contact surface on a substrate |
EP1936677A3 (fr) * | 2006-12-22 | 2009-11-11 | TDK Corporation | Structure de câblage de carte de circuit imprimé et son procédé de fabrication |
US8227710B2 (en) | 2006-12-22 | 2012-07-24 | Tdk Corporation | Wiring structure of printed wiring board and method for manufacturing the same |
EP2357875A1 (fr) * | 2010-02-16 | 2011-08-17 | Gemalto SA | Procédé pour fabriquer un boîtier électronique |
WO2011101359A1 (fr) * | 2010-02-16 | 2011-08-25 | Gemalto Sa | Procédé pour fabriquer un boîtier électronique |
CN102754535A (zh) * | 2010-02-16 | 2012-10-24 | 格马尔托股份有限公司 | 用于制造电子封装的方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2002047161A2 (fr) | 2002-06-13 |
FR2817656B1 (fr) | 2003-09-26 |
AU2002216182A1 (en) | 2002-06-18 |
FR2817656A1 (fr) | 2002-06-07 |
AU2002216172A1 (en) | 2002-06-18 |
WO2002047151B1 (fr) | 2004-02-26 |
WO2002047151A3 (fr) | 2003-02-13 |
WO2002047161A3 (fr) | 2003-04-24 |
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