WO2002047161A2 - Barriere anti debordement de colle fixation d'une puce semi-conductrice - Google Patents
Barriere anti debordement de colle fixation d'une puce semi-conductrice Download PDFInfo
- Publication number
- WO2002047161A2 WO2002047161A2 PCT/FR2001/003834 FR0103834W WO0247161A2 WO 2002047161 A2 WO2002047161 A2 WO 2002047161A2 FR 0103834 W FR0103834 W FR 0103834W WO 0247161 A2 WO0247161 A2 WO 0247161A2
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
Definitions
- the invention relates to the manufacture of electronic devices comprising at least one integrated circuit called "chip", fixed on a substrate. In this area, the invention relates to the isolation of chip wafers.
- the invention applies in particular to electronic devices forming or integrated into intelligent portable objects, such as smart cards, electronic labels or the like.
- a device is called a “module” if it is integrated into a body of the intelligent portable object.
- a chip it is made of a semiconductor material called core or "bulk" (sometimes mounted on an insulator): it is for example silicon.
- a chip has two opposite main faces, one called the active face covered by a passivation layer, with the exception of connection pads. The other side is called back. Between these two faces is a peripheral edge.
- the chip is transferred either with its rear face against the substrate and the connection pads of the active face opening out opposite the substrate. This report is called in English "die attach”.
- peripheral edge or even the rear face are conductive, in particular due to the so-called cutting operations
- this chip - and more broadly its electronic destination device - must often be provided with protection against external damage in particular, physico-chemical such as humidity, and mechanical such as impact or stress.
- This electrical and mechanical protection is carried out differently depending on the type of connection of the pads with contact pads to at least one input / output interface of the device.
- An input / output interface is, according to the embodiments, a terminal block with contact pads such as that of a bank chip card, a contactless transmission antenna, such as in an electronic label.
- Other input / output interfaces here include: control such as a power button or keyboard such as a accumulator or battery; visual display such as LED or screen; sound sensor or diffuser; measurement sensor, for example bio metric; data storage unit; etc.
- connection to interface elements is called wire wiring or "wire bonding".
- Document FR-A-2684802 describes such wiring, where the studs of the chip are connected to an interface by metallic wires. This connection is not targeted here.
- pads of a chip at the corresponding contact pads to at least one input / output interface uses electrically conductive polymer compounds instead of the soldered wires.
- connection pads and contact pads by deposition of a resin such as a polymerizable adhesive charged with conductive silver particles.
- Document JP-A-57060844 describes an individualized chip, with a thin layer of metal formed at its edge to prevent an electrode from being reached by a silicone coating covering a bevel of the heart. However, this layer is not intended to be then covered by a connection made by depositing a conductive substance ("wire deposition").
- Document FR-A-2779272 describes a chip mounted on contact pads and connected to these by conductive resin connections made by exemption. The glue does not rise on the flanks of the chip. On the other hand, the connections are in contact with these sides.
- Document JP-A-53120271 describes how to prevent a refrigerating agent from corroding the passivation layer by spreading a covering material up to the insulation strip including the electrode.
- Document FR-A-2779851 describes a chip mounted on contact pads and connected to these by a mass of conductive resin performed with a syringe. The glue does not rise on the flanks of the chip. On the other hand, the connections are in contact with these sides.
- Document JP53005970 describes how to prevent a surface protection agent from flowing inside a part to drown an electrode when it is applied to a semiconductor element of a mesa structure, by providing a annular wall at the circumference portion of the surface of a plate called "wafer”.
- the problem which the invention aims to solve is precisely to avoid short circuits between the connection by "wire deposition" and the edges of the chip: this is the function of an insulating barrier which is interposed between connection and edges.
- the insulation has an appropriate thickness (that is to say the distance between the substrate and the top of the protection, measured transversely to the faces of the chip).
- the target dimension for the adhesive thickness is for example of the order of 80% of the thickness of the chip (for example of 180 ⁇ m) with a tolerance of the order of +/- 10% of the thickness of the chip.
- the device While it is often desired that the device has flexibility properties in correspondence with those imposed on the portable object (card, label or the like) for which it is intended.
- the invention aims to overcome these drawbacks in particular. It aims to ensure that the conductive areas of the chip, and in particular its peripheral edges, are “fully” protected.
- the term "entirely” excludes the parts of the chip which it is necessary to be able to access, such as for example the connection pads. Apart from these zones, it is desired to achieve protection extended over substantially 100% of the conductive surface of the chip.
- the invention must allow the integration of the chip protection steps in an online and continuous manufacturing.
- the rate of the protection steps must therefore be close to that of the upstream and downstream steps, depending on the direction of the manufacturing process of the electronic device. This is not the case for example for wired cabling.
- an object of the invention relates to a method of manufacturing an electronic device, in particular an intelligent portable object such as a smart card, electronic label or the like.
- an intelligent portable object such as a smart card, electronic label or the like.
- Other objects of the invention relate to an electronic device and an intelligent portable object, for example a smart card, electronic label or the like.
- Yet another object of the invention relates to equipment such as an online and continuous production line for an electronic device.
- FIG. 1 shows in partial schematic section, on the one hand (top) a solid protective layer to be laminated, and on the other hand (bottom) a plate forming a substrate for chips.
- FIG. 2 is a view similar to FIG. 1, which represents on the one hand (top) a solid protective layer provided with access recesses, and on the other hand (bottom) a plate forming a substrate for chips, its connection pads being opposite the recesses.
- FIG. 3 shows in partial schematic section, a manufacturing step during which access recesses are formed in a solid protective layer laminated on a plate forming a substrate for chips.
- FIG. 4 shows in partial schematic section, a manufacturing step during which a layer of viscous protective material is deposited by screen printing or ink jet, on a plate forming a substrate for chips, access recesses being formed during the deposit in this layer.
- Figure 5 is a view similar to the previous ones, which illustrates a step of mounting a substrate plate for chips on its sawing vehicle.
- FIG. 6 is a view similar to FIG. 5, which illustrates the result of a step of sawing a substrate plate into chips, the latter remaining on the vehicle.
- FIG. 7 represents in schematic section, the result of a step of fixing a chip on its substrate, using a polymer adhesive.
- FIG. 8 represents in schematic section, the result of a step of connection of the studs of a chip on its substrate, by deposition of a polymer material on the fixing glue and a protective layer, in particular.
- FIG. 9 schematically represents an equipment for manufacturing portable devices and objects (here a smart card), with, depending on the direction of the process implemented by the equipment, stations for:
- FIG. 8 in particular, an electronic device 1 can be seen.
- This device 1 forms a module also designated in 1, for an intelligent portable object 2 such as the smart card shown in FIG. 9.
- the device 1 comprises at least:
- a chip 3 provided with at least:
- a dielectric substrate 8 on which the rear face 5 of the chip 3 is fixed, by bonding using a fixing material 9; contact pads 10 (or interface elements) to at least one input / output interface, electrically connected to the pads 7 by a conductive material 11.
- a protective structure of the device generally designated at 12 in FIG. 8 and comprising in particular a first electrically insulating material 13. More generally, all of the materials of the structure 12 are hereinafter called“ protective materials ”.
- the structure 12 comprises two protective materials, namely on the one hand the first material 13 which is in fact the fixing glue already mentioned.
- the structure 12 according to the invention comprises a second protective material 14.
- This same reference numeral 14 also designates a component of the structure 12 called “protective layer”.
- the second material 14 is applied before sawing (on the plate or “wafer”), but only on part of the active face 6, in contact with the adhesive 9 also serving as the first protective material 13. More specifically, here is a peripheral barrier 15 of the layer 14 (in particular visible in FIG. 7), which is in contact with the fixing and protection adhesive designated at 9 and 13 according to its function.
- the structure 12 is partly covered by the conductive material 11 ensuring the connection.
- the interface conductor which is covered by the drop of resin.
- an insulating part 16 of the active face 3, here of its passivation layer, is cleared, that is to say devoid of any protective layer and / or connection material
- the equipment 17 comprises one (or more): ⁇ application station 19 of a protective layer 14
- This equipment 17 has its station 19 for the unitary application of the insulating protective layer 14 on a wafer designated as 26 grouping together several chips, upstream of the mounting station 20, according to the direction 18 of the process.
- the equipment 17 While downstream of the transfer station 22 (here by bonding), the equipment 17 has a station 23 for depositing a material 11 conductor ensuring the connection of the chip 3 to the interface elements (here a terminal block for a smart card).
- such a process comprises the following chronological sequence of steps providing for: m mounting (as illustrated by arrow 20 in FIG. 5), on a sawing vehicle 25 a semiconductor plate called “wafer” 26, forming unitary substrate for several chips 3; “Sawing (as illustrated by the arrow 21 in FIG. 6) for example using a diamond tool such as a circular saw, each of the chips 3 to make them unitary, but keeping them integral and supported by the vehicle 25 ;
- the manufacturing process comprises in synthesis, according to the direction of unfolding 18, the steps providing:
- step 19 in FIG. 9 a dielectric layer 14 of protection on at least one active face 6 of chip 3 of this plate 26 ; "for at least one device 3, place it and then fix it (in step 22 in FIG. 9) on its substrate 8, by bonding its passive face 5, a periphery of the layer 14 forming the barrier 15 against the glue overflow (9-13) on the active face 6 of the chip 3; and
- step 19 during which the protective layer 14 is applied is carried out before the mounting 20 of the plate 26 on its vehicle 25.
- the chips 3 have on their active face 6 a passivation layer which is not shown: the protective layer 14 is applied to this passivation layer.
- the steps providing for applying at 19 the protective layer 14, placing then fixing at 22 the chip 3 on its substrate 8 and connecting it (23), are integrated into an online and continuous manufacturing process .
- the rate of these steps is close to that of manufacturing steps upstream and downstream, according to the direction of flow 18 of the process.
- the protective layer 14 is a dielectric polymer film, with a thickness for example of the order of 50 ⁇ m.
- This film is first unwound from a distribution reel 29 and then applied by lamination.
- FIG. 2 shows such a film, also designated at 14, through which access recesses 30 are reserved prior to lamination. Each obviously 30 opens once the layer 14 is applied to the plate 26 as illustrated in FIG. 4, opposite the connection pads 7.
- the recesses 30 are previously formed by laser cutting, mechanical cutting or stamping or similar, before re-reeling 29.
- FIG. 3 shows a protective layer 14 of polymeric dielectric film, also applied by so-called “lamination” lamination.
- This lamination provides for applying against the destination surface a sheet capable of becoming adherent under the effect of heat, by exerting on it a pressure (for example using pressure rollers). But here, the access recesses 30 are formed after lamination on the active face 6.
- a cutting tool is designated at 31 to form these recesses 30. According to the embodiments, this tool operates the cutting in the film 14 by laser, stamping or the like.
- the protective layer 14 is a polymeric and initially viscous dielectric material.
- layer 14 is applied by screen printing. Then, the recesses 30 are formed during screen printing, so that there is no protection at the desired locations.
- a screen with a masking area is used to prevent the deposition of screen printing material on the pads 7.
- This screen is not shown in the figures.
- the protective layer 14 is also made of a polymeric and initially viscous dielectric material, such as ink or polymer adhesive, but is here applied by jet of material.
- a matrix of nozzles with a section of the order of 20 ⁇ m launches material 14 on the face 6, except at the location of the recesses 30. This is obtained by programming during the projection of the jets.
- the face intended to form the active faces 6 of the plate 26 is "entirely" coated with the layer 14, except at the location of the recesses 30.
- An implementation with the application of an initially viscous material by screen printing or ink jet provides, for example before sawing 28, a step of polymerization by thermal input, photonic, chemical or the like. This step is shown diagrammatically in FIG. 4 at 32.
- the layer 14 has a barrier 15 (in this embodiment with a thickness of 70 ⁇ m), the external profile is substantially identical to - as well as to the right of - the peripheral section 4.
- the barrier 15 prevents the overflow inward of the adhesive 9/13 on the active face 6.
- the adhesive 9/13 flows upwards and against the slabs 4, during the step of fixing the chip 3.
- this adhesive 9/13 is an insulating polymer resin.
- this adhesive 9/13 is raised against the external peripheral edge 4 of the chip 3.
- the thickness of the adhesive 9/13 is between 80% and 100% of the thickness of the chip 3 such as of the order of 180 ⁇ m, with a tolerance of the order of +/- 10% the thickness of the chip 3.
- step 23 aimed at connecting the pads 7, is carried out by depositing conductive material 11 such as resin or polymer adhesive.
- conductive material 11 such as resin or polymer adhesive.
- Such an adhesive is either intrinsically electrically conductive, or it is charged with electrically conductive particles.
- this connection is made by pad printing, ink jet, syringe deposition or the like.
- connection material 11 is deposited on the fixing adhesive 9/13 and therefore on an external part of the dielectric protective layer 14.
- the peripheral barrier 15 is here locally covered by the connection inputs 11.
- the part 16 of the active face 6 and therefore of the passivation layer is devoid of this protective layer 14.
- the protection 12 is here a dielectric layer 14 having a peripheral barrier 15 which is at less partially covered by the conductive connection material 11, between the pad 7 and the electrically connected pad 10.
- the step 23 of connection after protection (19, 22) is carried out here by deposition of material (11) by jet of material and / or deposition with a syringe called "dispensation”, at different thickness levels called elevation on: the active face, edge, glue, barrier, substrate and contact pads. .
- connection contribution called boss (or "bump” in English) is deposited after fixing the chip 3 on its substrate 8. This contribution is often placed on the pads 7 and intended to receive a portion of end of the electrical connections 11 to the interface elements 10.
- the invention also covers intelligent portable objects 2 such as the card in FIG. 9. But other objects 2 also fall within its scope, such as electronic tags or other intelligent portable objects whose interface communicates with the exterior contactless.
- the invention allows the integration of the chip protection steps in online and continuous manufacturing, at a rate close to that of the upstream and downstream steps. It ensures optimal protection of the chip, with the techniques of fixing by gluing and connection by "exemption".
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002216172A AU2002216172A1 (en) | 2000-12-05 | 2001-12-05 | Barrier against overflow for fixing adhesive of a semiconductor chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR00/15941 | 2000-12-05 | ||
FR0015941A FR2817656B1 (fr) | 2000-12-05 | 2000-12-05 | Isolation electrique de microcircuits regroupes avant collage unitaire |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002047161A2 true WO2002047161A2 (fr) | 2002-06-13 |
WO2002047161A3 WO2002047161A3 (fr) | 2003-04-24 |
Family
ID=8857387
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2001/003834 WO2002047161A2 (fr) | 2000-12-05 | 2001-12-05 | Barriere anti debordement de colle fixation d'une puce semi-conductrice |
PCT/FR2001/003846 WO2002047151A2 (fr) | 2000-12-05 | 2001-12-05 | Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2001/003846 WO2002047151A2 (fr) | 2000-12-05 | 2001-12-05 | Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree |
Country Status (3)
Country | Link |
---|---|
AU (2) | AU2002216182A1 (fr) |
FR (1) | FR2817656B1 (fr) |
WO (2) | WO2002047161A2 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2845805B1 (fr) * | 2002-10-10 | 2005-06-03 | Gemplus Card Int | Adhesif d'encartage formant navette |
DE102006010523B3 (de) | 2006-02-20 | 2007-08-02 | Siemens Ag | Verfahren zur Herstellung von planaren Isolierschichten mit positionsgerechten Durchbrüchen mittels Laserschneiden und entsprechend hergestellte Vorrichtungen |
JP4303282B2 (ja) | 2006-12-22 | 2009-07-29 | Tdk株式会社 | プリント配線板の配線構造及びその形成方法 |
EP2357875A1 (fr) * | 2010-02-16 | 2011-08-17 | Gemalto SA | Procédé pour fabriquer un boîtier électronique |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS535970A (en) * | 1976-07-07 | 1978-01-19 | Toshiba Corp | Semiconductor device |
JPS53120271A (en) * | 1977-03-29 | 1978-10-20 | Mitsubishi Electric Corp | Semiconductor device |
JPS5760844A (en) * | 1980-09-30 | 1982-04-13 | Nec Corp | Semiconductor device |
US5144407A (en) * | 1989-07-03 | 1992-09-01 | General Electric Company | Semiconductor chip protection layer and protected chip |
FR2779272A1 (fr) * | 1998-05-27 | 1999-12-03 | Gemplus Card Int | Procede de fabrication d'un micromodule et d'un support de memorisation comportant un tel micromodule |
FR2779851A1 (fr) * | 1998-06-12 | 1999-12-17 | Gemplus Card Int | Procede de fabrication d'une carte a circuit integre et carte obtenue |
DE19845296A1 (de) * | 1998-09-03 | 2000-03-16 | Fraunhofer Ges Forschung | Verfahren zur Kontaktierung eines Schaltungschips |
FR2791471A1 (fr) * | 1999-03-22 | 2000-09-29 | Gemplus Card Int | Procede de fabrication de puces de circuits integres |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3212110B2 (ja) * | 1991-07-15 | 2001-09-25 | 沖電気工業株式会社 | 半導体素子の製造方法 |
JP3128878B2 (ja) * | 1991-08-23 | 2001-01-29 | ソニー株式会社 | 半導体装置 |
FR2735284B1 (fr) * | 1995-06-12 | 1997-08-29 | Solaic Sa | Puce pour carte electronique revetue d'une couche de matiere isolante et carte electronique comportant une telle puce |
FR2806189B1 (fr) * | 2000-03-10 | 2002-05-31 | Schlumberger Systems & Service | Circuit integre renforce et procede de renforcement de circuits integres |
-
2000
- 2000-12-05 FR FR0015941A patent/FR2817656B1/fr not_active Expired - Fee Related
-
2001
- 2001-12-05 WO PCT/FR2001/003834 patent/WO2002047161A2/fr not_active Application Discontinuation
- 2001-12-05 AU AU2002216182A patent/AU2002216182A1/en not_active Abandoned
- 2001-12-05 WO PCT/FR2001/003846 patent/WO2002047151A2/fr not_active Application Discontinuation
- 2001-12-05 AU AU2002216172A patent/AU2002216172A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS535970A (en) * | 1976-07-07 | 1978-01-19 | Toshiba Corp | Semiconductor device |
JPS53120271A (en) * | 1977-03-29 | 1978-10-20 | Mitsubishi Electric Corp | Semiconductor device |
JPS5760844A (en) * | 1980-09-30 | 1982-04-13 | Nec Corp | Semiconductor device |
US5144407A (en) * | 1989-07-03 | 1992-09-01 | General Electric Company | Semiconductor chip protection layer and protected chip |
FR2779272A1 (fr) * | 1998-05-27 | 1999-12-03 | Gemplus Card Int | Procede de fabrication d'un micromodule et d'un support de memorisation comportant un tel micromodule |
FR2779851A1 (fr) * | 1998-06-12 | 1999-12-17 | Gemplus Card Int | Procede de fabrication d'une carte a circuit integre et carte obtenue |
DE19845296A1 (de) * | 1998-09-03 | 2000-03-16 | Fraunhofer Ges Forschung | Verfahren zur Kontaktierung eines Schaltungschips |
FR2791471A1 (fr) * | 1999-03-22 | 2000-09-29 | Gemplus Card Int | Procede de fabrication de puces de circuits integres |
Non-Patent Citations (3)
Title |
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PATENT ABSTRACTS OF JAPAN vol. 002, no. 040 (E-022), 16 mars 1978 (1978-03-16) & JP 53 005970 A (TOSHIBA CORP), 19 janvier 1978 (1978-01-19) * |
PATENT ABSTRACTS OF JAPAN vol. 002, no. 150 (E-078), 15 décembre 1978 (1978-12-15) & JP 53 120271 A (MITSUBISHI ELECTRIC CORP), 20 octobre 1978 (1978-10-20) * |
PATENT ABSTRACTS OF JAPAN vol. 006, no. 136 (E-120), 23 juillet 1982 (1982-07-23) & JP 57 060844 A (NEC CORP), 13 avril 1982 (1982-04-13) * |
Also Published As
Publication number | Publication date |
---|---|
WO2002047151A3 (fr) | 2003-02-13 |
FR2817656B1 (fr) | 2003-09-26 |
WO2002047151A2 (fr) | 2002-06-13 |
AU2002216172A1 (en) | 2002-06-18 |
FR2817656A1 (fr) | 2002-06-07 |
WO2002047151B1 (fr) | 2004-02-26 |
AU2002216182A1 (en) | 2002-06-18 |
WO2002047161A3 (fr) | 2003-04-24 |
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