JPS5760844A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5760844A
JPS5760844A JP13628180A JP13628180A JPS5760844A JP S5760844 A JPS5760844 A JP S5760844A JP 13628180 A JP13628180 A JP 13628180A JP 13628180 A JP13628180 A JP 13628180A JP S5760844 A JPS5760844 A JP S5760844A
Authority
JP
Japan
Prior art keywords
electrode
metal
bevel
coated
protective agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13628180A
Other languages
Japanese (ja)
Inventor
Yukiyasu Usunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13628180A priority Critical patent/JPS5760844A/en
Publication of JPS5760844A publication Critical patent/JPS5760844A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the surface from adhering too much due to overflow of a protective agent and enable thick coating, by providing a groove apart from a metal electrode on the surface around an element, for an element whose bevel-cut portion is coated with a protective agent. CONSTITUTION:An ohmic electrode 5 is provided on an element 4 where a substrate 1 is brazed to a heat compensator 3. A bevel surface 6 is coated with silicone rubber 7 and passivated after bevel-cutting and etching. A fine metal 8 made of the same metal as the electrode 5 is formed at the edge of the element 4 apart from the electrode 5. This makes the metal a stopper and keeps from reaching the electrode 5, while coating with silicone rubber. Therefore, the rubber 7 can be applied thickly, and insulating capability and workability are improved.
JP13628180A 1980-09-30 1980-09-30 Semiconductor device Pending JPS5760844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13628180A JPS5760844A (en) 1980-09-30 1980-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13628180A JPS5760844A (en) 1980-09-30 1980-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5760844A true JPS5760844A (en) 1982-04-13

Family

ID=15171509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13628180A Pending JPS5760844A (en) 1980-09-30 1980-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5760844A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
US6190947B1 (en) * 1997-09-15 2001-02-20 Zowie Technology Corporation Silicon semiconductor rectifier chips and manufacturing method thereof
FR2817656A1 (en) * 2000-12-05 2002-06-07 Gemplus Card Int ELECTRICAL INSULATION OF GROUPED MICROCIRCUITS BEFORE UNIT BONDING
FR2828333A1 (en) * 2000-06-23 2003-02-07 Gemplus Card Int Electrical insulation of chip wafers involves liquid phase deposition of an insulating silica layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535970A (en) * 1976-07-07 1978-01-19 Toshiba Corp Semiconductor device
JPS53120271A (en) * 1977-03-29 1978-10-20 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535970A (en) * 1976-07-07 1978-01-19 Toshiba Corp Semiconductor device
JPS53120271A (en) * 1977-03-29 1978-10-20 Mitsubishi Electric Corp Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
US6190947B1 (en) * 1997-09-15 2001-02-20 Zowie Technology Corporation Silicon semiconductor rectifier chips and manufacturing method thereof
FR2828333A1 (en) * 2000-06-23 2003-02-07 Gemplus Card Int Electrical insulation of chip wafers involves liquid phase deposition of an insulating silica layer
FR2817656A1 (en) * 2000-12-05 2002-06-07 Gemplus Card Int ELECTRICAL INSULATION OF GROUPED MICROCIRCUITS BEFORE UNIT BONDING
WO2002047151A2 (en) * 2000-12-05 2002-06-13 Gemplus Method for making a semiconductor chip using an integrated rigidity layer
WO2002047161A2 (en) * 2000-12-05 2002-06-13 Gemplus Barrier against overflow for fixing adhesive of a semiconductor chip
WO2002047151A3 (en) * 2000-12-05 2003-02-13 Gemplus Card Int Method for making a semiconductor chip using an integrated rigidity layer
WO2002047161A3 (en) * 2000-12-05 2003-04-24 Gemplus Card Int Barrier against overflow for fixing adhesive of a semiconductor chip

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