AU2002216182A1 - Method for making a semiconductor chip using an integrated rigidity layer - Google Patents

Method for making a semiconductor chip using an integrated rigidity layer

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Publication number
AU2002216182A1
AU2002216182A1 AU2002216182A AU1618202A AU2002216182A1 AU 2002216182 A1 AU2002216182 A1 AU 2002216182A1 AU 2002216182 A AU2002216182 A AU 2002216182A AU 1618202 A AU1618202 A AU 1618202A AU 2002216182 A1 AU2002216182 A1 AU 2002216182A1
Authority
AU
Australia
Prior art keywords
making
semiconductor chip
rigidity layer
integrated rigidity
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002216182A
Inventor
Philippe Patrice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Publication of AU2002216182A1 publication Critical patent/AU2002216182A1/en
Abandoned legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
AU2002216182A 2000-12-05 2001-12-05 Method for making a semiconductor chip using an integrated rigidity layer Abandoned AU2002216182A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR00/15941 2000-12-05
FR0015941A FR2817656B1 (en) 2000-12-05 2000-12-05 ELECTRICAL INSULATION OF GROUPED MICROCIRCUITS BEFORE UNIT BONDING
PCT/FR2001/003846 WO2002047151A2 (en) 2000-12-05 2001-12-05 Method for making a semiconductor chip using an integrated rigidity layer

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AU2002216182A1 true AU2002216182A1 (en) 2002-06-18

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AU2002216172A Abandoned AU2002216172A1 (en) 2000-12-05 2001-12-05 Barrier against overflow for fixing adhesive of a semiconductor chip
AU2002216182A Abandoned AU2002216182A1 (en) 2000-12-05 2001-12-05 Method for making a semiconductor chip using an integrated rigidity layer

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FR2845805B1 (en) * 2002-10-10 2005-06-03 Gemplus Card Int SHUTTERING ADHESIVE FORMING SHUTTLE
DE102006010523B3 (en) 2006-02-20 2007-08-02 Siemens Ag Method and device for contacting an electrical contact surface on a substrate and/or a component on the substrate laminates an insulating film with laser-cut openings and applies electrically conductive material
JP4303282B2 (en) 2006-12-22 2009-07-29 Ｔｄｋ株式会社 Wiring structure of printed wiring board and method for forming the same
EP2357875A1 (en) * 2010-02-16 2011-08-17 Gemalto SA Method for manufacturing an electronic box

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JPS535970A (en) * 1976-07-07 1978-01-19 Toshiba Corp Semiconductor device
JPS53120271A (en) * 1977-03-29 1978-10-20 Mitsubishi Electric Corp Semiconductor device
JPS5760844A (en) * 1980-09-30 1982-04-13 Nec Corp Semiconductor device
US5144407A (en) * 1989-07-03 1992-09-01 General Electric Company Semiconductor chip protection layer and protected chip
JP3212110B2 (en) * 1991-07-15 2001-09-25 沖電気工業株式会社 Method for manufacturing semiconductor device
JP3128878B2 (en) * 1991-08-23 2001-01-29 ソニー株式会社 Semiconductor device
FR2735284B1 (en) * 1995-06-12 1997-08-29 Solaic Sa CHIP FOR ELECTRONIC CARD COATED WITH A LAYER OF INSULATING MATERIAL AND ELECTRONIC CARD CONTAINING SUCH A CHIP
FR2779272B1 (en) * 1998-05-27 2001-10-12 Gemplus Card Int METHOD FOR MANUFACTURING A MICROMODULE AND A STORAGE MEDIUM COMPRISING SUCH A MICROMODULE
FR2779851B1 (en) * 1998-06-12 2002-11-29 Gemplus Card Int METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT CARD AND CARD OBTAINED
DE19845296A1 (en) * 1998-09-03 2000-03-16 Fraunhofer Ges Forschung Method for contacting a circuit chip
FR2791471B1 (en) * 1999-03-22 2002-01-25 Gemplus Card Int METHOD FOR MANUFACTURING INTEGRATED CIRCUIT CHIPS
FR2806189B1 (en) * 2000-03-10 2002-05-31 Schlumberger Systems & Service REINFORCED INTEGRATED CIRCUIT AND METHOD FOR REINFORCING INTEGRATED CIRCUITS

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WO2002047161A3 (en) 2003-04-24
WO2002047151A2 (en) 2002-06-13
WO2002047161A2 (en) 2002-06-13
WO2002047151A3 (en) 2003-02-13
WO2002047151B1 (en) 2004-02-26
FR2817656B1 (en) 2003-09-26
AU2002216172A1 (en) 2002-06-18
FR2817656A1 (en) 2002-06-07

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