FR2645681B1 - Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication - Google Patents

Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication

Info

Publication number
FR2645681B1
FR2645681B1 FR8904592A FR8904592A FR2645681B1 FR 2645681 B1 FR2645681 B1 FR 2645681B1 FR 8904592 A FR8904592 A FR 8904592A FR 8904592 A FR8904592 A FR 8904592A FR 2645681 B1 FR2645681 B1 FR 2645681B1
Authority
FR
France
Prior art keywords
manufacturing
integrated circuits
interconnecting pads
vertically interconnecting
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR8904592A
Other languages
English (en)
Other versions
FR2645681A1 (fr
Inventor
Val Christian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR8904592A priority Critical patent/FR2645681B1/fr
Publication of FR2645681A1 publication Critical patent/FR2645681A1/fr
Application granted granted Critical
Publication of FR2645681B1 publication Critical patent/FR2645681B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80012—Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR8904592A 1989-04-07 1989-04-07 Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication Expired - Lifetime FR2645681B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8904592A FR2645681B1 (fr) 1989-04-07 1989-04-07 Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8904592A FR2645681B1 (fr) 1989-04-07 1989-04-07 Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication

Publications (2)

Publication Number Publication Date
FR2645681A1 FR2645681A1 (fr) 1990-10-12
FR2645681B1 true FR2645681B1 (fr) 1994-04-08

Family

ID=9380488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8904592A Expired - Lifetime FR2645681B1 (fr) 1989-04-07 1989-04-07 Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication

Country Status (1)

Country Link
FR (1) FR2645681B1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2620523B2 (ja) 1993-09-13 1997-06-18 インターナショナル・ビジネス・マシーンズ・コーポレイション 集積マルチチップ・メモリ・モジュールの構造および製造方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5847448A (en) * 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
FR2670323B1 (fr) * 1990-12-11 1997-12-12 Thomson Csf Procede et dispositif d'interconnexion de circuits integres en trois dimensions.
JPH0715969B2 (ja) * 1991-09-30 1995-02-22 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチチツプ集積回路パツケージ及びそのシステム
KR100310220B1 (ko) * 1992-09-14 2001-12-17 엘란 티본 집적회로장치를제조하기위한장치및그제조방법
FR2704690B1 (fr) * 1993-04-27 1995-06-23 Thomson Csf Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.
US5561622A (en) * 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
US5466634A (en) * 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
FR2802706B1 (fr) * 1999-12-15 2002-03-01 3D Plus Sa Procede et dispositif d'interconnexion en trois dimensions de composants electroniques
FR2812453B1 (fr) * 2000-07-25 2004-08-20 3D Plus Sa Procede de blindage et/ou de decouplage repartis pour un dispositif electronique a interconnexion en trois dimensions , dispositif ainsi obtenu et procede d'obtention de celui- ci
US6806559B2 (en) 2002-04-22 2004-10-19 Irvine Sensors Corporation Method and apparatus for connecting vertically stacked integrated circuit chips
US7777321B2 (en) 2002-04-22 2010-08-17 Gann Keith D Stacked microelectronic layer and module with three-axis channel T-connects
US7064055B2 (en) 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
WO2004061961A1 (fr) * 2002-12-31 2004-07-22 Massachusetts Institute Of Technology Structure integree multicouche de semi-conducteur avec partie d'ecran electrique
US8461542B2 (en) 2008-09-08 2013-06-11 Koninklijke Philips Electronics N.V. Radiation detector with a stack of converter plates and interconnect layers
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2022895B2 (de) * 1970-05-11 1976-12-02 Siemens AG, 1000 Berlin und 8000 München Stapelfoermige anordnung von halbleiterkoerpern und verfahren zu deren herstellung
JPS5853822A (ja) * 1981-09-25 1983-03-30 Toshiba Corp 積層半導体装置
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
KR900008647B1 (ko) * 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
US4734825A (en) * 1986-09-05 1988-03-29 Motorola Inc. Integrated circuit stackable package
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2620523B2 (ja) 1993-09-13 1997-06-18 インターナショナル・ビジネス・マシーンズ・コーポレイション 集積マルチチップ・メモリ・モジュールの構造および製造方法

Also Published As

Publication number Publication date
FR2645681A1 (fr) 1990-10-12

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