EP0380481A1 - Recepteur selectif pour chaque processeur d'un systeme a processeur multiple - Google Patents

Recepteur selectif pour chaque processeur d'un systeme a processeur multiple

Info

Publication number
EP0380481A1
EP0380481A1 EP19880904138 EP88904138A EP0380481A1 EP 0380481 A1 EP0380481 A1 EP 0380481A1 EP 19880904138 EP19880904138 EP 19880904138 EP 88904138 A EP88904138 A EP 88904138A EP 0380481 A1 EP0380481 A1 EP 0380481A1
Authority
EP
European Patent Office
Prior art keywords
data
bus
processor
port
buffer means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880904138
Other languages
German (de)
English (en)
Inventor
David Mordecai Cohen
Bhaskarpillai Gopinath
John Richard Vollaro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iconectiv LLC
Original Assignee
Bell Communications Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bell Communications Research Inc filed Critical Bell Communications Research Inc
Publication of EP0380481A1 publication Critical patent/EP0380481A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Definitions

  • This invention relates generally to multiple processor configurations and, more particularly, to circuitry and associated methodology for enabling each processor to receive selectively only pertinent portions of data that is broadcast to the processor over a communication bus interconnecting the processors.
  • a programmable digital computer provides a readily adaptable environment to simulate physical systems such as a communication network or a multi-layer protocol.
  • parallel processing system computations are subdivided into tasks that are suitable for execution in parallel. The tasks are then distributed among a plurality of synchronized processors for autonomous execution.
  • computation results are stored in a single memory which is common to or shared among the several processors via a multiple access memory bus interconnecting the memory with the processors.
  • Traditional methods for accessing and then storing computational data into the single memory possess inherent deficiencies. Two prime areas of difficulty are excessive loading of the memory bus and high overhead manifested by extra, unproductive processor cycles.
  • each autonomous processor with an arrangement to receive selectively only pertinent segments of data propagating over the bus.
  • this is achieved by providing each processor with both buffer memory means and means for selectively enabling the buffer means to accept data on a first-in, first-out basis off the bus.
  • the means for enabling stores information which is indicative of those segments of data that are required by the associated processor.
  • FIG. 1 is a block diagram depicting three processors, and their associated shared address space circuits, from a multiple processor system configured in accordance with one aspect of the present invention
  • FIG. 2 depicts, in block diagram form, one processor and its associated shared address space circuitry from FIG. 1, wherein the circuitry is shown to further comprise a control arrangement for conflict resolution and flow control;
  • FIG. 3 is a timing diagram for the embodiment in accordance with FIGS. 1 and 2.
  • each processing unit 100, 200 or 300 includes stand-alone processors 110, 210 or 310, and each of these processors is coupled to shared address space circuitry.
  • processor 110 for example, mask memory 120, first-in, first-out (FIFO) buffer 140 and AND gate 130 are circuits comprising the shared address space circuitry of processor 110.
  • memory 120, gate 130 and FIFO 140 each are coupled to bus 60.
  • memory 120 is coupled to parallel address (ADD) sub-bus 61
  • gate 130 is connected to STROBE lead 63
  • FIFO 140 has parallel DATA sub-bus 62 as input. All other shared address space circuitry associated with the remaining processors are configured in essentially the same manner.
  • each processor 110, 210 and 310 operates in essentially an autonomous mode, that is, in the sense that each processor is composed of an internal clock (not shown) which is independent of the clocks in all other processors.
  • the processors operate autonomously, the processors form a parallel processing system having a need to interact such as, for example, by transmitting information generated by or stored in one processor to certain other processors requiring that information; computational data from executed tasks is one form of the information requiring transmission.
  • This is effected over bus 60 in the conventional manner; for the VME-type arrangement, an interrupt signal is the indicator of a transmit ready condition for the broadcasting of information by one or more processors.
  • a separate copy of the data broadcast over bus 62 may be stored by FIFO's 140, 240 and 340. When data is written on bus 62, the data is registered simultaneously in each enabled FIFO.
  • the arrangement in accordance with the present invention utilizes replicated, distributed FIFO buffers that are selectively enabled to receive data on bus 62. This makes it possible for each processor to accept only the data that is pertinent to its tasks from what is broadcast over bus 62. Once copied, reading of the data by any particular processor 110, 210 or 310 may occur asynchronously from its associated private copy.
  • Mask memory 120 is illustratively a one bit wide memory having its address input (A) connected to bus 61. Memory 120 stores an enable bit at each address which is pertinent to its associated processor 110.
  • the output (Q) of memory 120 serves as one input to AND gate 130 via lead 121.
  • the other input to gate 130 is STROBE lead 63 of bus 60.
  • the STROBE signal indicates when data is stabilized and may be read off bus 60.
  • the output of gate 130, on lead 131 serves to enable the SHIFT-IN input of FIFO 140.
  • the one bit of mask memory 120 when ANDed with the FIFO write signal, allows FIFO 140 to receive selectively the data presented to its DATA IN port. Since -a,-g-iven " processor usually requires only a limited portion of the br-oadcast data, the AND operation effectively filters unwanted data under control of the contents of memory 120. Moreover, this arrangement of FIFO 140 effects non-destruct write operations. Since every data update is stored when received on a first-in, first-out basis, processor 110 has available a history of variable changes. For instance, it is supposed that there are two successive writes to an enabled memory location by processing units 200 and 300, respectively. Because of interposed FIFO 140, the two data segments are stacked in FIFO 140. Now, if a conflict is detected (as discussed shortly) , the fact that successive segments of data have been written to the same address and, consequently, are stored serially in FIFO 140, allows for conflict resolution according to an algorithm that is appropriate to the process being executed.
  • processor 110 and its associated shared address space circuitry are shown together with circuitry to control conflict resolution and flow control.
  • Conflicts are detected by supplying "PENDING" lead 72 and connecting lead 72 to all processors of processor system 50.
  • Lead 72 is arranged to have a "wired OR" characteristic, that is, one or more processors can force PENDING to its dominant or asserted state.
  • the PENDING signal is transmitted from the P-OUT port of processor 110 via inverter 154, and PENDING is received at the P-IN port via inverter 156.
  • PENDING is asserted by any processor 110, 210 or 310 at the start of a standard contention cycle on bus 60, and PENDING is released upon the release of bus 60 after the update process is complete. If multiple processors are queued and waiting to use bus 60, PENDING is asserted from the beginning of the first bus request until the completion of the last update; FIG. 3, discussed below, presents timing information.
  • Receiving processor 110 remains in the receive mode until PENDING is cleared after completion of the next data transmission. Finally, when lead 72 is unasserted, « the receiving processor may begin an appropriate conflict resolution routine, being assured that all possible 5 conflicting data has been received.
  • the conflict resolution scheme since it is not hard-wired, may be implemented as appropriate to each simulation application. For instance, one resolution scheme may deal with the conflict by taking the first update and discarding all 10 others; another scheme may be to average the data.
  • a flow control mechanism is provided to preclude FIFO overflow.
  • the FIFO's are configured to provide a signal on their 15 FLOW port (FIG. 2) whenever they are filled to a predetermined threshold.
  • the FLOW port is connected to FLOW lead 71 via, for example, inverter 150 for FIFO 140.
  • lead 71 connects to all other processors via, for example, the F port through inverter 152.
  • Lead 71 is also
  • FIG. 3 To exemplify the timing required of the various components comprising processing system 50, FIG. 3 is considered. It is presumed that processors 210 and 310 are propagating variable changes to processor 110
  • bus 60 transmits an INITIATE transfer of data signal to processors 210 and 310. This is shown as TIME POSITION 1 and line (i) . Both processors 210 and 310 assert PENDING on lead 72, as shown as TIME POSITION 2 on line (ii) ; also, these processors
  • processor 210 acquires bus 60 first, then processor 210 begins to transmit its data; this is depicted as beginning at TIME POSITION 3 on line (iii) .
  • the data is received by processor 110 through its shared address space circuitry; in particular, since FIFO 140 receives data, an INTERRUPT is issued to processor 110 via the DATA READY port of FIFO 140.
  • This INTERRUPT signal is shown as commencing at TIME POSITION 4 of line (v) .
  • processor 110 begins to read the data.
  • TIME POSITION 5 on line (vi) depicts the start of the read phase.
  • processor 210 has completed its write operation.
  • processor 110 completes its read phase and checks the PENDING lead. Since it is still asserted by processor 310, processor 110 awaits more data.
  • Processor 310 now acquires bus 60 and my begin to write the data onto bus 60;
  • TIME POSITION 8 on line (iv) indicates the time that processor 310 begins data transmission.
  • PENDING is unasserted, as per TIME POSITION 9 on line (ii) .
  • data processor 110 detects that PENDING is released, it may begin to process the total data now in its local storage.
  • TIME POSITION 10 on live (vii) depicts the start of the processing by processor 110 and TIME POSITION 11 shows the completion time.
  • Processors 110, 210 and 310 are now prepared to proceed with the next phase in the simulation process.
  • each shared address space circuitry e.g., elements 120, 130 and 140 of FIG. 1
  • mask memory 120 is an N+l bit wide memory wherein one of the bits is used in conjunction with gate 130 for activating data copying and the remaining N bits indicate the address in local memory allocated to store the data.
  • mask memory 120 as described are static, it is possible to alter dynamically- its contents by also arranging memory 120 with an enable input so as to receive data off bus 60 to alter its contents.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

Procédé et circuit dans un système de traitement en parallèle (50) pour partager l'espace d'adresse parmi une pluralité de processeurs autonomes (110, 210, 310) communiquant par un bus commun, dans le but d'obtenir un environnement de stockage et de transfert de données efficace et non destructif. Ce résultat est obtenu en augmentant chaque processeur avec des moyens tampons (p.ex. 140) pour stocker des données reçues du bus, et des moyens (p.ex. 120, 130) pour valider sélectivement les moyens tampons et accepter les segments de données ayant des adresses affectées au processeur donné. Pour éviter la superposition d'écriture de données lors de conflits de bus, les moyens tampons sont conçus pour stocker des données d'après un système premier entré, premier sorti et pour commander les états de traitement et le transfert de données en correspondance aux états respectifs du bus et des processeurs.
EP19880904138 1987-10-06 1988-04-20 Recepteur selectif pour chaque processeur d'un systeme a processeur multiple Withdrawn EP0380481A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10499187A 1987-10-06 1987-10-06
US104991 1987-10-06

Publications (1)

Publication Number Publication Date
EP0380481A1 true EP0380481A1 (fr) 1990-08-08

Family

ID=22303492

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880904138 Withdrawn EP0380481A1 (fr) 1987-10-06 1988-04-20 Recepteur selectif pour chaque processeur d'un systeme a processeur multiple

Country Status (4)

Country Link
EP (1) EP0380481A1 (fr)
JP (1) JPH02503121A (fr)
CA (1) CA1309503C (fr)
WO (1) WO1989003565A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3493309B2 (ja) 1997-10-31 2004-02-03 富士通株式会社 マルチキャスト送信方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2703559A1 (de) * 1977-01-28 1978-08-03 Siemens Ag Rechnersystem
US4604500A (en) * 1981-12-02 1986-08-05 At&T Bell Laboratories Multiprocessing interrupt arrangement
US4494190A (en) * 1982-05-12 1985-01-15 Honeywell Information Systems Inc. FIFO buffer to cache memory
DE3233542A1 (de) * 1982-09-10 1984-03-15 Philips Kommunikations Industrie AG, 8500 Nürnberg Verfahren und schaltungsanordnung zur abgabe von unterbrechungs-anforderungssignalen
AU4907285A (en) * 1984-11-09 1986-05-15 Spacelabs, Inc. Communications bus broadcasting

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8903565A1 *

Also Published As

Publication number Publication date
JPH02503121A (ja) 1990-09-27
CA1309503C (fr) 1992-10-27
WO1989003565A1 (fr) 1989-04-20

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