CA1309503C - Recepteur selectif pour processeur de systeme a processeurs multiples - Google Patents
Recepteur selectif pour processeur de systeme a processeurs multiplesInfo
- Publication number
- CA1309503C CA1309503C CA000572328A CA572328A CA1309503C CA 1309503 C CA1309503 C CA 1309503C CA 000572328 A CA000572328 A CA 000572328A CA 572328 A CA572328 A CA 572328A CA 1309503 C CA1309503 C CA 1309503C
- Authority
- CA
- Canada
- Prior art keywords
- processors
- data
- processor
- bus
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10499187A | 1987-10-06 | 1987-10-06 | |
US07/104,991 | 1987-10-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1309503C true CA1309503C (fr) | 1992-10-27 |
Family
ID=22303492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000572328A Expired - Lifetime CA1309503C (fr) | 1987-10-06 | 1988-07-18 | Recepteur selectif pour processeur de systeme a processeurs multiples |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0380481A1 (fr) |
JP (1) | JPH02503121A (fr) |
CA (1) | CA1309503C (fr) |
WO (1) | WO1989003565A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3493309B2 (ja) | 1997-10-31 | 2004-02-03 | 富士通株式会社 | マルチキャスト送信方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2703559A1 (de) * | 1977-01-28 | 1978-08-03 | Siemens Ag | Rechnersystem |
US4604500A (en) * | 1981-12-02 | 1986-08-05 | At&T Bell Laboratories | Multiprocessing interrupt arrangement |
US4494190A (en) * | 1982-05-12 | 1985-01-15 | Honeywell Information Systems Inc. | FIFO buffer to cache memory |
DE3233542A1 (de) * | 1982-09-10 | 1984-03-15 | Philips Kommunikations Industrie AG, 8500 Nürnberg | Verfahren und schaltungsanordnung zur abgabe von unterbrechungs-anforderungssignalen |
AU4907285A (en) * | 1984-11-09 | 1986-05-15 | Spacelabs, Inc. | Communications bus broadcasting |
-
1988
- 1988-04-20 JP JP50378888A patent/JPH02503121A/ja active Pending
- 1988-04-20 WO PCT/US1988/001283 patent/WO1989003565A1/fr not_active Application Discontinuation
- 1988-04-20 EP EP19880904138 patent/EP0380481A1/fr not_active Withdrawn
- 1988-07-18 CA CA000572328A patent/CA1309503C/fr not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO1989003565A1 (fr) | 1989-04-20 |
JPH02503121A (ja) | 1990-09-27 |
EP0380481A1 (fr) | 1990-08-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKLA | Lapsed |