EP0327608A1 - Cmos-schwellenschaltung. - Google Patents

Cmos-schwellenschaltung.

Info

Publication number
EP0327608A1
EP0327608A1 EP88905310A EP88905310A EP0327608A1 EP 0327608 A1 EP0327608 A1 EP 0327608A1 EP 88905310 A EP88905310 A EP 88905310A EP 88905310 A EP88905310 A EP 88905310A EP 0327608 A1 EP0327608 A1 EP 0327608A1
Authority
EP
European Patent Office
Prior art keywords
terminal means
channel
source
input
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88905310A
Other languages
English (en)
French (fr)
Other versions
EP0327608B1 (de
Inventor
Donald Keith Lauffer
Ikuo Jimmy Sanwo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0327608A1 publication Critical patent/EP0327608A1/de
Application granted granted Critical
Publication of EP0327608B1 publication Critical patent/EP0327608B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Definitions

  • This invention relates to a CMOS circuit having an input threshold, of the kind including input terminal means, output terminal means, first power supply terminal means, second power supply terminal means and first field-effect transistor means having first source-drain path means connected between said first power supply terminal means and said output terminal means, and first gate means connected to said input terminal means, said first source-drain path including a first channel means of a first conductivity type, having an effective first width and first length.
  • the invention has a particular application as a buffer circuit for logic level conversion.
  • U.S. Patent No. 4,555,642 discloses a low power CMOS input buffer circuit for use with a TTL level input.
  • An additional input buffer dummy stage is configured as in a real input buffer stage.
  • the current produced in the dummy stage is sensed and converted to a compensation voltage, which is applied to the real buffer stages to modify the current therein to a desired minimum level.
  • CMOS circuit of the kind specified, characterized by programmable field-effect transistor means having second gate means connected to said input terminal means, and second source-drain path means connected between said output terminal means and said second power supply terminal means, said second source-drain path including a second channel means of a second conductivity type, having an effective second width and second length, and programmable input means connected to said second channel means and adapted to change the ratio of the product of said first width times said second length to the product of said second width times said first length, such that the input threshold voltage of said CMOS circuit is changed accordingly.
  • CMOS circuit has the advantage that its threshold may be programmed to one of several values, as desired.
  • Fig. 1 is a schematic diagram of a prior art inverter circuit having a p channel transistor and an n channel transistor;
  • Fig. 2 is a plot of the value of the threshold voltage (V TH ) in volts versus the ratio (W p L n /W n L p ) for two values of the power supply voltage between the terminals V A and V B of the circuit of Fig. 1;
  • Fig. 3 is a schematic diagram of an inverter circuit of an embodiment of the present invention utilizing a pair of n channel transistors which may be connected in parallel by jumpers;
  • Fig. 4 is a schematic diagram of an inverter circuit wherein a pair of p channel transistors are connected in series;
  • Fig. 5 is a schematic diagram of the circuit of the preferred embodiment of the present invention having a programmable input threshold. Best Mode for Carrying Out the Invention
  • Fig. 1 is a circuit diagram of a CMOS inverter circuit 9 in which transistor 10 is a p channel transistor that is turned on when the voltage V IN is low in comparison with V A , making the voltage V OUT high.
  • Transistor 12 is a n channel transistor which is turned on when the voltage V IN is high in comparison to V B , making the voltage V OUT low.
  • V TH threshold voltage
  • V AB Power supply voltage between V A and V B ;
  • V TP Linear threshold voltage of the p channel device
  • V TN Linear threshold voltage of the n channel device
  • W p Width of the p channel device
  • W n Width of the n channel device
  • L p Length of the p channel device
  • L n Length of the n channel device
  • Fig. 2 is a plot of the value of V TH in volts versus the ratio (W p L n /W n L p ) wherein the values of V TP , V TN , and K are constants.
  • Line 14 is a curve wherein the value of V ⁇ g is held constant at 3.3 volts, and the ratio (W p L n /W n L p ) is varied.
  • the line 16 is a curve wherein the value of V AB is held constant at 5 volts, and the ratio (W p L n /W n L p ) is varied. It will thus be seen that the threshold voltage V TH of the inverter circuit of Fig.
  • the transistors 10 and 12 are comprised of multiple transistors which may be selectively placed in series- parallel combinations to vary the ratio (W p L n /W n L p ), as desired.
  • Fig. 3 is a circuit diagram of a CMOS inverter 17 having a p channel transistor 18, which is equivalent to the p channel transistor 10 of Fig. 1, and a pair of n channel transistors 20 and 21, which together are equivalent to the n transistor 12 of Fig. 1.
  • the sources of the transistors 20 and 21 are connected to the terminal 22 on which is placed voltage V B .
  • the drains of the transistors 20 and 21 are connected to the output terminal 24 of the inverter circuit 17 via jumpers 26 and 28, respectively.
  • the source of the p channel transistor 18 is connected to the terminal 30 on which is placed the voltage V A , and its drain is connected to the output terminal 24.
  • the gates of the transistors 18 and 20 are connected to the input terminal 32 which receives the input voltage V IN .
  • the gate of the transistor 21 is connected to the input terminal 32 via a jumper 34.
  • the ratio of the width of the p channel transistor 18 to its length is 160/2, as shown in Fig. 3.
  • the ratio of the width of each of the n channel transistors 20 and 21 to its length is 80/2.
  • the threshold voltage of the inverter circuit 17 is about 2.1 volts. If the jumpers 28 and 34 are disconnected and the voltage V AB is held at 3.3 volts, the threshold voltage is about 1.55 volts (see 37 on line 14 of Fig. 2). If the jumpers 28 and 34 are connected and the voltage V AB is held at 3.3 volts, the threshold voltage is about 1.37 volts (see 38 on line 14 of Fig. 2).
  • Fig. 4 is a schematic diagram of an inverter circuit 39 having p channel transistors 40 and 41 in series.
  • the source of the transistor 40 is connected to a V A terminal 43, and its drain is connected to the source of the transistor 41.
  • the drain of the p channel transistor 41 is connected to a V OUT terminal 42.
  • An n channel transistor 44 has its source connected to a V B terminal 45 and its drain connected to the V OUT terminal 42.
  • the gates of the transistors 41 and 44 are connected to a V IN terminal 46.
  • the gate of the p channel transistor 40 is connected to the V B terminal 45.
  • the ratio of the width to the length of each of the p channel devices 40 and 41 is 160/2, and the ratio of the width to the length of the n channel device 44 is 80/2.
  • the threshold voltage V T H for the inverter circuit 39 is about 2.1 volts (36 on line 16)
  • the threshold voltage V TH is about 1.37 volts (38 on line 14). It will thus be understood that the threshold voltage of an inverter circuit can readily be adjusted by arranging its transistors in parallel (Fig. 3), by arranging its transistors in series (Fig. 4), and/or by changing its power supply voltage V AB .
  • Fig. 5 is a schematic diagram of an inverter circuit 50 of the preferred embodiment of the present invention having a p channel transistor 52 with its source connected to a V A terminal 54 and its drain connected to a V OUT terminal 56.
  • the gate of the p channel transistor 52 is connected to a V IN terminal 58.
  • An n channel transistor 60 has its source connected to a V B terminal 62 and its drain connected to the V OUT terminal 56.
  • a first pair of n channel transistors 64 and 66 are connected in series with the source of transistor 66 connected to the V B terminal 62, the drain of the transistor 66 connected to the source of the transistor 64, and the drain of the transistor 64 connected to the V OUT terminal 56.
  • a second pair of n channel transistors 68 and 70 are connected in series with the source of transistor 70 connected to the V B terminal 62, the drain of the transistor 70 connected to the source of the transistor 68, and the drain of the transistor 68 connected to the V OUT terminal 56.
  • the gates of the transistors 60, 64 and 68 are connected to the V IN terminal 58.
  • a shift register 72 which may be an MM74C95 device from National Semiconductor, has a serial input 74 connected to pin 1 for receiving serial data bits, a clock input 76 connected to pin 7 for clocking data bits into the shift register 72, and outputs 78 and 80 connected between pin 13 and the gate of transistor 66 and between pin 12 and the gate of the transistor 70, respectively.
  • data bits may be shifted into the shift register 72 to turn on the transistors 66 or 70 thereby arranging the transistors 60, 64, 66, 68 and 70 in the desired series/parallel circuit such that the (W p L n /W n L p ) ratio of the inverter circuit 50 is at the desired level.
  • the inverter circuit 50 of Fig. 5 is programmable in that when the output on pin 13 (O A ) of the shift register 70 is high, the transistor 66 is enabled and the series transistors 64 and 66 are placed in parallel with the transistor 60. When the output on pin 12 (O B ) of the shift register 72 is high, the transistor 70 is enabled and the series transistors 68 and 70 are placed in parallel with the transistor 60.
  • the following table shows programmed variations of the circuit 50 for providing interfaces between emitter coupled logic (ECL), normal complementary metal oxide silicon (CMOS) logic, and/or transistor-to-transistor logic (TTL).
  • ECL emitter coupled logic
  • CMOS normal complementary metal oxide silicon
  • TTL transistor-to-transistor logic
  • CMOS devices which are formed on a chip with the inverter circuit 50, either alone or with other devices, to provide a programmable interface between the circuit on the chip and other devices external to the chip. Any of such devices are referred to herein as a register.
  • Various parallel and series combinations may also be used other than the combinations shown in Fig. 5.
  • the input structure may also be applied to other logic devices such as NOR or NAND structures.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
EP88905310A 1987-06-04 1988-05-26 Cmos-schwellenschaltung Expired - Lifetime EP0327608B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57416 1987-06-04
US07/057,416 US5059835A (en) 1987-06-04 1987-06-04 Cmos circuit with programmable input threshold

Publications (2)

Publication Number Publication Date
EP0327608A1 true EP0327608A1 (de) 1989-08-16
EP0327608B1 EP0327608B1 (de) 1992-03-11

Family

ID=22010454

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88905310A Expired - Lifetime EP0327608B1 (de) 1987-06-04 1988-05-26 Cmos-schwellenschaltung

Country Status (5)

Country Link
US (1) US5059835A (de)
EP (1) EP0327608B1 (de)
JP (1) JP2909990B2 (de)
DE (1) DE3869117D1 (de)
WO (1) WO1988010031A1 (de)

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US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors
US4999529A (en) * 1989-06-30 1991-03-12 At&T Bell Laboratories Programmable logic level input buffer
JPH03179780A (ja) * 1989-12-07 1991-08-05 Fujitsu Ltd 半導体装置
US5227679A (en) * 1992-01-02 1993-07-13 Advanced Micro Devices, Inc. Cmos digital-controlled delay gate
JPH06209252A (ja) * 1992-09-29 1994-07-26 Siemens Ag Ｃｍｏｓ入力段
EP0590326A1 (de) * 1992-09-29 1994-04-06 Siemens Aktiengesellschaft CMOS-Eingangsstufe
US5424672A (en) * 1994-02-24 1995-06-13 Micron Semiconductor, Inc. Low current redundancy fuse assembly
US5945840A (en) * 1994-02-24 1999-08-31 Micron Technology, Inc. Low current redundancy anti-fuse assembly
JPH07297705A (ja) * 1994-04-27 1995-11-10 Mitsubishi Electric Corp 出力バッファ回路
US6433579B1 (en) 1998-07-02 2002-08-13 Altera Corporation Programmable logic integrated circuit devices with differential signaling capabilities
US6346827B1 (en) 1998-09-09 2002-02-12 Altera Corporation Programmable logic device input/output circuit configurable as reference voltage input circuit
US6472903B1 (en) 1999-01-08 2002-10-29 Altera Corporation Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
US6967348B2 (en) * 2002-06-20 2005-11-22 Micron Technology, Inc. Signal sharing circuit with microelectric die isolation features
US7307446B1 (en) 2003-01-07 2007-12-11 Altera Corporation Integrated circuit output driver circuitry with programmable preemphasis
US6831480B1 (en) 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
US6940302B1 (en) * 2003-01-07 2005-09-06 Altera Corporation Integrated circuit output driver circuitry with programmable preemphasis
US7598779B1 (en) 2004-10-08 2009-10-06 Altera Corporation Dual-mode LVDS/CML transmitter methods and apparatus
US7365570B2 (en) * 2005-05-25 2008-04-29 Micron Technology, Inc. Pseudo-differential output driver with high immunity to noise and jitter
US7265587B1 (en) 2005-07-26 2007-09-04 Altera Corporation LVDS output buffer pre-emphasis methods and apparatus
US7953162B2 (en) * 2006-11-17 2011-05-31 Intersil Americas Inc. Use of differential pair as single-ended data paths to transport low speed data
US7733118B2 (en) * 2008-03-06 2010-06-08 Micron Technology, Inc. Devices and methods for driving a signal off an integrated circuit
US7973557B2 (en) * 2008-05-02 2011-07-05 Texas Instruments Incorporated IC having programmable digital logic cells
US8102187B2 (en) * 2008-05-02 2012-01-24 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US8324934B1 (en) 2011-01-17 2012-12-04 Lattice Semiconductor Corporation Programmable buffer
WO2015045207A1 (ja) 2013-09-27 2015-04-02 パナソニック株式会社 半導体集積回路および半導体集積回路装置
CN107534440B (zh) 2015-04-02 2018-12-25 美高森美半导体无限责任公司 通用输入缓冲器

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Also Published As

Publication number Publication date
WO1988010031A1 (en) 1988-12-15
JPH01503510A (ja) 1989-11-22
DE3869117D1 (de) 1992-04-16
JP2909990B2 (ja) 1999-06-23
EP0327608B1 (de) 1992-03-11
US5059835A (en) 1991-10-22

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