DE3869117D1 - Cmos-schwellenschaltung. - Google Patents

Cmos-schwellenschaltung.

Info

Publication number
DE3869117D1
DE3869117D1 DE8888905310T DE3869117T DE3869117D1 DE 3869117 D1 DE3869117 D1 DE 3869117D1 DE 8888905310 T DE8888905310 T DE 8888905310T DE 3869117 T DE3869117 T DE 3869117T DE 3869117 D1 DE3869117 D1 DE 3869117D1
Authority
DE
Germany
Prior art keywords
cmos threshold
cmos
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888905310T
Other languages
English (en)
Inventor
Keith Lauffer
Jimmy Sanwo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE3869117D1 publication Critical patent/DE3869117D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE8888905310T 1987-06-04 1988-05-26 Cmos-schwellenschaltung. Expired - Lifetime DE3869117D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/057,416 US5059835A (en) 1987-06-04 1987-06-04 Cmos circuit with programmable input threshold
PCT/US1988/001770 WO1988010031A1 (en) 1987-06-04 1988-05-26 Cmos threshold circuit

Publications (1)

Publication Number Publication Date
DE3869117D1 true DE3869117D1 (de) 1992-04-16

Family

ID=22010454

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888905310T Expired - Lifetime DE3869117D1 (de) 1987-06-04 1988-05-26 Cmos-schwellenschaltung.

Country Status (5)

Country Link
US (1) US5059835A (de)
EP (1) EP0327608B1 (de)
JP (1) JP2909990B2 (de)
DE (1) DE3869117D1 (de)
WO (1) WO1988010031A1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors
US5469085A (en) * 1991-01-12 1995-11-21 Shibata; Tadashi Source follower using two pairs of NMOS and PMOS transistors
US4999529A (en) * 1989-06-30 1991-03-12 At&T Bell Laboratories Programmable logic level input buffer
JPH03179780A (ja) * 1989-12-07 1991-08-05 Fujitsu Ltd 半導体装置
US5227679A (en) * 1992-01-02 1993-07-13 Advanced Micro Devices, Inc. Cmos digital-controlled delay gate
JPH06209252A (ja) * 1992-09-29 1994-07-26 Siemens Ag Ｃｍｏｓ入力段
EP0590326A1 (de) * 1992-09-29 1994-04-06 Siemens Aktiengesellschaft CMOS-Eingangsstufe
US5945840A (en) * 1994-02-24 1999-08-31 Micron Technology, Inc. Low current redundancy anti-fuse assembly
US5424672A (en) * 1994-02-24 1995-06-13 Micron Semiconductor, Inc. Low current redundancy fuse assembly
JPH07297705A (ja) * 1994-04-27 1995-11-10 Mitsubishi Electric Corp 出力バッファ回路
US6433579B1 (en) 1998-07-02 2002-08-13 Altera Corporation Programmable logic integrated circuit devices with differential signaling capabilities
US6346827B1 (en) 1998-09-09 2002-02-12 Altera Corporation Programmable logic device input/output circuit configurable as reference voltage input circuit
US6472903B1 (en) 1999-01-08 2002-10-29 Altera Corporation Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
US6967348B2 (en) * 2002-06-20 2005-11-22 Micron Technology, Inc. Signal sharing circuit with microelectric die isolation features
US7307446B1 (en) 2003-01-07 2007-12-11 Altera Corporation Integrated circuit output driver circuitry with programmable preemphasis
US6940302B1 (en) * 2003-01-07 2005-09-06 Altera Corporation Integrated circuit output driver circuitry with programmable preemphasis
US6831480B1 (en) 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
US7598779B1 (en) 2004-10-08 2009-10-06 Altera Corporation Dual-mode LVDS/CML transmitter methods and apparatus
US7365570B2 (en) * 2005-05-25 2008-04-29 Micron Technology, Inc. Pseudo-differential output driver with high immunity to noise and jitter
US7265587B1 (en) 2005-07-26 2007-09-04 Altera Corporation LVDS output buffer pre-emphasis methods and apparatus
US7953162B2 (en) * 2006-11-17 2011-05-31 Intersil Americas Inc. Use of differential pair as single-ended data paths to transport low speed data
US7733118B2 (en) * 2008-03-06 2010-06-08 Micron Technology, Inc. Devices and methods for driving a signal off an integrated circuit
US8102187B2 (en) * 2008-05-02 2012-01-24 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US7973557B2 (en) * 2008-05-02 2011-07-05 Texas Instruments Incorporated IC having programmable digital logic cells
US8324934B1 (en) 2011-01-17 2012-12-04 Lattice Semiconductor Corporation Programmable buffer
WO2015045207A1 (ja) * 2013-09-27 2015-04-02 パナソニック株式会社 半導体集積回路および半導体集積回路装置
WO2016154761A1 (en) 2015-04-02 2016-10-06 Microsemi Semiconductor Ulc Universal input buffer

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691401A (en) * 1971-03-10 1972-09-12 Honeywell Inf Systems Convertible nand/nor gate
US3900742A (en) * 1974-06-24 1975-08-19 Us Navy Threshold logic using complementary mos device
US4016434A (en) * 1975-09-04 1977-04-05 International Business Machines Corporation Load gate compensator circuit
US4217502A (en) * 1977-09-10 1980-08-12 Tokyo Shibaura Denki Kabushiki Kaisha Converter producing three output states
US4242604A (en) * 1978-08-10 1980-12-30 National Semiconductor Corporation MOS Input circuit with selectable stabilized trip voltage
US4438352A (en) * 1980-06-02 1984-03-20 Xerox Corporation TTL Compatible CMOS input buffer
JPS5710533A (en) * 1980-06-23 1982-01-20 Nec Corp Logical circuit
US4495427A (en) * 1980-12-05 1985-01-22 Rca Corporation Programmable logic gates and networks
JPS5838032A (ja) * 1981-08-13 1983-03-05 Fujitsu Ltd Ｃ―ｍｏｓインバータ駆動用バッファ回路
DE3232843C2 (de) * 1981-09-03 1986-07-03 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa MOS-Logikschaltung
USRE32515E (en) * 1981-10-30 1987-10-06 American Telephone And Telegraph Company At&T Bell Laboratories Apparatus for increasing the speed of a circuit having a string of IGFETS
US4471242A (en) * 1981-12-21 1984-09-11 Motorola, Inc. TTL to CMOS Input buffer
DE3300869A1 (de) * 1982-01-26 1983-08-04 Deutsche Itt Industries Gmbh, 7800 Freiburg Logischer cmos-schaltkreis
JPS6030216A (ja) * 1983-07-28 1985-02-15 Mitsubishi Electric Corp 半導体装置
US4555642A (en) * 1983-09-22 1985-11-26 Standard Microsystems Corporation Low power CMOS input buffer circuit
US4609830A (en) * 1983-11-28 1986-09-02 Zoran Corporation Programmable logic gate
US4639615A (en) * 1983-12-28 1987-01-27 At&T Bell Laboratories Trimmable loading elements to control clock skew
US4584491A (en) * 1984-01-12 1986-04-22 Motorola, Inc. TTL to CMOS input buffer circuit for minimizing power consumption
US4595845A (en) * 1984-03-13 1986-06-17 Mostek Corporation Non-overlapping clock CMOS circuit with two threshold voltages
US4590388A (en) * 1984-04-23 1986-05-20 At&T Bell Laboratories CMOS spare decoder circuit
JPS61112424A (ja) * 1984-11-06 1986-05-30 Nec Corp 出力バツフア回路
US4593212A (en) * 1984-12-28 1986-06-03 Motorola, Inc. TTL to CMOS input buffer
EP0253914A1 (de) * 1986-07-23 1988-01-27 Deutsche ITT Industries GmbH Isolierschicht-Feldeffekttransistor-Gegentakttreiberstufe mit Kompensierung von Betriebsparameterschwankungen und Fertigungsstreuungen

Also Published As

Publication number Publication date
WO1988010031A1 (en) 1988-12-15
EP0327608B1 (de) 1992-03-11
US5059835A (en) 1991-10-22
EP0327608A1 (de) 1989-08-16
JPH01503510A (ja) 1989-11-22
JP2909990B2 (ja) 1999-06-23

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Legal Events

Date Code Title Description
8380 Miscellaneous part iii

Free format text: DER PATENTINHABER LAUTET RICHTIG: NCR INTERNATIONAL INC., DAYTON, OHIO, US

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8339 Ceased/non-payment of the annual fee