EP0324470A2 - Halbleiterspeicheranordnung mit serieller Zugriffsanordnung - Google Patents

Halbleiterspeicheranordnung mit serieller Zugriffsanordnung Download PDF

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Publication number
EP0324470A2
EP0324470A2 EP89100475A EP89100475A EP0324470A2 EP 0324470 A2 EP0324470 A2 EP 0324470A2 EP 89100475 A EP89100475 A EP 89100475A EP 89100475 A EP89100475 A EP 89100475A EP 0324470 A2 EP0324470 A2 EP 0324470A2
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EP
European Patent Office
Prior art keywords
memory
data
circuit
latch circuits
bit lines
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Granted
Application number
EP89100475A
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English (en)
French (fr)
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EP0324470A3 (de
EP0324470B1 (de
Inventor
Moemi Harada
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NEC Corp
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NEC Corp
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Publication of EP0324470A3 publication Critical patent/EP0324470A3/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Definitions

  • the present invention relates to a semiconductor memory and more particularly, to a memory provided with at least a serial access port.
  • this dual port memory is used as a memory (referred to as a "video memory") for holding image data.
  • the dual-port memory of this kind includes a random access port and a serial access port on the single chip.
  • the random access port is the same as the port provided to a conventional RAM (Random Access Memory).
  • the serial access port usually has a buffer (hereinafter referred to as "line buffer") corresponding to the number of bits of one word is used to simultaneously receive all the bits in the memory cells connected to the word line selected in accordance with row address information in the cell array and output them serially to the outside.
  • line buffer a buffer corresponding to the number of bits of one word is used to simultaneously receive all the bits in the memory cells connected to the word line selected in accordance with row address information in the cell array and output them serially to the outside.
  • the random access port and the serial access port can be used synchronously to that the read/write of image data between CPU and the video memory and the readout of display data from the video memory to a display (such as a CRT or a liquid crystal display) can be made asynchronously. Therefore, the dual-port memory can greatly contribute to the improvement in processing efficiency of CPU, high speed display/simplification of display processing and digitallization of TV, VTR, and the like.
  • the serial access port includes a word data latch circuit (hereinafter referred to as the "line buffer") for holding data derived from one selected word, a serial selection circuit for serially selecting data stored in the line buffer one by one, and a serial port for outputting data designated by the serial selection circuit.
  • the dual port memory having a large memory capacity such as 256 K bits or 1 Mega bits, whole memory cells are splited into a plurality of memory planes.
  • Each of the memory planes is provided with a random access port and a serial access port which includes a line buffer, a serial selection circuit and a serial output circuit.
  • one memory plane is selectively enabled while the remaining other memory planes are disenabled.
  • the number of the memory planes is increased, the number of line buffers as the nuclei of the dual-port memory must be increased in proportion to the number of memory planes. Therefore, though the total area of the cell array does not much change as a whole due to division into the memory planes, the occupying area of the line buffers increases in proportion to the number of the division. As a result, the problem develops in that the memory cell capacity is limited. Particularly because the serial access port having the line buffer must be able to operate asynchronously with the random access port, static type latch circuits not requiring refresh are preferably used for the line buffer even if dynamic memory transistors are used for the memory cells in the array. However, the area necessary for the static latch circuits is by far greater than that of the dynamic latch circuits.
  • the bit number of the line buffer is required to be the number of the memory cells which are selected at each access cycle, in each of the memory plane.
  • the bit number in all the line buffers is remarkably large even they are not used simultaneously.
  • the semiconductor memory circuit comprises first and second memory arrays, a common data hold circuit, a first control circuit for enabling one of the first and second memory arrays, and a data transfer circuit which transfers data derived from the first memory array to the common data hold circuit when the first memory array is enabled and transfers data derived from the second memory array to the common data hold circuit when the second memory array is enabled.
  • the single common data hold circuit is provided for both of the first and second memory arrays. Therefore, the area on the semi­conductor chip required to form the data hold circuit is greatly reduced.
  • a memory circuit comprising first and second memory planes, each of the first and second memory planes including first and second memory arrays, each of the first and second memory arrays having a plurality of word lines, a plurality of bit lines intersecting with said word lines and a plurality of memory cells coupled to the word lines and the bit lines; a data hold circuit having a plurality of latch circuits each having an input end and an output end; a first data transfer circuit connected between the bit lines of the first memory array and the input ends of the latch circuits of the data hold circuit; a second data transfer circuit connected between the digit lines of the second memory array and the input ends of the latch circuits of the data hold circuit; a serial data line; a plurality of transfer gates connected between the output ends of the latch circuits and the serial data line; a serial selection circuit coupled to said plurality of transfer gates for sequentially enabling the transfer gates one by one; first means for operatively enabling first transfer circuits of the first and second memory planes simultaneously thereby
  • the random access port (hereinafter referred to as the "RAM port") includes a memory cell array 10, a row decoder 11, a column decoder 12, a sense and selection circuit 13 and a random port 14 for outputting the data read out through the sense amplifiers to the outside and for writing the data inputted from outside into the memory cell array 10.
  • the memory cell array 10 includes word lines WL in rows, bit lines BL in columns, and dynamic type memory cells MC coupled to the the word lines and the bit lines in a known way.
  • the sense and selection circuit 13 includes sense amplifiers SA provided in columns and column selection transfer gate transistors QR coupled between outputs of the sense amplifiers SA and a data line DL1 connected to an random I/O port 14.
  • the outputs of the column decoder 12 are applied to gates of the transistors QR to make one of the transistors QR conductive.
  • the serial access port SAM includes a word data holding circuit (hereinafter referred to as the "line buffer") 15 for temporarily holding the data of one word (all the cells connected to one word line) inside the memory cell array 10, a serial pointer 16 (usually, a programmable shift register) for arbitrarily sequencing the data bits in a word stored in the line buffer in response to a clock signal ⁇ S , and a serial port 17 for outputting serially the bit designated by the serial pointer 16 to the outside or for writing the data inputted serially from outside into the line buffer.
  • a necessary number of external terminals are connected to the random port 14 and to the serial port 17.
  • the line buffer 16 includes a plurality of latch circuits such as static type flip-flops FF and a plurality of serial transfer gate transistors QS coupled between output terminals of latch circuits FF and a serial data line DL2 connected to a serial port 17.
  • the gates of the transistors QS are connected to the outputs of the serial pointer 16 and rendered conductive one by one.
  • a data transfer circuit 18 includes a plurality of transfer gate transistors QT connected between the outputs of the sense amplifiers SA and the inputs of the latch circuits FF in the line buffer 15 for simultaneously transferring data from the sense amplifiers SA to the latch circuits FF in response to an active level of a control signal DT.
  • the line buffer 15 of the serial access port SAM is connected to each input/output node of the sense and selection circuit 13 inside the random access port through the transfer circuit 18 and is designed so that all the transfer gates are opened only in a specific cycle called a "data transfer mode" in response to DT thereby to connect electrically the memory cell array 10 and the line buffer 15 to each other.
  • This data transfer mode represents a memory cycle in which the random access port is neither in the read cycle nor in the write cycle and during this period, the data from one word in the memory cell array 10 are altogether transferred to the line buffer 15 or the data for one word in the line buffer 15 are altogether transferred to the memory cell array 10.
  • FIG. 2 layout design such as shown in Fig. 2 is employed.
  • the memory cell array 10 of Fig. 1 is divided into two arrays 11a and 11b, which are disposed on the right and left.
  • a sense and selection circuit 13a and a line buffer 15a for the cell array 11a and those for the cell array 11b are provided to these cell arrays 11a and 11b, respectively, and a column decoder 12 and a serial pointer 16 are disposed at their center, as illustrated.
  • This arrangement is employed primarily in order to prevent deterioration of sensitivity of the sense amplifiers.
  • bit lines get elongated so that stray capacitance between bit lines increases and the load (the number of cells) of the sense amplifiers increases, thereby reducing sensitivity of the sense amplifiers. Furthermore, the pre-charge time of the bit line gets elongated and the response speed of the memory drops. For this reason, the cell array is divided into a plurality of blocks to reduce the length of the bit line and the sense amplifier is disposed for each block to prevent the drop of sensitivity. The pre-charge time is shortened to attain high speed response.
  • the row decoder is divided in accordance with the division of the cell array, too, but the row address is applied in common to the divided row decoders 11a, 11b and the two cell arrays 10a and 10b are simultaneously activated. Therefore, the cell arrays 11a and 11b in Fig. 2 together serve for one word of the memory cell array 10 shown in Fig. 1.
  • One of the requirements is low power consumption by low voltage driving.
  • FIG. 3 is a layout diagram of an improved dual-port memory chip.
  • the memory is divided as a whole into a plurality of memory planes MP1 - MP4 and only one arbitrary plane is selected in accordance with the content of the upper-order bit of the row address with the other planes being non-selected by a plane decoder 21.
  • this system is referred to as a "decoder division system”.
  • Each plane has the same memory layout as that of Fig. 2 and it is possible to regard a plurality of memories as together constituting one large capacity memory.
  • the upper-order two bits of the row address inputted to a row address buffer 20 are applied to a pre-decoder 21 and two row decoders 11a, 11b inside each plane are selected at the same time in accordance with their content.
  • the plains MP1 - MP4 are selected respectively when the upper-order bits are "00", “01", “10” and "11” through selection signals ⁇ P1 - ⁇ P4 .
  • the other bits of the row address other than these upper-order two bits are applied in common to the row decoders 11a, 11b in each plane.
  • only one plane is selected in accordance with the content of the upper-­order two bits of the row address.
  • the selected plane is activated and exhibits the memory operation but the rest of the planes which are under the non-selection state are inoperative. Therefore, the decoders and the sense amplifiers are inoperative in these inoperative planes and the memory is not refreshed. Therefore, power is consumed in only the selected plane and unnecessary power consumption in the other planes can be saved. Thus, the requirement for low power consumption can be satisfied.
  • the large-capacity dual-port memory can now operate with low power consumption but the following problems become remarkable and further improvements are necessary.
  • the number of line buffers as the nuclei of the dual-port memory must be increased in proportion to the number of division. Therefore, though the total area of the cell array does not much change as a whole due to division, the occupying area of the line buffers increases in proportion to the number of division. As a result, the problem develops in that the memory cell capacity is limited. Particularly because the serial access port having the line buffer must be able to operate asynchronously with the random access port containing the cell array, static type memory not requiring refresh are preferably used for the line buffer even if dynamic memory cells are used for the memory cells in the array. However, the area necessary for the static memory is by far greater than that of the dynamic memory.
  • CMOS complementary MOS transistor
  • each plane has two divided blocks.
  • the memory cell array 10a and its sense amplifier group 13a, its line buffer 15a and its row decoder 11a exist in the first block
  • the memory cell array 10b, its sense amplifier group 13b, its line buffer 15b and its row decoder 11b exist in the second block.
  • the memory cell array 10a and the line buffer 15a are connected by the first transfer circuit 18a and the memory cell array 10b and the line buffer 15b are connected by the second transfer circuit 18b. These first and second transfer circuits 18a, 18b are simultaneously turned ON/OFF by the control signal DT from a control circuit 22.
  • Fig. 4 is a chip layout diagram when the present invention is applied to a dual port memory having four planes MP1′ - MP4′.
  • Four planes MP1′ - MP4′ are formed on a single semiconductor chip and two memory arrays (block) 10a and 10b are disposed in each plane in the same way as in the prior art device.
  • one of the memory arrays (the array containing the memory cell array 10b, the row decoder 11b and the sense amplifier group 13b in Fig. 2) of the two memory arrays that have been disposed conventionally in the same plane MP1 is disposed in a different plane e.g. MP2′ from plane MP1′.
  • one of the blocks (the block containing the memory cell array 10c, the sense amplifier group 13c and the row decoder 10c in Fig. 1) of the two memory arrays that have conventionally been disposed in plane MP2 is disposed in plane MP1′.
  • one of the memory array 10f in the conventional plane MP3 and one of the memory arrays 10g in the conventional plane MP4 are substituted with each other and disposed as shown in the drawing.
  • the eight memory blocks in Fig. 1 may have the same circuit structure, substitution of the block itself is not necessary and only the change of wirings of the selection signal for selecting the decoders is necessary. Therefore, neither drastic change of circuit design nor any additional circuits for control are necessary and design as well as fabrication are extremely easy.
  • the line buffers (the portions represented by oblique lines in the drawing) in each plane can be made common by making the layout as described above. Therefore, the occupying area of the line buffers can be reduced by half as a whole in comparison with the prior art technique.
  • the upper two bits of the row address inputted to the row address register 20 are decoded by the pre-decoder 21.
  • the array 10a in plane MP1′ and the memory array 10b in plane MP2′ are selected in practice with all the other memory arrays 10c to 10h being under the non-selection condition.
  • the respective row decoders 11a and 11b are activated and the remaining bits other than upper two bits of the row address are commonly decoded thereby.
  • the respective random access port and serial access port become operative for these two activated memory arrays 10a and 10b and if the mode using the random access port is set, data transfer can be made between the memory cell arrays 10a and 10b and the external apparatus (e.g. CPU) through the random access port.
  • the data transfer mode is set, the data for one word are transferred to the line buffer of plane MP1′ through the sense amplifier group 13a in the memory array 10a and at the same time, the data for one word are transferred to the line buffer of plane MP2′ through the sense amplifier group 13b in the memory block 13b. Since the memory array 10c inside plane MP1′ and the memory array 10d inside plane MP2′ are inoperative during this period, they do not exert any influences on the line buffers.
  • the data are outputted one bit by one simultaneously and serially from the line buffers of planes MP1′ and MP2′ to the external apparatus (e.g. CRT or a liquid crystal display) through the respective corresponding serial ports. Since this operation is conducted asynchronously with the operation of the random access port, it is possible to execute random access and serial access in the overlapping arrangement.
  • the external apparatus e.g. CRT or a liquid crystal display
  • Fig. 5 shows the internal circuit block diagram of plane MP1′ shown in Fig. 5 as a typical example and the operation inside this plane in the data transfer mode will be explained in more detail.
  • the row decoder 11a of the memory array 10a is connected to the decoder selection signal line ⁇ P1 generated by a AND gate 51 and the row decoder 11c of the memory array 10c is connected to the decoder selection line ⁇ P2 generated by a AND gate 52.
  • a single line buffer 16-1 having storage bits of the same number of the columns of the blocks 10a and 10b is used in common for the memory arrays 10a and 10c in the plane MP1′.
  • Each of the sense amplifier groups 13a and 13c includes a plurality of sense amplifiers SA having inputs connected to the bit lines BL in the arrays 10a and 10c and a plurality of column selection transistors QR coupled between the outputs of the sense amplifiers SA and the data lines DL1a and DL1c coupled to the random ports 14a and 14c, respectively.
  • the column selection transistors QR of the sense amplifier groups 13a and 13c are supplied with the outputs of the column decoder 12 in common.
  • the line buffer 15-1 in the plane MP1′ includes a plurality of latch circuits FF and a plurality of transfer gate transistors QS connected between the outputs of the latch circuits FF and the serial data line DL2-1 connected to the serial port 17-1.
  • the transfer circuit 18a includes data transfer transistors QT connected between the outputs of the sense amplifiers SA in the group 13a and the inputs of the latch circuits FF while the transfer circuit 18c includes transistors QT connected between the outputs of sense amplifiers SA in the group 13c and the inputs of the latch circuits FF in the line buffer 15-1.
  • the numbers of the latch circuits, the transistor QR in the group 13a, the transistors QR in the group 13c, the transistors QT in the transfer circuits 18a and 18c are the same as the number of bit lines in the blocks 10a and 10c.
  • the transfer circuit 18a is enabled in response to a control signal DT1 when the row decoder 11a is enabled in response to ⁇ P1
  • the transfer circuit 18c is enabled in response to a control signal DT2 when the row decoder 11c is enabled in response to ⁇ P2 .
  • the column decoders 12 and the serial pointers 16 in the respective planes MP1′ - MP4′ operate simultaneously. However, it is also possible to operate the column decoders and the serial pointers of the selected planes e.g. MP1′ and MP2′.
  • the memory array 10a of plane MP1′ and 10b in MP2′ are simultaneously activated.
  • the signal DT1 is generated and the transfer gate circuit 18a for the memory array 10a of plane MP1′ and the transfer circuit 18c in the memory array 10b of plane MP2′ are simultaneously turned conductive. Since the signal DT2 is not made active at this time, the transfer gate circuit 18c for the memory array 10c of plane MP1′ and the transfer circuit 18d in the memory array 10d of plane MP2′ are turned OFF.
  • the line buffers 16-1 and 16-2 of the planes MP1′ and MP2′ are electrically connected to the memory cell arrays 10a and 10b, respectively while they are electrically cut off from other memory arrays 10c and 10d so that the line buffer can be used in common for two blocks in each plane.
  • the serial port too, can be used in common in each plane.
  • the transfer gate circuit 18 for connecting the line buffer 16 to the sense amplifiers SA are used in common for the two memory arrays 10a and 10c as shown in Fig. 7.
  • the sense amplifiers SA are used in common, each memory cell arrays 10a and 10b must be connected by separate transfer gate circuits 18a′ and 18c′. Therefore, a cell array selection signals ⁇ Ra and ⁇ Rc for selecting the transfer gate circuits 18a′ and 18c′ in accordance with which array is used must be provided.
  • the sense amplifier too, can be used commonly by making some changes of the circuit.
  • each line buffer in each plane in these embodiments has a two-word capacity, however, 4-bit data can be taken out serially and in parallel through the serial access port.
  • each line buffer of the two systems can be disposed very closely and adjacent to one another and moreover, both of them can be made operative simultaneously. In a high density chip layout, therefore, there are the possibility of the occurrence of mutual interference between the line buffers of the two systems and the possibility of signal leakage and inversion of bit data.
  • a circuit arrangement shown in Fig. 8 may be employed in order to solve such problems.
  • Fig. 8 is a layout diagram showing still another embodiment of the present invention.
  • the arrangement is made so as to select exclusively one of the memory arrays 10a, 10b, 10c, 10d of each plane and the other memory arrays 10e, 10f, 10g, 10h.
  • the output signal lines of the decorder 21 are arranged so that when the upper one bit of the row address is at the "H" level, the memory array 10a - 10d is selected and when it is at the "L” level, the memory array 10e - 10h is selected.
  • one of the memory arrays of each of four planes is simultaneously activated and 4-bit data can be taken out from the line buffers that are disposed at physically spaced-apart positions.
  • adverse influences due to mutual interference of the line buffers can be eliminated and this is extremely advantageous for high density integration.
  • no power is consumed by the memory block under the non-selection state in each plane, low power consumption is not impeded.
  • the present invention provides the excellent effect in that the occupying area of the line buffer can be reduced without requiring any complicated circuit or design change. Moreover, the advantages of the decoder division system and the cell array division system are not lost. Particularly, the present invention can reduce by half the area in comparison with the prior art in accordance with which the area corresponding to about 10 word lines is necessary for one line buffer. This can greatly contribute to the improvement in a greater memory capacity. A further greater effect can be obtained because not only the line buffer but also the sense amplifier and the serial port can be used in common as represented by various foregoing embodiments.
  • the present invention can be applied not only to the circuit arrangement wherein the memory cell array portion consists of dynamic memories and the line buffer consists of static memories but also to the circuit arrangement wherein both of them consist of static memories or dynamic memories.

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EP89100475A 1988-01-12 1989-01-12 Halbleiterspeicheranordnung mit serieller Zugriffsanordnung Expired - Lifetime EP0324470B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5232/88 1988-01-12
JP63005232A JPH0760595B2 (ja) 1988-01-12 1988-01-12 半導体メモリ

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EP0324470A2 true EP0324470A2 (de) 1989-07-19
EP0324470A3 EP0324470A3 (de) 1992-08-26
EP0324470B1 EP0324470B1 (de) 1995-03-29

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EP (1) EP0324470B1 (de)
JP (1) JPH0760595B2 (de)
DE (1) DE68921900T2 (de)

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DE4022149A1 (de) * 1990-01-19 1991-07-25 Mitsubishi Electric Corp Halbleiterspeichereinrichtung und betriebsverfahren fuer diese
EP0483723A2 (de) * 1990-11-01 1992-05-06 Nec Corporation Halbleiterspeicheranordnung mit einer Abfühlverstärkereinheit und auch mit einem Daten/Anzeigerregister gemeinsam benutzt zwischen mehreren Speicherzellenmatrizen
DE4133058A1 (de) * 1991-06-28 1993-01-07 Samsung Electronics Co Ltd Verfahren zur gemeinsamen nutzung eines speichers mit seriellem zugriff und einen entsprechenden schaltkreis eines doppelanschlussspeichers
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US5150327A (en) * 1988-10-31 1992-09-22 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and video signal processing circuit having the same
JPH07101554B2 (ja) * 1988-11-29 1995-11-01 三菱電機株式会社 半導体記憶装置およびそのデータ転送方法
JP2993671B2 (ja) * 1989-01-07 1999-12-20 三菱電機株式会社 半導体記憶装置
JP2664810B2 (ja) * 1991-03-07 1997-10-22 株式会社東芝 メモリセルアレイ分割型半導体記憶装置
EP0895162A3 (de) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern
JP3481263B2 (ja) * 1992-02-19 2003-12-22 株式会社リコー シリアル記憶装置
US5522054A (en) * 1993-09-13 1996-05-28 Compaq Computer Corporation Dynamic control of outstanding hard disk read requests for sequential and random operations
KR970004346B1 (ko) * 1994-01-26 1997-03-27 삼성전자 주식회사 듀얼포트를 가지는 그래픽램 및 그래픽램의 시리얼데이타 액세스방법
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US6067595A (en) * 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
KR100301046B1 (ko) * 1998-09-01 2001-09-06 윤종용 그래픽처리속도를향상시킬수있는듀얼포트를갖는고속싱크로너스메모리장치
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
JP2007200512A (ja) * 2006-01-30 2007-08-09 Renesas Technology Corp 半導体記憶装置
JP5706635B2 (ja) * 2010-06-24 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置及びその内部回路の制御方法

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4022149A1 (de) * 1990-01-19 1991-07-25 Mitsubishi Electric Corp Halbleiterspeichereinrichtung und betriebsverfahren fuer diese
US5566371A (en) * 1990-01-19 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of data transfer between memory arrays coupled to different data pins and operating method thereof
EP0483723A2 (de) * 1990-11-01 1992-05-06 Nec Corporation Halbleiterspeicheranordnung mit einer Abfühlverstärkereinheit und auch mit einem Daten/Anzeigerregister gemeinsam benutzt zwischen mehreren Speicherzellenmatrizen
EP0483723A3 (en) * 1990-11-01 1993-08-04 Nec Corporation Semiconductor memory device with sense amplifier unit as well as data register/pointer shared between plural memory cell arrays
DE4133058A1 (de) * 1991-06-28 1993-01-07 Samsung Electronics Co Ltd Verfahren zur gemeinsamen nutzung eines speichers mit seriellem zugriff und einen entsprechenden schaltkreis eines doppelanschlussspeichers
FR2702322A1 (fr) * 1993-03-01 1994-09-09 Texas Instruments France Mémoire à points d'interconnexion notamment pour la mise en communication de terminaux de télécommunication fonctionnant à des fréquences différentes.
EP0617530A1 (de) * 1993-03-01 1994-09-28 Texas Instruments France Aus einem Array von Dual-Port-FIFO-Speichern bestehender Querverbindungsspeicher
GB2308695A (en) * 1995-12-22 1997-07-02 Motorola Inc Memory system and memory element

Also Published As

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DE68921900T2 (de) 1995-12-21
DE68921900D1 (de) 1995-05-04
JPH01184693A (ja) 1989-07-24
EP0324470A3 (de) 1992-08-26
JPH0760595B2 (ja) 1995-06-28
US4937788A (en) 1990-06-26
EP0324470B1 (de) 1995-03-29

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