GB2308695A - Memory system and memory element - Google Patents
Memory system and memory element Download PDFInfo
- Publication number
- GB2308695A GB2308695A GB9526312A GB9526312A GB2308695A GB 2308695 A GB2308695 A GB 2308695A GB 9526312 A GB9526312 A GB 9526312A GB 9526312 A GB9526312 A GB 9526312A GB 2308695 A GB2308695 A GB 2308695A
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- Prior art keywords
- shift
- bit
- memory
- line
- coupled
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Description
MEMORY SYSTEM AND MEMORY ELEMENT
FOR A MEMORY SYSTEM
Field of the Invention
This invention relates to a memory system and a memory element for a memory system.
Background of the Invention
A number of applications perform bit by bit processing of multiple words stored in a memory array, and thus require that the multiple words be shifted out simultaneously from the memory array bit by bit. Such applications include, for example, comparing a given data word and a plurality of stored data words in order to find matching words or comparing between the stored words themselves to find the lowest or highest value, both of which are described in UK patent application GB-A-2277425.
One way of achieving such a bit by bit shifting function is to utilise a shift register coupled to the memory array. Each word is read one by one, bit by bit, into the shift register. Utilising a shift register increases the size of the memory system, although the increase is small. However, using a shift register requires a significant number of clock cycles to shift all the words from the memory array. The number of clock cycles is equal to m X n, where m is the number of words and n is the number of bits in a word.
Another known technique for providing such a shifting function is to build each memory element of the memory array as a master/slave type element. That is, the memory element comprises two typical memory bits, one memory bit being the master and the other memory bit being the slave.
The data bit stored in the master is shifted to the slave in one clock cycle. It therefore only takes n clock cycles to shift out all the bits in a word and hence n clock cycles to shift out all the words, where n is the number of bits in a word. Thus, such a technique does not suffer from the speed disadvantages of the shift register above but there is a significant increase in size of the memory array. A memory element comprising a master/slave type element would almost double the size of the memory array.
It would be desirable to provide an improved memory element and memory system that do not suffer from the speed and size disadvantages outlined above.
Summary of the Invention
In accordance with a first aspect of the present invention there is provided a memory element for a memory system for storing m words comprising n data bits, the memory element comprising:
a memory cell for storing a data bit; and
switching means coupled to a bit shift line and a shift control line and to the memory cell, the switching means being enabled in response to a shift control signal on the shift control line for coupling the data bit stored in the memory cell to the bit shift line.
In accordance with a second aspect of the present invention there is provided a memory system for storing m words comprising n data bits, the memory array comprising:
a plurality of memory elements arranged in an array of n columns and m rows, each of the plurality of memory elements comprising a memory cell for storing a data bit;
m bit shift lines, each of the m bit shift lines being coupled to each memory element in a respective one of the m rows; and
n shift control lines, each of the n shift control lines being coupled to each memory element in a respective one of the n columns,
wherein each of the plurality of memory elements further comprises switching means coupled to a respective bit shift line and a respective shift control line and to the respective memory cell, the switching means of each memory element in a respective column each being enabled in response to a shift control signal on the respective shift control line for coupling the data bit stored in the respective memory cell to the respective bit shift line, such that the data bits of the memory elements in the respective column are shifted out simultaneously on the m bit shift lines.
The memory element in accordance with the present invention thus enables the memory system 2 to function as an output shift register without having to use a dedicated shift register. Moreover, the present invention makes it possible to simultaneously shift out multiple words of the memory array bit by bit in n clock cycles, where n is the number of bits in a word, irrespective of the number of words in the memory array.
Preferably, the switching means of a memory element comprises a first transistor having a first current electrode coupled to the respective bit shift line, a control electrode coupled to receive the data bit stored in the memory element and a second current electrode; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a first supply line and a control electrode coupled to the respective shift control line, the second transistor being activated to provide a conduction path between the respective bit shift line and the first supply line when the switching means is enabled in response to the shift control signal.
Brief Description of the Drawings
A memory element in accordance with the present invention and a memory system in accordance with the present invention will now be described, by way of example only, with reference to the accompanying drawings in which:
FIG. 1 is a schematic block diagram of a memory system in accordance with the present invention;
FIG. 2 is a schematic circuit diagram of a memory element in accordance with the present invention, a plurality of such memory elements forming part of the memory system of FIG. 1;
FIG. 3 shows a representation of a shift control signal applied to the memory element of FIG. 2; and
FIG. 4 is an alternative precharge circuit for precharging the bit shift line of the memory element in accordance with the present invention.
Detailed Description
Referring firstly to FIG. 1, a memory system 2 in accordance with a preferred embodiment of the present invention comprises a memory array 4 for storing m words, each word comprising n data bits, where m and n are positive integers. Words are transferred between the memory array 4 and a data bus 6 via read/write data buffer 8. Read/write word select logic 10 provides word select signals to the memory array 4 via word select lines (R/W) to select a word of the memory array which is to be written to or read from.
The memory system 2 further comprises shift bit select logic 12 and shift logic 14. The shift bit select logic 12 has n outputs coupled respectively to n shift control lines 32. Each of the n shift control lines 32 being associated with a respective one of the n bits of the m words of the memory array 4. The shift logic 14 has m inputs coupled respectively to m bit shift lines 34. Each of the m bit shift lines 34 being associated with a respective one of the m words of the memory array 4. The shift bit select logic 12 and the shift logic 14 are both clocked by a shift clock signal provided at a clock input 16.
The memory array 4 comprises a plurality of memory elements, only one of which 20, is shown in FIG. 2. In the following description it will be assumed that memory element 20 is the first bit (1) of the first word (word~1). It will however be appreciated that memory array 4 comprises a plurality of memory elements 20 arranged in an array of m rows and n columns.
Memory element 20 comprises a memory cell 22 which in accordance with a preferred embodiment is a static Random Access Memory (RAM) cell 22 comprising a flip-flop arrangement 24 coupled to first bit line B1 and complementary first bit line B1 via transistors 26 and 28 respectively. The control electrodes of transistors 26 and 28 are coupled to the word select line Ray~1 of the first word (word~1).
The memory element 20 further comprises switching means 30 coupled to the respective bit shift line (first bit shift line~1), the respective shift control line (first shift control line~1) and to the respective memory cell 22. Preferably, the switching means 30 comprises a first transistor 36 and a second transistor 38. The first transistor 36 has a first current electrode coupled to the first bit shift line (bit shift line~1), a control electrode coupled to receive the data bit stored in the memory cell and a second current electrode. The second transistor 38 has a first current electrode coupled to the second current electrode of the first transistor 36, a second current electrode coupled to a first supply line, which in the preferred embodiment is at ground potential, and a control electrode coupled to the first shift control line (shift control line~1). Alternatively, the switching means 30 may be implemented as a logic gate.
The operation of the memory element and memory system in accordance with the invention will now be described with reference to FIGs.
1 and 2 and also to FIG. 3 which shows a representation of a shift control signal applied to the first shift control line (shift control line~1) of or the memory element 20.
In the preferred embodiment, the data bit stored in each memory element is shifted out onto the respective bit shift line in two phases: a precharge phase and a discharge phase.
For memory element 20, during the precharge phase the first bit shift line~1 is precharged via a precharge circuit 40 when the shift control signal applied to the first shift control line~1 is negated. In the preferred embodiment the precharge phase occurs when the shift control signal is a logic "0" (see 42 in FIG. 3). When the shift control signal is negated (44, in
FIG. 3), second transistor 38 is turned "off' (inactivated) with the result that the switching means 30 is disabled, the conduction path through the current electrodes of the first 36 and second 38 transistors is disabled and the first bit shift line~1 is precharged to the second supply line (V).
It will be appreciated that in order to precharge each of the m bit shift lines 34, m precharge circuits 40 are coupled respectively to the m bit shift lines 34 and also to a second supply line (V). Since the shift control signal applied to the first shift control line~1 is applied to all the memory elements in the first column, all the m bit shift lines 34 are precharged simultaneously.
During the discharge phase, the shift control signal on the first shift control line~1 is asserted, logic "1", (44 on FIG. 3). When the shift control signal is asserted, the second transistor 38 is rendered conductive (activated) with the result that the switching means 30 is enabled and the conduction path through the current electrodes of the first 36 and second 38 transistors is enabled. Since the stored data bit is applied to the control electrode of the first transistor 36, during the discharge phase the logic state of the data bit ("1" or "0") is transferred to the first bit shift line~1. Since the shift control signal applied to the first shift control lines is applied to all the memory elements in the first column, the data bits stored in all the memory elements in the first column are shifted out on the respective bit shift lines simultaneously. In each of the m rows (i.e. for each word), only one data bit is selected at a time and shifted out on the respective bit shift line.
The precharge circuit 40 may be a pull-up resistor 40, coupled between the second supply line (V), such as a 5 Volt supply line, and the first bit shift line~1 such that the first bit shift line~1 is precharge to the second supply line (V). It will be appreciated that in order to precharge each of the bit shift lines 34 in the memory array 4, a pull-up resistor is coupled to each of the m bit shift lines 34. Such pull-up resistors perform static precharging of the bit shift lines 34, which means that the pull-up resistors couple the bit shift lines 34 to the second supply line (V) until a shift control signal selects a column of memory elements and the data bits stored therein are transferred to the bit shift lines 34.
Alternatively, the precharge circuit 40 may comprise a precharge switch 40 formed by a transistor 48 having current electrodes coupled between a second supply line (V) and the first bit shift line~1 and a control electrode coupled to receive the shift control signals, which are applied to input 50 of the precharge circuit 40 as well as the shift control lines 32, via inverter 46. It will be appreciated that in order to precharge each of the bit shift lines 34 in the memory array 4, a precharge switch is coupled to each of the m bit shift lines 34. Since the precharge switches are enabled in response to the shift control signal, the precharge switches perform dynamic precharging of the bit shift lines 34, which means that the precharge phase and the discharge phase of the bit shift lines are timed by different clock phases.
It will be appreciated that the above description for memory element 20 applies to all the other memory elements in the memory array 4.
The present invention has been described, with reference to FIG. 2, wherein each memory element comprises a static RAM cell. It is not intended that the invention be limited solely to static RAM cells. The memory element may comprises any type of solid state memory cell, such as a dynamic RAM cell, a Read Only Memory (ROM) cell, an Electrically
Programmable Read Only Memory (EPROM) cell, or a flash EPROM cell.
In order to shift out bit by bit the m words from the memory array 4 in accordance with the preferred embodiment, the shift clock signal applied to the clock input 16 initiates the shifting process. In response to the shift clock signal, the shift bit select logic 12 sets a first output whereby the shift control signal is applied to the first shift control line~1 to initiate a precharge followed by a discharge of the bit shift lines 34. Each subsequent clock cycle of the shift clock signal, sets successive outputs of the shift bit select logic 12 so that shift control signals are applied to the shift control lines 32 in succession. At each clock cycle, the corresponding data bits are shifted simultaneously from all the m words on bit shift lines 34 to shift logic 14, which is also clocked by the shift clock signal. After n clock cycles of the shift clock signal, the shifting process is completed.
The memory element in accordance with the present invention thus enables the memory system 2 to function as an output shift register without having to use a dedicated shift register. Moreover, the present invention makes it possible to simultaneously shift out multiple words of the memory array bit by bit in n clock cycles, where n is the number of bits in a word, irrespective of the number of words in the memory array. The present invention is therefore quicker than the prior art dedicated shift register solution and is applicable to any word size and to any number of words in the memory array.
Assuming a regular memory array of m words of n data bits, the present invention adds 2 X n X m transistors and n + m conductor lines to the memory array in order to make it possible to simultaneously shift out multiple words from the memory array bit by bit. This involves a size penalty of only about a 1/3 of the size penalty of the known solution which uses master/slave type memory elements described above. Thus, the present invention completes the shift-out process in n clock cycles whilst having an improved size penalty over the prior art master/slave type elements.
The present invention provides an improved minimum cost memory system which allows for multiple words to be shifted out bit by bit simultaneously.
Claims (10)
1. A memory element for a memory system for storing m words comprising n data bits, the memory element comprising:
a memory cell for storing a data bit; and
switching means coupled to a bit shift line and a shift control line and to the memory cell, the switching means being enabled in response to a shift control signal on the shift control line for coupling the data bit stored in the memory cell to the bit shift line.
2. The memory element according to claim 1 wherein the switching means comprises:
a first transistor having a first current electrode coupled to the bit shift line, a control electrode coupled to receive the data bit stored in the memory cell and a second current electrode; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a first supply line and a control electrode coupled to the shift control line, the second transistor being activated to provide a conduction path between the bit shift line and the first supply line when the switching means is enabled in response to the shift control signal.
3. A memory system for storing m words comprising n data bits, the memory system comprising:
a plurality of memory elements arranged in an array of n columns and m rows, each of the plurality of memory elements comprising a memory cell for storing a data bit;
m bit shift lines, each of the m bit shift lines being coupled to each memory element in a respective one of the m rows; and
n shift control lines, each of the n shift control lines being coupled to each memory element in a respective one of the n columns,
wherein each of the plurality of memory elements further comprises switching means coupled to a respective bit shift line and a respective shift control line and to the respective memory cell, the switching means of each memory element in a respective column each being enabled in response to a shift control signal on the respective shift control line for coupling the data bit stored in the respective memory cell to the respective bit shift line, such that the data bits of the memory elements in the respective column are shifted out simultaneously on the m bit shift lines.
4. The memory system according to claim 3 wherein the switching means of a memory element comprises:
a first transistor having a first current electrode coupled to the respective bit shift line, a control electrode coupled to receive the data bit stored in the memory element and a second current electrode; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a first supply line and a control electrode coupled to the respective shift control line, the second transistor being activated to provide a conduction path between the respective bit shift line and the first supply line when the switching means is enabled in response to the shift control signal.
5. The memory system according to claim 3 or 4 further comprising:
shift bit select logic being coupled to receive a shift clock signal and having n outputs coupled respectively to the n shift control lines, the shift bit select logic being clocked by the shift clock signal to provide the shift control signal to each of the n shift control lines in succession; and
shift logic being coupled to receive the shift clock signal and having m inputs coupled respectively to the m bit shift lines, the shift logic being clocked by the shift clock signal to receive each of the n data bits of a word in succession on each of the m bit shift lines.
6. The memory system according to claim 3, 4 or 5 further comprising m precharge circuits coupled respectively to the m bit shift lines and to a second supply line for precharging the m bit shift lines to the second supply line, each of the m precharge circuits comprising a pull-up resistor.
7. The memory system according to claim 3, 4 or 5 further comprising m precharge circuits coupled respectively to the m bit shift lines and to a second supply line for precharging the m bit shift lines to the second supply line, each of the precharge circuits comprising a precharge switch, each precharge switch being enabled to precharge the respective bit shift line to the second supply line when the respective switching means is disabled and being disabled when the switching means is enabled.
8. The memory element according to claim 1 or 2 or the memory system according to claim 3, 4, 5, 6 or 7, wherein the memory cell of a memory element comprises any one of the following: a static RAM cell, a dynamic
RAM cell, a ROM cell, an EPROM cell, a flash EPROM cell.
9. A memory system substantially as hereinbefore described with reference to FIGs. 1, 2, 3 and 4 of the drawings.
10. A memory element for a memory system substantially as hereinbefore described with reference to FIG. 2 and 3 of the drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9526312A GB2308695A (en) | 1995-12-22 | 1995-12-22 | Memory system and memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9526312A GB2308695A (en) | 1995-12-22 | 1995-12-22 | Memory system and memory element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9526312D0 GB9526312D0 (en) | 1996-02-21 |
| GB2308695A true GB2308695A (en) | 1997-07-02 |
Family
ID=10785917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9526312A Withdrawn GB2308695A (en) | 1995-12-22 | 1995-12-22 | Memory system and memory element |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2308695A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2183374A (en) * | 1985-11-23 | 1987-06-03 | Stc Plc | Sequential access memory |
| EP0324470A2 (en) * | 1988-01-12 | 1989-07-19 | Nec Corporation | Semiconductor memory circuit with improved serial access circuit arrangement |
| US4985872A (en) * | 1989-06-23 | 1991-01-15 | Vlsi Technology, Inc. | Sequencing column select circuit for a random access memory |
| EP0547830A2 (en) * | 1991-12-19 | 1993-06-23 | Texas Instruments Incorporated | Circuitry and method for sequentially accessing a memory array |
-
1995
- 1995-12-22 GB GB9526312A patent/GB2308695A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2183374A (en) * | 1985-11-23 | 1987-06-03 | Stc Plc | Sequential access memory |
| EP0324470A2 (en) * | 1988-01-12 | 1989-07-19 | Nec Corporation | Semiconductor memory circuit with improved serial access circuit arrangement |
| US4985872A (en) * | 1989-06-23 | 1991-01-15 | Vlsi Technology, Inc. | Sequencing column select circuit for a random access memory |
| EP0547830A2 (en) * | 1991-12-19 | 1993-06-23 | Texas Instruments Incorporated | Circuitry and method for sequentially accessing a memory array |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9526312D0 (en) | 1996-02-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |