EP0166423B1 - Circuit intégré semi-conducteur comportant des transistors à effet de champ complémentaires - Google Patents

Circuit intégré semi-conducteur comportant des transistors à effet de champ complémentaires Download PDF

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Publication number
EP0166423B1
EP0166423B1 EP85107845A EP85107845A EP0166423B1 EP 0166423 B1 EP0166423 B1 EP 0166423B1 EP 85107845 A EP85107845 A EP 85107845A EP 85107845 A EP85107845 A EP 85107845A EP 0166423 B1 EP0166423 B1 EP 0166423B1
Authority
EP
European Patent Office
Prior art keywords
wirings
power supply
transistor forming
integrated circuit
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP85107845A
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German (de)
English (en)
Other versions
EP0166423A3 (en
EP0166423A2 (fr
Inventor
Ryuichi Hashishita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
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NEC Corp
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Publication date
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Publication of EP0166423A2 publication Critical patent/EP0166423A2/fr
Publication of EP0166423A3 publication Critical patent/EP0166423A3/en
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Publication of EP0166423B1 publication Critical patent/EP0166423B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a semiconductor integrated circuit employing complementary MOS transistors.
  • CMOS Complementary MOS
  • N-channel field effect transistors and P-channel field effect transistors are formed on different surface regions of a semiconductor substrate.
  • P-channel transistors are formed on a certain area of the substrate while a P-type well region is povided on another area of the substrate and N-channel transistors are formed on the well region.
  • the above certain region and the well region are adjacently located and power supply wirings are arranged both outer sides of the adjacent certain region and the well regions.
  • signal wirings for carrying logic signals are extended in the direction normal to that of the power supply wirings through the above two regions.
  • the power supply wirings are arranged in parallel and the signal wirings are also arranged in parallel in each wiring group, and hence design in the wiring is easy.
  • the signal wirings are extending beyond the power supply wirings from the transistor region and therefore the signal wirings inevitably overlap the power supply wirings. Therefore, in the case where the power supply wirings are made of low-resistive metal, the signal wirings are usually made of polycrystalline silicon in order to achieve the multi-layer wirings with ease.
  • the resistance of the polycrystalline silicon is relatively large and hence the signal transmission time through the signal wirings is large, resulting in low speed operation.
  • the above overlap of the signal wirings on the power supply wirings and the formation of the power supply wirings outside the transistor region make it difficult to form the circuit with the high integration structure.
  • a semiconductor integrated circuit according to the preamble part of claim 1 is known from JP-A-59 63 754.
  • this device a N-type region and a P-type region surrounding the N-type region are formed and a plurality of signal wirings are extending through those regions in parallel with a power supply wiring.
  • a further semiconductor device is disclosed in US-A-4 035 826 in which a P-channel field effect transistor and a N-channel field effect transistor are formed in a first region surrounded by a N+-region and in a second region surrounded by a P+-region, respectively, and an input wiring and an output wiring are extending over the first and second regions.
  • both of the first and second power supply wirings pass over the first and second transistor forming regions in parallel in the direction perpendicular to that of the first and second transistor forming regions. Therefore, since both of the first and second transistor forming regions overlap with the first and second power supply wirings, any particular area on the substrate is not necessitated for the arrangement of the power supply wirings, and the transistors can be connected to either one or both of the power supply wirings with ease within the respective transistor forming regions. Thus, a high integration rate of the integrated circuit can be achieved. Furthermore, the internal wirings formed on the different level layers extend over both transistor forming regions to serve as the gates of the field effect transistors and extend in the same direction as that of the transistor forming regions. Therefore, the gates themselves of the transistor and the wirings connected between the gates and the single wirings can be formed by the internal wirings at the same time. Therefore, the field effect transistors can be formed over the transistor forming regions efficiently with high density structure.
  • two rectangular regions 1 and 2 are defined on a semiconductor substrate.
  • the region 1 is, for example, of an N-type conductivity region and the region 2 is of a P-type conductivity region.
  • P-channel field effect transistors are formed on the region 1 while N-channel field effect transistors are formed on the region 2.
  • a power supply wiring V1 is provided in a lateral direction and another power supply V2 is provided in the lateral direction along the lower side periphery 12 of the region 2.
  • Signal wirings S1 to S4 for carrying logic signals are provided in a vertical direction across the regions 1 and 2 as illustrated. In the drawing, an arrow with a reference "F" indicates the flow of logic processing in the circuit.
  • the power supply wirings V1 and V2 are formed on independent areas which are separate from the regions 1 and 2. Therefore, it has been difficult to fabricate the integrated circuit in a high-density structure. Furthermore, the signal wirings S1 to S4 are required to intersect with the power supply wiring V1 and hence the signal wirings S1 to S4 must be formed by a different layer of conductive material.
  • the power supply wirings V1 and V2 are formed of a highly conductive metal e.g. aluminium and the signal wirings S1 to S4 are formed of a polycrystalline silicon. The resistance of the polycrystalline silicon is relatively and hence signal transmission time through the signal wirings inevitably large, resulting in low speed operation.
  • CMOS integrated circuit Referring to fig. 2, a basic structure of a CMOS integrated circuit according to the present invention is explained.
  • the portions corresponding to those in fig. 1 are denoted by the same references employed in fig. 1.
  • the power supply wirings V1 and V2 instead of arranging the power supply wirings V1 and V2 in the lateral direction along the peripheries 11 and 12 in fig. 1, the power supply wirings V1' and V2' are arranged in the vertical direction on both the regions 1 and 2. Also, the power supply wirings V1' and V2' are extending in parallel with the signal wirings S2 to S4.
  • the power supply wirings V1' and V2' are formed on the transistor regions 1 and 2, the area solely required for the wirings V1' and V2' are not necessary.
  • the power supply wirings V1' and V2' and the signal wirings S1 to S4 are arranged in parallel and both of the wirings have no overlapping portion therebetween, and hence the signal wirings S1 to S4 can be formed of the same wiring layer as the power supply wirings V1' and V2'.
  • both of the signal wirings S1 to S4 and the power supply wirings V1' and V2' can be made by the same highly conductive material such as aluminium. Accordingly, the signal wirings S1 to S4 can be provided with low impedance as well as the power supply wiring.
  • Fig. 3 shows one example of a logic diagram of the circuit to be realized by the embodiment.
  • the logic circuit to be fabricated in this embodiment includes a NAND gate G1 receiving signals S1 and S2, an OR gate G2 receiving the signals S1 and S2, a NAND gate G3 receiving the outputs of the gates G1 and G2, and a NAND gate G4 receiving signals S3 and S4 and the output of the gate G3.
  • Fig. 4 shows a schematic circuit diagram of the logic circuit of fig. 3.
  • an N-type conductivity region 7 and a P-type conductivity region 2 are adjacently provided.
  • P-channel transistors are formed on the region 7 while N-channel transistors are formed on the region 2.
  • a wiring 61 made of aluminium serves as the V5 line and is extended in the vertical direction along and on the left side peripheries of the regions 1 and 2.
  • a wiring 63 made of aluminium also serves as the V1' and is arranged in the vertical direction along and on the right side peripheries of the regions 1 and 2.
  • An aluminium wiring 62 serves as the V2' line and is extending in the vertical direction through the center parts of the regions 1 and 2.
  • Wirings 64 to 67 made of aluminium serve as the signal input lines S1 to S4, respectively and are extending in the vertical direction.
  • the wiring 64 is connected to a polycrystalline silicon wiring 73 serving as gates of the P-channel transistors Q1 and Q5 through a contact 102 and connected to a polycrystalline silicon wiring 76 serving gates of the N-channel transistors Q3 and Q9 through a contact 121.
  • the wiring 65 is connected to a polycrystalline silicon wiring 74 serving as the gates of the P-channel transistors Q2 and Q6 through a contact 104 and connected to a polycrystalline silicon wiring 79 serving as the gates of the N-channel transistors Q4 and Q10 through a contact 109.
  • the wiring 66 is connected to an polycrystalline silicon wiring 80 serving a gate of the P-channel transistor Q12 and a gate of the N-channel transistor Q15 through a contact 114.
  • the wiring 67 is connected to a polycrystalline silicon wiring 81 serving as a gate of the P-channel transistor Q11 through a contact 120 and to a polycrystalline silicon wiring 82 serving as a gate of the N-channel transistor Q16
  • An aluminium wiring 68 performs an internal connection connecting the commonly connected sources of Q1 and Q2 to gates of the transistors Q7 and Q8 via a contact 103, a polycrystalline silicon wiring 75, a contact 107 and a polycrystalline wiring 78.
  • An aluminium wiring 72 connects the drains of the transistors Q14, Q15 and Q16 to form an output terminal OUT.
  • the power wiring lines 61 and 63 are coupled to the P-type diffusion regions 51 and 51' via contacts 101 and 119, respectively.
  • the power supply wiring 62 is connected to an N-type diffusion region 52 in the region 2 via contacts 113.
  • Fig. 6 shows a pattern of the diffusion regions 51, 51' and 52 for easier understanding.
  • the power supply wirings 61, 62 and 63 (V1', V2') are provided on the transistor forming regions 1 and 2 and hence any special area solely required for the wirings V1', V2 ⁇ are not necessary.
  • the signal wirings 64 to 67 are formed in parallel with the power wirings 61 to 63 and of the same conductive layer (aluminium). Therefore, the signal wirings 64 to 67 can be provided with low impedance characteristics.
  • the semiconductor integrated circuit which can be fabricated at high-density and can operate at a high speed, is obtained.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Claims (3)

  1. Un circuit intégré semi-conducteur comprenant un
    substrat semi-conducteur (10),
    Une première région de formation des transistors (1) d'un premier type de conductivité allongée au moins dans une première direction,
    Une seconde région de formation des transistors (2) d'un second type de conductivité allongée au moins dans ladite première direction.
    Une pluralité de premiers transistors à effet de champ (Q1, Q2, Q7, Q11, Q13) formés dans la dite première région de formation des transistors (1), une pluralité de seconds transistors à effet de champ (Q3, Q8, Q10, Q14, Q16) formés dans ladite seconde région de formation des transistors (2), un premier et un second conducteurs d'alimentation (V2, V1') s'étendant sur ledit substrat semi-conducteur (10),
    Une pluralité de fils de signalisation (S1-S4) passant sur lesdites première et seconde régions de formation des transistors (1,2) dans la même direction que lesdits premier et second conducteurs d'alimentation (V2', V1'), un premier moyen pour connecter électriquement lesdits premiers et seconds tansistors à effet de champ auxdits fils de signalisation (S1-S4), et lesdits fils de signalisation (S1-S4) étant formés à un premier niveau de couche de câblage sans se chevaucher, caractérisé en ce que lesdites première et seconde régions de formation des transistors sont adjacentes et parallèles l'une à l'autre chacun desdits premier et second conducteurs d'aluminium (V2', V1) passent au-dessus desdites première et seconde régions de formation de transistors (1,2) de manière parallèle et dans une seconde direction perpendiculaire à ladite première direction, et en ce que ledit premier moyen comprend une pluralité de conducteurs internes (73-82) formés sur lesdites première et seconde régions de formation des transistors (1,2) et ayant des parties s'étendant dans ladite première direction et servant de portes pour lesdits premiers et seconds transistors.
  2. Le circuit intégré semi-conducteur conformément à la revendication 1, caractérisé en ce que lesdits conducteurs d'alimentation (V2' , V1') et lesdits fils de signalisation S1-S4) sont formés d'aluminium en ce que lesdits conducteurs internes (73 - 82) sont formés de silicium à polycristaux.
  3. Le circuit intégré semi-conducteur conformément à la revendication 1, caractérisé en ce que ledit premier conducteur d'alimentation (V2') s'étend le long sensiblement des parties centrales desdites première et seconde régions de formation des transistors (1,2) et ledit second conducteur d'alimentation (V1') est disposé le long d'une périphérie desdites première et seconde régions de formation des transistors, et en ce que un troisième conducteur d'alimentation (V1') est en outre prévu et s'étendant dans ladite seconde direction le long de l'autre périphérie desdites première et seconde régions de formation des transistors (1,2)
EP85107845A 1984-06-26 1985-06-25 Circuit intégré semi-conducteur comportant des transistors à effet de champ complémentaires Expired - Lifetime EP0166423B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59131474A JPS6110269A (ja) 1984-06-26 1984-06-26 半導体集積回路
JP131474/84 1984-06-26

Publications (3)

Publication Number Publication Date
EP0166423A2 EP0166423A2 (fr) 1986-01-02
EP0166423A3 EP0166423A3 (en) 1986-11-26
EP0166423B1 true EP0166423B1 (fr) 1991-02-27

Family

ID=15058814

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85107845A Expired - Lifetime EP0166423B1 (fr) 1984-06-26 1985-06-25 Circuit intégré semi-conducteur comportant des transistors à effet de champ complémentaires

Country Status (4)

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US (1) US4716450A (fr)
EP (1) EP0166423B1 (fr)
JP (1) JPS6110269A (fr)
DE (1) DE3581842D1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056034Y2 (fr) * 1986-04-16 1993-02-17
JPH0822492B2 (ja) * 1986-12-26 1996-03-06 松下電器産業株式会社 プリント基板保管箱搬送方法
US5410173A (en) * 1991-01-28 1995-04-25 Kikushima; Ken'ichi Semiconductor integrated circuit device
JPH04340252A (ja) * 1990-07-27 1992-11-26 Mitsubishi Electric Corp 半導体集積回路装置及びセルの配置配線方法

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US3599010A (en) * 1967-11-13 1971-08-10 Texas Instruments Inc High speed, low power, dynamic shift register with synchronous logic gates
US4035826A (en) * 1976-02-23 1977-07-12 Rca Corporation Reduction of parasitic bipolar effects in integrated circuits employing insulated gate field effect transistors via the use of low resistance substrate contacts extending through source region
JPS5526680A (en) * 1978-08-16 1980-02-26 Mitsubishi Electric Corp Semiconductor integrated circuit
JPS5591162A (en) * 1978-12-27 1980-07-10 Fujitsu Ltd Semiconductor device
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JPS5843568A (ja) * 1981-09-09 1983-03-14 Nec Corp 相補型絶縁ゲ−ト電界効果半導体メモリ装置
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Title
PATENT ABSTRACTS OF JAPAN, vol. 8, no. 167 (E-258)[1604], 2nd August 1984 & JP-A-59-63 754 *

Also Published As

Publication number Publication date
EP0166423A3 (en) 1986-11-26
JPS6110269A (ja) 1986-01-17
JPH0352225B2 (fr) 1991-08-09
EP0166423A2 (fr) 1986-01-02
DE3581842D1 (de) 1991-04-04
US4716450A (en) 1987-12-29

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