JPH0434309B2 - - Google Patents
Info
- Publication number
- JPH0434309B2 JPH0434309B2 JP57065021A JP6502182A JPH0434309B2 JP H0434309 B2 JPH0434309 B2 JP H0434309B2 JP 57065021 A JP57065021 A JP 57065021A JP 6502182 A JP6502182 A JP 6502182A JP H0434309 B2 JPH0434309 B2 JP H0434309B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- basic cells
- gate electrode
- fixed
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6502182A JPS58182242A (ja) | 1982-04-19 | 1982-04-19 | 半導体集積回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6502182A JPS58182242A (ja) | 1982-04-19 | 1982-04-19 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58182242A JPS58182242A (ja) | 1983-10-25 |
JPH0434309B2 true JPH0434309B2 (fr) | 1992-06-05 |
Family
ID=13274898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6502182A Granted JPS58182242A (ja) | 1982-04-19 | 1982-04-19 | 半導体集積回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58182242A (fr) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60110137A (ja) * | 1983-11-18 | 1985-06-15 | Sanyo Electric Co Ltd | 半導体装置 |
US4910574A (en) * | 1987-04-30 | 1990-03-20 | Ibm Corporation | Porous circuit macro for semiconductor integrated circuits |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
SG10201608214SA (en) | 2008-07-16 | 2016-11-29 | Tela Innovations Inc | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621364A (en) * | 1979-07-31 | 1981-02-27 | Fujitsu Ltd | Manufacture of semiconductor integrated circuit |
-
1982
- 1982-04-19 JP JP6502182A patent/JPS58182242A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621364A (en) * | 1979-07-31 | 1981-02-27 | Fujitsu Ltd | Manufacture of semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS58182242A (ja) | 1983-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5384472A (en) | Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density | |
EP0098163B1 (fr) | Puce comprenant une matrice de portes | |
JP2912174B2 (ja) | ライブラリ群及びそれを用いた半導体集積回路 | |
JPH0434309B2 (fr) | ||
JPH03165061A (ja) | 半導体集積回路装置 | |
JPH0480538B2 (fr) | ||
JP2822781B2 (ja) | マスタスライス方式半導体集積回路装置 | |
US4951111A (en) | Integrated circuit device | |
EP0119059B1 (fr) | Circuit intégré semi-conducteur comportant une structure de matrice de portes | |
JPH0252428B2 (fr) | ||
JPS58169937A (ja) | 半導体集積回路装置 | |
JPH0120539B2 (fr) | ||
JPH10173055A (ja) | セルベース半導体装置及びスタンダードセル | |
JPH0630377B2 (ja) | 半導体集積回路装置 | |
JP2000223575A (ja) | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 | |
JPH0371789B2 (fr) | ||
JP3972018B2 (ja) | 半導体集積回路装置 | |
JPH0122736B2 (fr) | ||
JPS5972742A (ja) | マスタスライスlsiのマスタ方法 | |
JPH0230163A (ja) | マスタスライス型半導体集積回路装置およびその製造方法 | |
JPH073863B2 (ja) | 半導体集積回路 | |
JPH0316790B2 (fr) | ||
JP2522678B2 (ja) | Cmos集積回路装置 | |
JPH0563944B2 (fr) | ||
JPS62263653A (ja) | 半導体集積回路装置の製造方法 |