Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K9/00—Screening of apparatus or components against electric or magnetic fields
  • H05K9/0007—Casings
  • H05K9/002—Casings with localised screening
  • H05K9/0039—Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/647—Resistive arrangements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
  • H01L2224/0555—Shape
  • H01L2224/05552—Shape in top view
  • H01L2224/05554—Shape in top view being square
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/4805—Shape
  • H01L2224/4809—Loop shape
  • H01L2224/48091—Arched
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
  • H01L2224/491—Disposition
  • H01L2224/4912—Layout
  • H01L2224/49171—Fan-out arrangements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
  • H01L2224/491—Disposition
  • H01L2224/4912—Layout
  • H01L2224/49175—Parallel arrangements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/42—Wire connectors; Manufacturing methods related thereto
  • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/42—Wire connectors; Manufacturing methods related thereto
  • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01039—Yttrium [Y]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01057—Lanthanum [La]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12042—LASER
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19041—Component type being a capacitor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3025—Electromagnetic shielding
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/3447—Lead-in-hole components

Definitions

• the present invention relates to a device for protecting a component and / or an electronic circuit against disturbances (voltages) generated by an external electromagnetic field, such as the so-called EMP wave due to atomic or nuclear decay.
• the present invention relates to a protection device making it possible to avoid the above drawbacks and, this, by draining the parasitic charges towards the exterior at each of the connections of the protected element.
• the subject of the invention is a device for protecting an electronic device against an external electromagnetic field, comprising electrical connection means, the conductivity of which increases under the effect of the electro field. external magnetic, between each of the output connections of the electronic device and an evacuation and / or a reservoir of the charges created by the field.
• FIG. 4 a third embodiment of the device according to the invention, also suitable for a "chip carrier" type housing;
• an electronic component C is therefore shown, for example provided with four connection pads (1, 2, 3 and 4) which are each conventionally connected by a conductive wire (10) to conductors, for example constituted by the tracks of the base of the housing B (ceramic or plastic) which carries the component, marked respectively 11, 12, 13 and 14.
• connection 3 and the track 13 which constitute the mass of the whole device.
• a frame is provided enclosing the component.
• sant near the latter, consisting of a layer V of a varistor material covered with a conductive electrode E, for example of a width slightly less than that of the layer V; this frame V is deposited on the support B and on the conductors 11 to 14.
• the electrode E is connected to the track 13 by a tongue 15.
• a varistor material which generally consists of oxide of doped zinc (by oxides of bismuth, cobalt, chromium, molybdenum, antimony, etc.) has a non-linear resistance: it is not electrically conductive when the potential difference applied to it does not exceed a certain voltage threshold (V C ), and it becomes after this threshold.
• This phenomenon being due to a field effect, the switching between the conductive state and the non-conductive state is very fast (it can be equal to or less than 1 ns).
• a material can be deposited in any known way: for example screen-printed on the support B of the component C when the latter is made of ceramic or else deposited, by sputtering for example, when this support is plastic.
• the threshold voltage V C of a varistor is a function of its thickness and can therefore be chosen as a function of the intensities which can be expected for the disturbing electromagnetic fields, when 'they are known.
• the threshold V C must be greater than the highest of the working voltages of the component C; to constitute an effective protection, it is clear that this voltage V C must however be lower than the breakdown voltage of the component and, preferably, as close as possible to its working voltage.
• technological considerations of manufacturing tolerance on the thickness of the layer constituting the varistor can lead to choosing V C of the order of two to three times the highest working voltage of the component.
• the value chosen for V C can be of the order of 30 volts, which is a voltage lower than the breakdown voltage of most current electronic components.
• an advantage of the protection device according to the invention is that, in addition to allowing effective protection, it is capable of being integrated on the support of the component.
• FIG. 2 shows, seen from above, a practical embodiment of the device according to the invention in a "chip carrier" type housing. It will be recalled that such a housing is essentially characterized by the absence of connection pins, which are replaced by metal deposits.
• FIG. 3 which is a partial sectional view taken along the axis XX of FIG. 2, the metallizations such as 11 and the mass metallization 13 are deposited directly on the CC substrate.
• the metallizations 11 are covered by the layer of varistor material V which surrounds the component C, except at the level of the ground connection 13.
• the electrode E covers the layer V and extends over the ground track 13, thus making the connection electric between elements E and 13.
• FIG. 4 shows another embodiment of the device according to the invention, also suitable for a "chip carrier” type housing but also comprising a capacity integrated in the substrate of the housing.
• the metallization 22 forms one of the reinforcements of a capacitor whose dielectric is formed by the DC substrate and the other reinforcement by a metallization 21 deposited on the other face of the substrate; the metallization 21 is connected to the ground connection 13.
• This embodiment has the advantage of allowing, by the capacity thus interposed, to store on site at least a fraction of the charges created by the external electromagnetic field, in order to avoid too great a transfer of charges to the mass which is in turn liable create disturbances, for example a parasitic voltage by inductive induction.
• it is known to integrate capacities on the substrate of a "chip carrier" type housing, which is described in particular in patent applications No. 79-11852, 80-18927 and 80- 26076, all three on behalf of THOMSON-CSF.
• the preceding storage capacity may or may not be confused with the decoupling capacities described in the aforementioned patent applications.
• FIGS 5, 6 and 7 show three embodiments of the device according to the invention, applied to the protection of one or more electronic circuits mounted on the same card (printed circuit or ceramic).
• FIG 5 there is shown the end of a card S supporting one or more electronic components or circuits (not shown), seen at its connection end, that is to say the one where it ends in conductive tracks intended to cooperate with other cards via connectors.
• These tracks are for example of two kinds, on the one hand two identified ground tracks, respectively 31 and 32 located at the two ends of the card S and, on the other hand, tracks 33 ensuring the supply and the inputs-outputs of signals from the various circuits and components carried by the S card.
• this card S further carries a layer in the form of a strip of varistor material marked V S , formed and deposited on the end of the tracks 33 advantageously in the same way as the frame V of the preceding figures, and covered by an electrode E S which is in electrical contact with the or, in this case, the tracks (31 and 32) connected to the ground of the device.
• the varistor material V S can be deposited by screen printing or sputtering, etc.
• this protection device located at the level of the card S is identical to that which has been described for a single component previously, namely that when a disturbing external electromagnetic field is of sufficient intensity, the material constituting the layer V S becomes conductive and the charges created outside the card and arriving via the connections 33 are found, via the electrode E S then in electrical contact with them, discharged to ground therefore, by connections 31 and 32, cannot reach the circuits carried by the card, thus ensuring the protection sought.
• this protection device described in FIG. 5 can be used cumulatively with protection devices as described in the preceding figures at the level of each of the electronic components or circuits used on the card.
• FIG. 6 represents an alternative embodiment of the protection device for an electronic card.
• This card also carries an elongated plate 34, covering substantially the entire edge of the card S, interposed on connections 32 and 33.
• This plate 34 is preferably made of ceramic and carries the varistor layer V S and the electrode E S , preferably deposited by screen printing on the plate 34, as well as electrodes 36 and 35 ensuring electrical continuity on the wafer 34 between the tracks 32 and 33 of the card S respectively.
• the connections are for example made in FIG. 6 by welded connection wires 37 or, as shown in FIG. 7, by brazed half-tro ⁇ s 38 of the type of half-holes for "chip carrier" boxes.
• This variant allows, because of the interposition of a ceramic plate 34, to deposit the varistor material V S by a screen printing technique when the. card S is a printed circuit board which is incompatible with this technique.
• Figures 8, 9 and 10 show three embodiments of the device according to the invention applied to a card connector carrying electronic circuits or components.
• FIG 8 there is shown in section a connector by its connection pins 51 emerging through holes in an insulating base CT.
• a metallization E C1 has been deposited in electrical contact with a solder 53 joining it to a pin 51 located on the right in the diagram; this metallization E C1 is partially covered by a layer of varistor material V C itself covered by an electrode E C2 which is without electrical contact with the electrode E C1 but joined to another pin 51, on the diagram situated to the left of the same element of the CT base, by a solder 54.
• this device is analogous to the previous devices, namely that the varistor material V C is chosen and dimensioned so that it is insulating in the absence of an external electromagnetic disturbance field: in this way, the different pins 51 are without electrical contact with each other, in a conventional manner.
• the varistor material V C becomes conductive and it appears that two successive pins 51 are in electrical contact through successively the solder 54, a first conductive layer E C2 , the varistor material V C become conductor, of a second layer E C1 and finally of a second solder 53. It appears as above that the charges created by the disturbing field therefore do not have the possibility of passing through the connector but are discharged for example towards one of the pins 51 connected to earth.
• this protection device at the connector can be used cumulatively with protection at the level of the card and protection at the level of the circuit or component itself.
• FIG. 9 represents an alternative embodiment of FIG. 8.
• the connector represented by its connection pins 51 and its insulating base CT. Between two successive pins 51 are deposited on the same face of the CT insulator two metallizations E C3 and E C4 without electrical contact but located at the same level. On the electrodes E C3 , E C4 and between them is placed a layer of varistor material V C. The electrical connection with the pins 51 is made by two solders 54 and 53 respectively connecting the electrodes E C3 and E C4 to their respective pins 51.
• the operation is identical to what has been described previously. The only difference is technological: in fact, the electrodes E C3 and E C4 can be deposited in a single operation, the space between them being produced by laser engraving.
• FIG. 10 represents another embodiment of the device according to the invention applied to an electronic circuit board connector which includes the integration of a capacitor, in a manner similar to what has been described in FIG. 4.
• connection pins 51 as well as the insulating base CT and, for example, the electrodes E C3 and E C4 and the varistor material V C as described in Figure 9.
• the other face of the insulating layer CT further comprises an electrode marked 55 extending for example over the entire surface between two pins 51; in addition, the solders making the electrical connection with the connection pins 51 are slightly modified: in fact, a pin 51 is either connected on either side to the metallizations 55, or to the metallizations situated on the other face, E C3 or E C4 .

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Thermistors And Varistors (AREA)
• Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
• Credit Cards Or The Like (AREA)
• Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
• Emergency Protection Circuit Devices (AREA)

Applications Claiming Priority (2)

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• 1982
  • 1982-05-14 FR FR8208489A patent/FR2527039A1/fr active Granted
• 1983
  • 1983-05-10 WO PCT/FR1983/000091 patent/WO1983004157A1/fr not_active Application Discontinuation
  • 1983-05-10 JP JP58501559A patent/JPS59500845A/ja active Pending
  • 1983-05-10 US US06/571,554 patent/US4559579A/en not_active Expired - Fee Related
  • 1983-05-10 EP EP83901382A patent/EP0108098A1/fr not_active Withdrawn

Non-Patent Citations (1)

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