EP0055451A2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung Download PDF

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Publication number
EP0055451A2
EP0055451A2 EP81110659A EP81110659A EP0055451A2 EP 0055451 A2 EP0055451 A2 EP 0055451A2 EP 81110659 A EP81110659 A EP 81110659A EP 81110659 A EP81110659 A EP 81110659A EP 0055451 A2 EP0055451 A2 EP 0055451A2
Authority
EP
European Patent Office
Prior art keywords
power supply
battery
memory
semiconductor memory
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81110659A
Other languages
English (en)
French (fr)
Other versions
EP0055451A3 (en
EP0055451B1 (de
Inventor
Miyauchi Katsuki
Kudo Tetsuichi
Minato Osamu
Masuhara Toshiaki
Uetani Yoshio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Maxell Ltd
Original Assignee
Hitachi Ltd
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Maxell Ltd filed Critical Hitachi Ltd
Publication of EP0055451A2 publication Critical patent/EP0055451A2/de
Publication of EP0055451A3 publication Critical patent/EP0055451A3/en
Application granted granted Critical
Publication of EP0055451B1 publication Critical patent/EP0055451B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/05—Accumulators with non-aqueous electrolyte
    • H01M10/056—Accumulators with non-aqueous electrolyte characterised by the materials used as electrolytes, e.g. mixed inorganic/organic electrolytes
    • H01M10/0561—Accumulators with non-aqueous electrolyte characterised by the materials used as electrolytes, e.g. mixed inorganic/organic electrolytes the electrolyte being constituted of inorganic materials only
    • H01M10/0562—Solid materials
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/474—Batteries in combination with leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • This invention relates to a semiconductor memory device.
  • ROMs read only memories
  • EEPROM electrically erasable and programable read only memory
  • EPROM electrically programable read only memory
  • the access time is as long as 450 ns, which is about 4 times the access time of a random access memory (RAM) having an equal capacity.
  • RAM random access memory
  • RAM random access memory
  • ROM read only memory
  • the memory cell of the RAM has a single data line as in the ROM, the operation thereof is dynamic and various signals can be generated in parallel. Since data can be sensed and amplified at high speed with the signals, the operating speed can be enhanced.
  • the access time of the RAM is about 1 ⁇ 4 as compared with that of the ROM.
  • the writing time is substantially the same as the access time.
  • the-RAMs have the disadvantage that they cannot avoid becoming volatile memories. More specifically, in case of a dynamic RAM, a one-transistor MOS structure is the mainstream at present. With this structure, unless the memory is refreshed once every 2 msec., the memory content cannot be retained. When the power supply is turned “off", naturally the memory content disappears. In case of a static RAM whose memory cell is a flip-flop structure, the refreshing becomes unnecessary. However, when the power supply is turned “off” so that no current is supplied to the memory cell, the memory content cannot be retained as in the dynamic RAM.
  • the semiconductor memory of this invention for accomplishing the object is a nonvolatile semiconductor memory containing a power supply-element, in which the power supply element such as a battery capacitor or solar battery,is installed in a volatile semiconductor memory to render the latter nonvolatile.
  • the fields of utilization of the nonvolatile semiconductor memory according to this invention are a memory part of a computer terminal equipment which uses a single small-sized power source, a microcomputer or a small-sized desk calculator which requires a nonvolatile memory, etc.
  • a passivation layer 8 of Si 3 N 4 or the like is disposed on the surface of a C-MOS static RAM which is constructed of a silicon substrate 1 of the n -type conductivity, a well region 2 of the p-type conductivity , n + -type conductivity regions 3, p + -type conductivity regions 4, an.insulating layer 5, metal interconnections 6, 6', 6" and 6"' and gate electrodes 7 and 7 1.
  • a conductive layer 9 for the anode or cathode of a battery there are successively formed a conductive layer 9 for the anode or cathode of a battery, -a solid electrolyte layer 10 and a conductive layer 11 for the cathode or anode of the battery.
  • TiS 2 , VSe 2 or the like is used as the anode material of the battery, while an Li-Al alloy, Li-Si alloy or the like is used as the cathode material.
  • Used as the substance of the solid electrolyte is an Li 4 SiO 4 -Li 3 PO 4 compound, Li 3 N-LiI compound, Li 3 N-LiI-LiOH compound, L i N b0 3 compound, LiTaO 3 compound or the like.
  • connection between the battery and the RAM chip is such that an earth terminal V ss 6 and. a power supply terminal V cc 6' of a circuit integrated within a semiconductor are respectively connected to the anode and cathode through conductors 12 and 12'. Lastly, a passivation layer 13 is formed, and the chip is bonded and then packaged.
  • the cell capacity corresponding to the anode and cathode active materials of the battery determines the retention-time of the RAM. For example, in case where a battery having a discharge capacity of 7 mAh is connected to a 16 kb C-MOS static RAM, the memory content is retained for about 30 days. In addition, since the battery is fully solid, it is stable and can possess a lifetime of at least 5 years. Further, since the battery indicated in the present embodiment is a secondary cell, it is charged while an external power source is turned “on”, and the memory content can be retained by the discharge of the battery after the external power source has been turned “off”.
  • FIG. 2A the fundamental arrangement of the static RAM can be depicted by a memory cell array 21 and a peripheral circuit 20 (22: column decoder, 23: control signal pulse generator, 24: row decoder, 25: I/0 circuit, 26: address buffer).
  • a memory cell array 21 the fundamental arrangement of the static RAM can be depicted by a memory cell array 21 and a peripheral circuit 20 (22: column decoder, 23: control signal pulse generator, 24: row decoder, 25: I/0 circuit, 26: address buffer).
  • current is basically supplied from the power supply element to only the memory cell array.
  • FIG. 2B The construction of this invention for using the battery is shown in Figure 2B as the block diagram.
  • the peripheral circuit has a circuit arrangement which does not consume current in a stand-by condition (for example, C-MOS circuit), it is also allowed to connect the power supply terminals c and d of the memory cell array and the peripheral circuit with the battery and to disconnect the path between the points a and d.
  • a stand-by condition for example, C-MOS circuit
  • the switching control circuit 28 can be constructed of a combination of a supply voltage (current) sensing circuit, a control circuit and a switching circuit. It may well be interlocked with a power supply switch or be made a mere switch.
  • nonvolatile RAM is constructed by forming a p-i-n multilayer solar cell on a memory chip as a power supply element will be described with reference to Figure 3.
  • a current collector 31 is formed on a C-MOS static RAM chip which has a passivation layer 8 as in Embodiment 1. Subsequently, using amorphous silicon layers or polycrystalline silicon layers, semiconductor thin layers of the p-type 32, the i-type 33 and the n-type 34 are formed to construct the solar battery. Subsequently, a current collector 35 and a passivation film 13 are formed. After bonding the resultant chip, it is sealed in a package provided with a transparent window. Thus, a nonvolatile RAM is obtained.
  • the earth terminal V ss 6 and power source terminal V cc 6 1 of the circuit integrated in the semiconductor are respectively connected with the current collectors 31 and 35 of the solar cell.
  • the construction of the C-MOS static RAM chip is the same as in Embodiment 1. By dividing the solar cell into several regions on the chip and connecting them in series, any desired retention voltage can be generated.
  • a current of at least 500 ⁇ A/cm 2 can be taken out in the presence of such light-.as the sunrays and the light of an electric lamp. In the presence of such light, therefore, the RAM functions as a semipermanently nonvolatile RAM.
  • any of the aforecited batteries is fixed, whereupon the bonding of the memory chip and the bonding between the battery and the chip are carried out.
  • the resultant structure is packaged to construct the nonvolatile RAM (40: package, 401: lead, 402: pin).
  • numerals 42 and 43 designate the anode and cathode collectors of the battery which are connected with the power supply terminal V cc and earth terminal V ss of the circuit integrated in the memory chip, respectively.
  • Numeral 44 indicates the sealing material of the battery.
  • Figure 5 is a view of one section of a thin type battery fixed on the memory chip.
  • numeral 41 indicates a silicon integrated circuit chip
  • numerals 42 and 43 the anode - and cathode collectors-of the battery
  • numeral 44 the sealing material of the battery
  • numeral 45 is the body of the battery
  • numeral 46 a passivation film
  • numeral 47 a bonding pad
  • a nonvolatile RAM in which a power supply element is added to a RAM having been packaged will be described with reference to Figures 6 and 7.
  • Figure 6 is an exterior view
  • Figure 7 is a sectional view.
  • a nonvolatile RAM can be constructed in such a way that a power supply element 60 is connected to a memory package 61 having an outer socket 63.
  • numerals 62 and 62' designate the anode and cathode collectors of the power supply element respectively
  • numerals 64 and 64' leads numeral 65 a battery body composed of an electrolyte and anode and cathode materials
  • numeral 66 a battery sealing material.
  • the power supply element 60 is connected with the retention power source terminals of the RAM through the socket 63.
  • the power supply element maybe added to only the device requiring the information retention, and the versatility increases sharply.
  • the power supply element there is employed a silver-zinc battery, a lithium battery, a solid-state lithium battery, a large-capacity capacitor (for example, electric double layer-capacitance type capacitor), a solar battery, etc.
  • a solid electrolyte capacitor is employed as the power supply element of Embodiment 1 or 3.
  • the solid electrolyte capacitor is a large-capacity capacitor which uses a solid electrolyte such as Rb 2 Cu 8 I 3 Cl 7 and Li 4 SiO 4 -Li 3 PO 4
  • circuitry has the same arrangement as in Figure 2B.
  • the nonvolatile RAM according to this invention has the memory contents of its individual memory chips retained. Therefore, it has the advantages that a RAM can be freely sampled and moved from a memory board and that it can be shipped in the state in which an appropriate memory content is retained. Moreover, a useful memory system which is high in both the writing and reading speeds and which is nonvolatile as stated before can be constructed by the use of the RAM according to this invention.
  • the RAM has been referred to as the memory of this invention.
  • the invention is not restricted thereto, but it is also applicable to other volatile memories, for example, a content addressable memory (CAM), a serial memory and an analogue memory. It is a matter of course that the invention is applicable, not only to a MOS type memory, but also to a bipolar type memory.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Secondary Cells (AREA)
  • Static Random-Access Memory (AREA)
  • Power Sources (AREA)
  • Semiconductor Memories (AREA)
  • Battery Electrode And Active Subsutance (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Non-Volatile Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Stand-By Power Supply Arrangements (AREA)
  • Non-Insulated Conductors (AREA)
EP81110659A 1980-12-26 1981-12-21 Halbleiterspeicheranordnung Expired - Lifetime EP0055451B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP188723/80 1980-12-26
JP55188723A JPS57109183A (en) 1980-12-26 1980-12-26 Non-volatile memory

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP85110709A Division EP0171089A3 (de) 1980-12-26 1981-12-21 Stromversorgungsanlage
EP85110709.4 Division-Into 1985-08-26

Publications (3)

Publication Number Publication Date
EP0055451A2 true EP0055451A2 (de) 1982-07-07
EP0055451A3 EP0055451A3 (en) 1984-03-28
EP0055451B1 EP0055451B1 (de) 1990-03-28

Family

ID=16228647

Family Applications (2)

Application Number Title Priority Date Filing Date
EP81110659A Expired - Lifetime EP0055451B1 (de) 1980-12-26 1981-12-21 Halbleiterspeicheranordnung
EP85110709A Withdrawn EP0171089A3 (de) 1980-12-26 1981-12-21 Stromversorgungsanlage

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP85110709A Withdrawn EP0171089A3 (de) 1980-12-26 1981-12-21 Stromversorgungsanlage

Country Status (5)

Country Link
US (1) US4539660A (de)
EP (2) EP0055451B1 (de)
JP (4) JPS57109183A (de)
CA (1) CA1202725A (de)
DE (1) DE3177169D1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710905A (en) * 1983-09-16 1987-12-01 Kabushiki Kaisha Toshiba Semiconductor memory device
WO1991002385A1 (en) * 1989-08-03 1991-02-21 Bell Communications Research, Inc. Battery containing solid protonically conducting electrolyte

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US7776478B2 (en) 2005-07-15 2010-08-17 Cymbet Corporation Thin-film batteries with polymer and LiPON electrolyte layers and method
JP2009502011A (ja) 2005-07-15 2009-01-22 シンベット・コーポレイション 軟質および硬質電解質層付き薄膜電池および方法
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Publication number Priority date Publication date Assignee Title
US4710905A (en) * 1983-09-16 1987-12-01 Kabushiki Kaisha Toshiba Semiconductor memory device
WO1991002385A1 (en) * 1989-08-03 1991-02-21 Bell Communications Research, Inc. Battery containing solid protonically conducting electrolyte

Also Published As

Publication number Publication date
JPH0334662B2 (de) 1991-05-23
EP0171089A3 (de) 1987-09-09
JPS5932023A (ja) 1984-02-21
JPH0410303B2 (de) 1992-02-24
EP0171089A2 (de) 1986-02-12
JPS5931570A (ja) 1984-02-20
JPS57109183A (en) 1982-07-07
EP0055451A3 (en) 1984-03-28
CA1202725A (en) 1986-04-01
EP0055451B1 (de) 1990-03-28
US4539660A (en) 1985-09-03
DE3177169D1 (de) 1990-05-03
JPS5925531A (ja) 1984-02-09

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