EP0052553B1 - Générateur de courant intégré en technologie CMOS - Google Patents

Générateur de courant intégré en technologie CMOS Download PDF

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Publication number
EP0052553B1
EP0052553B1 EP81401753A EP81401753A EP0052553B1 EP 0052553 B1 EP0052553 B1 EP 0052553B1 EP 81401753 A EP81401753 A EP 81401753A EP 81401753 A EP81401753 A EP 81401753A EP 0052553 B1 EP0052553 B1 EP 0052553B1
Authority
EP
European Patent Office
Prior art keywords
transistors
transistor
current
gate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP81401753A
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German (de)
English (en)
French (fr)
Other versions
EP0052553A1 (fr
Inventor
Jean-Claude Bertails
Christian Perrin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Ste
Original Assignee
Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Ste
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Application filed by Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Ste filed Critical Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Ste
Publication of EP0052553A1 publication Critical patent/EP0052553A1/fr
Application granted granted Critical
Publication of EP0052553B1 publication Critical patent/EP0052553B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to an integrated circuit capable of developing current sources of constant value, with a view to supplying current, for example, to analog functions of an integrated circuit.
  • CMOS technology is used here, that is to say that the circuits produced essentially comprise N-channel and P-channel MOS (Metal-Oxide-Semiconductor) transistors.
  • MOS Metal-Oxide-Semiconductor
  • the guiding idea of the present invention is that it is known, in CMOS technology, to produce transistors whose threshold voltage can be modified by ion implantation, this operation being carried out during the stages of manufacture of the integrated circuit, so that one can designate by masking certain transistors whose threshold voltage must be higher or lower (in absolute value) than others.
  • the threshold voltage of these chosen transistors can be adjusted to a desired value by acting on the dose of implanted ions.
  • the present invention provides a particularly simple transistor assembly for using this property and producing, from two transistors having different threshold voltages, one or more current sources stable in temperature and independent of the voltage supply.
  • couples of transistors operating in saturated conditions are used and connected to each other by connections such that the current or voltage conditions existing in another can be copied by a transistor, until the terminals appear of a resistance of known value exactly the difference between the threshold voltages of two transitors having undergone a different ion implantation.
  • the current which crosses this resistance is stable and one arranges to make it cross at least one MOS transistor operating in saturated mode and to make recopy this current (with a factor of proportionality near if it is desired) by at least one other transistor MOS having the same gate-source bias voltage as the first and the same threshold voltage.
  • a particularly simple assembly consists in having a voltage source supplying in parallel two sets of MOS transistors in series, each transistor of one of the sets having a counterpart of the same type of channel in the other set. ; each set comprises three transistors and the geometry ratios of the homologous transistors are the same for all the transistors of the sets; the first transistors, of a first type of channel, have the same threshold voltage and have their gates joined, that of the second assembly further having its gate joined to its drain; the second transistors, of a second type of channel opposite to the first, have the same threshold voltage and have their gates joined, that of the first assembly further having its gate joined to its drain; the third transistors, of the second type of channel, have respectively their gate joined to their drain and have different threshold voltages (one of them for example having not undergone like the other transistors of the same type an ion implantation intended to lower its threshold voltage in absolute value, or, conversely, having alone undergone an ion implantation intended to increase its threshold voltage in absolute value).
  • a resistor of known value, integrated or not, is inserted in series between the second and the third transistor of one of the assemblies.
  • at least one additional MOS transistor is provided, apart from the two sets, to serve as a constant and stable supply current generator, this transistor having its source and its gate connected to the source and to the gate of the first or of the third transistor of one of the assemblies and having the same threshold voltage as the transistor to which it is connected in order to copy the current flowing through the latter (to within a proportionality factor known).
  • additional transistors can be provided, each having their gate and their source connected to the gate and to the source respectively of the first or of the third transistor of one of the assemblies.
  • Each of these additional transistors serves as a stable current source since it copies the stable current into the resistor.
  • the additional transistor or transistors have a known geometry factor with respect to the transistors to which they are connected, so that the current which they copy is in a known relationship with the stable current in the resistor.
  • each first or third transistor as well as each additional transistor, that is to say constitute, instead of a single transistor, a plurality of individual transistors. partial dual all connected in parallel (same gate, source and drain connection) playing exactly the same role as a single transistor but can be located in several places. Under these conditions, it is possible to provide side by side a first or third partial transistor and a partial additional transistor associated therewith to constitute an individual stable current source copying the current into the resistor with a proportionality factor which depends on the geometry of this partial additional transistor.
  • the mounting of transistors according to the invention effectively makes it possible to have a stable current in the resistor because it appears at the terminals thereof a voltage which is the difference of the threshold voltages of two MOS transistors of which only one has undergone an adjustment ion implantation.
  • This voltage therefore the current flowing through the resistor, does not depend on the temperature or the supply voltage of the circuit and moreover it is very stable over time.
  • the current produced in the resistor depends on the temperature to the same extent as the resistor, and the latter is chosen to be as stable as possible, whether integrated or external. If it is integrated, one will choose among the resistances diffused that which presents the lowest coefficient of temperature.
  • the arrangement of the invention comprises a first pair of homologous transistors, one of which copies the current of the other (to within a factor), a second pair of homologous transistors, the a copy of the source voltage of the other, a third pair of homologous transistors but at different threshold voltages that generates a voltage difference, a resistance in series with one of the transistors of the third couple to make up for this voltage difference, and at least one additional transistor for copying (to within a factor) of the current in one of the preceding transistors.
  • the key to the invention resides in the correspondence of the ratios of geometry factors of all the pairs of homologous transistors, and in the exact correspondence of the threshold voltages of all the couples of homologous transistors except one of them which must precisely generate a voltage difference. It must also be ensured that the threshold voltage of the additional current copying transistor (s) is indeed the same as the threshold voltage of the transistor to which its gate and its source are connected.
  • the circuit of FIG. 2 is therefore intended to produce a stable current source intended to supply part of the analog circuit 10 which is in principle integrated on the same substrate as the current source according to the invention.
  • This analog circuit can for example be an amplifier part: many differential amplifiers in particular use constant current sources.
  • the entire integrated circuit (analog part 10 and current source according to the invention) is supplied for example by symmetrical voltage levels + V and -V.
  • the transistor Ti is the counterpart of the transistor T ' 1 , the transistor T 2 of the transistor T' 2 and the transistor T 3 of the transistor T ' 3 .
  • the transistors T 1 and T ' 1 are N-channel (for example); the transistors T 2 , T ' 2 and T 3 , T' 3 are of the opposite channel type, in this case P in the example chosen.
  • the transistors T 1 , T 2 and T 3 can have any geometry; the transistors T ' i , T' 2 and T ' 3 have geometries in the same relationship as the transistors T 1 , T 2 and T 3 , that is to say that there exists a constant coefficient of proportionality between the homologous transistors of the two sets in series.
  • the homologous transistors T 1 and T ' 1 have the same threshold voltage; the homologous transistors T 2 and T ' 2 also have the same threshold voltage; on the other hand the transistors T 3 and T ' 3 have different threshold voltages, respectively V T3 and V' T3 .
  • all the P-channel MOS transistors of the integrated circuit, and in particular the transistors T 2 , T ' 2 and T' 3 have undergone ion implantation through their gate isolation to lower their threshold voltage. The transistor T 3 or T ' 3 on the contrary was masked during this operation so that it retains a higher threshold voltage in absolute value than the transistor T' 3 or T 3 and the others.
  • a resistance R 1 has been incorporated in series between the drain of transistor T ' 2 and the source of transistor T'a. It should be noted here that this resistor R 1 can be incorporated in the integrated circuit, and then be produced in the form of a portion of doped silicon, or it can be external to the circuit and connected to the latter by means of pins of external connection and metallic connections.
  • the transistor T ' i has its drain connected to its gate which itself is connected to the gate of the transistor T i , according to a conventional arrangement known as "current mirror", so that the current in the transistor T 1 copies the current in the transistor T ' 1 to a factor of proportionality that is the ratio K between the geometry of the transistor T i and the geometry of the transistor T'i (which is also the ratio between T 2 and T' 2 and the ratio between T 3 and T ' 3 ).
  • the current I 1 in T 1 is indeed proportional to the current I ' 1 in T' 1 , the proportionality factor being the ratio of the geometries of the two transistors.
  • the drain of transistor T 2 is connected to its gate, which is itself also connected to the gate of transistor T ' 2 . It is also a mirror assembly of currents, but this time, the sources of the transistors T 2 and T'z are not connected to each other so that the gate-source voltage of the transistors T 2 and T ' 2 is not directly imposed.
  • the current which crosses T 2 is the same as the current which crosses T 1 (I 1 ) and the current which crosses T ' 2 is the same as the current which crosses T' 1 (I ' 1 ).
  • the transistors T 3 and T ' 3 have their sources connected to the supply voltage + V; they preferably have their grid connected to their drain; by always applying the same formula for calculating the current in saturated regime, and taking into account that the currents I 1 and I ' 1 which cross T 3 and T' 3 are in the ratio K of the geometries of the transistors T 3 and T ' 3 , we immediately deduce that it appears between the drains (that is to say the gates) of the transistors T 3 and T' 3 a voltage difference which is precisely equal to the difference of the threshold voltages of these transistors.
  • V 3 V 2
  • the resistance R is inserted between the drain of T ' 3 and the source of T' 2
  • the voltage drop R 1 I' 1 in the resistor R 1 is equal to the difference of the threshold voltages of the transistors T ' 3 and T 3 .
  • the current I ′ 1 is therefore a current of well determined value stable over time, stable in temperature, and independent of the supply voltage + V, -V.
  • the current I 1 in the first set in series of the transistors T i , T 2 , T 3 is also a stable current since it copies the current I ' 1 to a factor of proportionality which is the ratio K between the geometries of the transistors of the first and second set in series. This ratio is independent of the temperature of course.
  • the transistor T " 1 is then placed in series between the analog circuit 10 and the supply connection V +, and a stable current returning i 1 is thus produced in the circuit 10.
  • an outgoing current i ' 1 by connecting a feedback transistor T ′′′ 1 , in series between the supply connection -V and the analog circuit 10.
  • the outgoing current I ' 1 may very well be provided in isolation or in addition to the current I 1 and it is not necessarily equal to the current I 1 .
  • the transistor T ′′′ 1 copies the current in the transistor T ' 1 (or T 1 ) if its gate and its source are connected to the gate and to the source of T' 1 (or T 1 ).
  • K is the ratio between the geometry of transistor T ′′′ 1 and that of transistor T ' 1 , these two transistors having the same threshold voltage, the current i' 1 will be K" I ' 1 .
  • FIG. 1 only one analog circuit 10 is represented, supplied by a re-entering current i 1 and an outgoing current i ' 1 ; it is obviously possible to provide several analog circuits each supplied by a feedback transistor having its gate and its source connected to one of the transistors traversed by the stable currents I 1 or I ' 1 (in practice the transistors T 1 , T' 1 and T ' 3 .
  • FIG 2 there is shown a current supply circuit quite similar to that of Figure 1, in which one seeks to supply several analog circuits 10, 20, etc., each requiring a particular stable current reference and possibly arranged in different places of the global integrated circuit chip.
  • the transistor T '3 is in the form of a plurality of transistors T' 31, T '32... etc. all connected in parallel.
  • the transistor T' 1 arises in the form of a plurality of transistors T '11, T 12,... etc.
  • the transistor T "1 is in the form of several transistorT" 11, T "12. . . etc.
  • the transistor T ′′′ 1 is in the form of several transistors T ′′′ 11 , T ′′′ 12 . . . etc.
  • the resulting stable supply currents i 11 , i 12 . . . or i '11, i' 12. . . are currents of recopy of the, in a proportionality ratio corresponding to the ratio of the geometry factors of the juxtaposed transistors which give rise to these recopy currents.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP81401753A 1980-11-14 1981-10-30 Générateur de courant intégré en technologie CMOS Expired EP0052553B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8024232A FR2494519A1 (fr) 1980-11-14 1980-11-14 Generateur de courant integre en technologie cmos
FR8024232 1980-11-14

Publications (2)

Publication Number Publication Date
EP0052553A1 EP0052553A1 (fr) 1982-05-26
EP0052553B1 true EP0052553B1 (fr) 1985-03-27

Family

ID=9247977

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81401753A Expired EP0052553B1 (fr) 1980-11-14 1981-10-30 Générateur de courant intégré en technologie CMOS

Country Status (5)

Country Link
US (1) US4442398A (enrdf_load_stackoverflow)
EP (1) EP0052553B1 (enrdf_load_stackoverflow)
JP (1) JPS57111711A (enrdf_load_stackoverflow)
DE (1) DE3169594D1 (enrdf_load_stackoverflow)
FR (1) FR2494519A1 (enrdf_load_stackoverflow)

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US4618815A (en) * 1985-02-11 1986-10-21 At&T Bell Laboratories Mixed threshold current mirror
JPS61212907A (ja) * 1985-03-18 1986-09-20 Fujitsu Ltd 半導体集積回路
US4788455A (en) * 1985-08-09 1988-11-29 Mitsubishi Denki Kabushiki Kaisha CMOS reference voltage generator employing separate reference circuits for each output transistor
JPS6324406A (ja) * 1986-07-17 1988-02-01 Seikosha Co Ltd 定電流回路
JP2508077B2 (ja) * 1987-04-22 1996-06-19 日本電気株式会社 定電流源回路
US4837459A (en) * 1987-07-13 1989-06-06 International Business Machines Corp. CMOS reference voltage generation
US4797580A (en) * 1987-10-29 1989-01-10 Northern Telecom Limited Current-mirror-biased pre-charged logic circuit
US4769589A (en) * 1987-11-04 1988-09-06 Teledyne Industries, Inc. Low-voltage, temperature compensated constant current and voltage reference circuit
GB2214018A (en) * 1987-12-23 1989-08-23 Philips Electronic Associated Current mirror circuit arrangement
JP2705169B2 (ja) * 1988-12-17 1998-01-26 日本電気株式会社 定電流供給回路
JP3009109B2 (ja) * 1989-11-07 2000-02-14 富士通株式会社 半導体集積回路
JPH04111008A (ja) * 1990-08-30 1992-04-13 Oki Electric Ind Co Ltd 定電流源回路
JP2978226B2 (ja) * 1990-09-26 1999-11-15 三菱電機株式会社 半導体集積回路
US5257039A (en) * 1991-09-23 1993-10-26 Eastman Kodak Company Non-impact printhead and driver circuit for use therewith
US5362988A (en) * 1992-05-01 1994-11-08 Texas Instruments Incorporated Local mid-rail generator circuit
JP3114391B2 (ja) * 1992-10-14 2000-12-04 三菱電機株式会社 中間電圧発生回路
JPH0793977A (ja) * 1993-04-26 1995-04-07 Samsung Electron Co Ltd 半導体メモリ装置の中間電圧発生回路
US5362990A (en) * 1993-06-02 1994-11-08 Motorola, Inc. Charge pump with a programmable pump current and system
DE4334513C1 (de) * 1993-10-09 1994-10-20 Itt Ind Gmbh Deutsche CMOS-Schaltung mit erhöhter Spannungsfestigkeit
JPH07191769A (ja) * 1993-12-27 1995-07-28 Toshiba Corp 基準電流発生回路
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FR2721119B1 (fr) * 1994-06-13 1996-07-19 Sgs Thomson Microelectronics Source de courant stable en température.
FR2721773B1 (fr) * 1994-06-27 1996-09-06 Sgs Thomson Microelectronics Dispositif de mise en veille partielle d'une source de polarisation et circuit de commande d'une telle source.
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EP1094599B1 (en) * 1999-10-21 2004-12-22 STMicroelectronics S.r.l. A circuit for compensating for the difference between the Vgs voltages of two MOS transistors
EP1315063A1 (en) * 2001-11-14 2003-05-28 Dialog Semiconductor GmbH A threshold voltage-independent MOS current reference
KR100460458B1 (ko) * 2002-07-26 2004-12-08 삼성전자주식회사 외부 전압 글리치에 안정적인 내부 전압 발생 회로
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US4342926A (en) * 1980-11-17 1982-08-03 Motorola, Inc. Bias current reference circuit

Also Published As

Publication number Publication date
JPH0261052B2 (enrdf_load_stackoverflow) 1990-12-19
DE3169594D1 (en) 1985-05-02
FR2494519A1 (fr) 1982-05-21
EP0052553A1 (fr) 1982-05-26
US4442398A (en) 1984-04-10
JPS57111711A (en) 1982-07-12
FR2494519B1 (enrdf_load_stackoverflow) 1984-10-12

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