EP0052553B1 - Integrated current-source generator in cmos technology - Google Patents

Integrated current-source generator in cmos technology Download PDF

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Publication number
EP0052553B1
EP0052553B1 EP81401753A EP81401753A EP0052553B1 EP 0052553 B1 EP0052553 B1 EP 0052553B1 EP 81401753 A EP81401753 A EP 81401753A EP 81401753 A EP81401753 A EP 81401753A EP 0052553 B1 EP0052553 B1 EP 0052553B1
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EP
European Patent Office
Prior art keywords
transistors
transistor
current
gate
source
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EP81401753A
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German (de)
French (fr)
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EP0052553A1 (en
Inventor
Jean-Claude Bertails
Christian Perrin
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Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Ste
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Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Ste
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to an integrated circuit capable of developing current sources of constant value, with a view to supplying current, for example, to analog functions of an integrated circuit.
  • CMOS technology is used here, that is to say that the circuits produced essentially comprise N-channel and P-channel MOS (Metal-Oxide-Semiconductor) transistors.
  • MOS Metal-Oxide-Semiconductor
  • the guiding idea of the present invention is that it is known, in CMOS technology, to produce transistors whose threshold voltage can be modified by ion implantation, this operation being carried out during the stages of manufacture of the integrated circuit, so that one can designate by masking certain transistors whose threshold voltage must be higher or lower (in absolute value) than others.
  • the threshold voltage of these chosen transistors can be adjusted to a desired value by acting on the dose of implanted ions.
  • the present invention provides a particularly simple transistor assembly for using this property and producing, from two transistors having different threshold voltages, one or more current sources stable in temperature and independent of the voltage supply.
  • couples of transistors operating in saturated conditions are used and connected to each other by connections such that the current or voltage conditions existing in another can be copied by a transistor, until the terminals appear of a resistance of known value exactly the difference between the threshold voltages of two transitors having undergone a different ion implantation.
  • the current which crosses this resistance is stable and one arranges to make it cross at least one MOS transistor operating in saturated mode and to make recopy this current (with a factor of proportionality near if it is desired) by at least one other transistor MOS having the same gate-source bias voltage as the first and the same threshold voltage.
  • a particularly simple assembly consists in having a voltage source supplying in parallel two sets of MOS transistors in series, each transistor of one of the sets having a counterpart of the same type of channel in the other set. ; each set comprises three transistors and the geometry ratios of the homologous transistors are the same for all the transistors of the sets; the first transistors, of a first type of channel, have the same threshold voltage and have their gates joined, that of the second assembly further having its gate joined to its drain; the second transistors, of a second type of channel opposite to the first, have the same threshold voltage and have their gates joined, that of the first assembly further having its gate joined to its drain; the third transistors, of the second type of channel, have respectively their gate joined to their drain and have different threshold voltages (one of them for example having not undergone like the other transistors of the same type an ion implantation intended to lower its threshold voltage in absolute value, or, conversely, having alone undergone an ion implantation intended to increase its threshold voltage in absolute value).
  • a resistor of known value, integrated or not, is inserted in series between the second and the third transistor of one of the assemblies.
  • at least one additional MOS transistor is provided, apart from the two sets, to serve as a constant and stable supply current generator, this transistor having its source and its gate connected to the source and to the gate of the first or of the third transistor of one of the assemblies and having the same threshold voltage as the transistor to which it is connected in order to copy the current flowing through the latter (to within a proportionality factor known).
  • additional transistors can be provided, each having their gate and their source connected to the gate and to the source respectively of the first or of the third transistor of one of the assemblies.
  • Each of these additional transistors serves as a stable current source since it copies the stable current into the resistor.
  • the additional transistor or transistors have a known geometry factor with respect to the transistors to which they are connected, so that the current which they copy is in a known relationship with the stable current in the resistor.
  • each first or third transistor as well as each additional transistor, that is to say constitute, instead of a single transistor, a plurality of individual transistors. partial dual all connected in parallel (same gate, source and drain connection) playing exactly the same role as a single transistor but can be located in several places. Under these conditions, it is possible to provide side by side a first or third partial transistor and a partial additional transistor associated therewith to constitute an individual stable current source copying the current into the resistor with a proportionality factor which depends on the geometry of this partial additional transistor.
  • the mounting of transistors according to the invention effectively makes it possible to have a stable current in the resistor because it appears at the terminals thereof a voltage which is the difference of the threshold voltages of two MOS transistors of which only one has undergone an adjustment ion implantation.
  • This voltage therefore the current flowing through the resistor, does not depend on the temperature or the supply voltage of the circuit and moreover it is very stable over time.
  • the current produced in the resistor depends on the temperature to the same extent as the resistor, and the latter is chosen to be as stable as possible, whether integrated or external. If it is integrated, one will choose among the resistances diffused that which presents the lowest coefficient of temperature.
  • the arrangement of the invention comprises a first pair of homologous transistors, one of which copies the current of the other (to within a factor), a second pair of homologous transistors, the a copy of the source voltage of the other, a third pair of homologous transistors but at different threshold voltages that generates a voltage difference, a resistance in series with one of the transistors of the third couple to make up for this voltage difference, and at least one additional transistor for copying (to within a factor) of the current in one of the preceding transistors.
  • the key to the invention resides in the correspondence of the ratios of geometry factors of all the pairs of homologous transistors, and in the exact correspondence of the threshold voltages of all the couples of homologous transistors except one of them which must precisely generate a voltage difference. It must also be ensured that the threshold voltage of the additional current copying transistor (s) is indeed the same as the threshold voltage of the transistor to which its gate and its source are connected.
  • the circuit of FIG. 2 is therefore intended to produce a stable current source intended to supply part of the analog circuit 10 which is in principle integrated on the same substrate as the current source according to the invention.
  • This analog circuit can for example be an amplifier part: many differential amplifiers in particular use constant current sources.
  • the entire integrated circuit (analog part 10 and current source according to the invention) is supplied for example by symmetrical voltage levels + V and -V.
  • the transistor Ti is the counterpart of the transistor T ' 1 , the transistor T 2 of the transistor T' 2 and the transistor T 3 of the transistor T ' 3 .
  • the transistors T 1 and T ' 1 are N-channel (for example); the transistors T 2 , T ' 2 and T 3 , T' 3 are of the opposite channel type, in this case P in the example chosen.
  • the transistors T 1 , T 2 and T 3 can have any geometry; the transistors T ' i , T' 2 and T ' 3 have geometries in the same relationship as the transistors T 1 , T 2 and T 3 , that is to say that there exists a constant coefficient of proportionality between the homologous transistors of the two sets in series.
  • the homologous transistors T 1 and T ' 1 have the same threshold voltage; the homologous transistors T 2 and T ' 2 also have the same threshold voltage; on the other hand the transistors T 3 and T ' 3 have different threshold voltages, respectively V T3 and V' T3 .
  • all the P-channel MOS transistors of the integrated circuit, and in particular the transistors T 2 , T ' 2 and T' 3 have undergone ion implantation through their gate isolation to lower their threshold voltage. The transistor T 3 or T ' 3 on the contrary was masked during this operation so that it retains a higher threshold voltage in absolute value than the transistor T' 3 or T 3 and the others.
  • a resistance R 1 has been incorporated in series between the drain of transistor T ' 2 and the source of transistor T'a. It should be noted here that this resistor R 1 can be incorporated in the integrated circuit, and then be produced in the form of a portion of doped silicon, or it can be external to the circuit and connected to the latter by means of pins of external connection and metallic connections.
  • the transistor T ' i has its drain connected to its gate which itself is connected to the gate of the transistor T i , according to a conventional arrangement known as "current mirror", so that the current in the transistor T 1 copies the current in the transistor T ' 1 to a factor of proportionality that is the ratio K between the geometry of the transistor T i and the geometry of the transistor T'i (which is also the ratio between T 2 and T' 2 and the ratio between T 3 and T ' 3 ).
  • the current I 1 in T 1 is indeed proportional to the current I ' 1 in T' 1 , the proportionality factor being the ratio of the geometries of the two transistors.
  • the drain of transistor T 2 is connected to its gate, which is itself also connected to the gate of transistor T ' 2 . It is also a mirror assembly of currents, but this time, the sources of the transistors T 2 and T'z are not connected to each other so that the gate-source voltage of the transistors T 2 and T ' 2 is not directly imposed.
  • the current which crosses T 2 is the same as the current which crosses T 1 (I 1 ) and the current which crosses T ' 2 is the same as the current which crosses T' 1 (I ' 1 ).
  • the transistors T 3 and T ' 3 have their sources connected to the supply voltage + V; they preferably have their grid connected to their drain; by always applying the same formula for calculating the current in saturated regime, and taking into account that the currents I 1 and I ' 1 which cross T 3 and T' 3 are in the ratio K of the geometries of the transistors T 3 and T ' 3 , we immediately deduce that it appears between the drains (that is to say the gates) of the transistors T 3 and T' 3 a voltage difference which is precisely equal to the difference of the threshold voltages of these transistors.
  • V 3 V 2
  • the resistance R is inserted between the drain of T ' 3 and the source of T' 2
  • the voltage drop R 1 I' 1 in the resistor R 1 is equal to the difference of the threshold voltages of the transistors T ' 3 and T 3 .
  • the current I ′ 1 is therefore a current of well determined value stable over time, stable in temperature, and independent of the supply voltage + V, -V.
  • the current I 1 in the first set in series of the transistors T i , T 2 , T 3 is also a stable current since it copies the current I ' 1 to a factor of proportionality which is the ratio K between the geometries of the transistors of the first and second set in series. This ratio is independent of the temperature of course.
  • the transistor T " 1 is then placed in series between the analog circuit 10 and the supply connection V +, and a stable current returning i 1 is thus produced in the circuit 10.
  • an outgoing current i ' 1 by connecting a feedback transistor T ′′′ 1 , in series between the supply connection -V and the analog circuit 10.
  • the outgoing current I ' 1 may very well be provided in isolation or in addition to the current I 1 and it is not necessarily equal to the current I 1 .
  • the transistor T ′′′ 1 copies the current in the transistor T ' 1 (or T 1 ) if its gate and its source are connected to the gate and to the source of T' 1 (or T 1 ).
  • K is the ratio between the geometry of transistor T ′′′ 1 and that of transistor T ' 1 , these two transistors having the same threshold voltage, the current i' 1 will be K" I ' 1 .
  • FIG. 1 only one analog circuit 10 is represented, supplied by a re-entering current i 1 and an outgoing current i ' 1 ; it is obviously possible to provide several analog circuits each supplied by a feedback transistor having its gate and its source connected to one of the transistors traversed by the stable currents I 1 or I ' 1 (in practice the transistors T 1 , T' 1 and T ' 3 .
  • FIG 2 there is shown a current supply circuit quite similar to that of Figure 1, in which one seeks to supply several analog circuits 10, 20, etc., each requiring a particular stable current reference and possibly arranged in different places of the global integrated circuit chip.
  • the transistor T '3 is in the form of a plurality of transistors T' 31, T '32... etc. all connected in parallel.
  • the transistor T' 1 arises in the form of a plurality of transistors T '11, T 12,... etc.
  • the transistor T "1 is in the form of several transistorT" 11, T "12. . . etc.
  • the transistor T ′′′ 1 is in the form of several transistors T ′′′ 11 , T ′′′ 12 . . . etc.
  • the resulting stable supply currents i 11 , i 12 . . . or i '11, i' 12. . . are currents of recopy of the, in a proportionality ratio corresponding to the ratio of the geometry factors of the juxtaposed transistors which give rise to these recopy currents.

Description

La présente invention concerne un circuit intégré capable d'élaborer des sources de courant de valeur constante, en vue d'alimenter en courant par exemple des fonctions analogiques d'un circuit intégré.The present invention relates to an integrated circuit capable of developing current sources of constant value, with a view to supplying current, for example, to analog functions of an integrated circuit.

On utilise ici une technologie CMOS, c'est-à-dire que les circuits réalisés comprennent essentiellement des transistors MOS (Métal-Oxyde-Semiconducteur) à canal N et à canal P.CMOS technology is used here, that is to say that the circuits produced essentially comprise N-channel and P-channel MOS (Metal-Oxide-Semiconductor) transistors.

On cherche selon l'invention à réaliser des sources de courant peu dépendantes de la température et de la tension d'alimentation du circuit intégré comportant ces sources.It is sought according to the invention to produce current sources little dependent on the temperature and the supply voltage of the integrated circuit comprising these sources.

Des sources de courant ont déjà été proposées dans cette technologie CMOS; par exemple, l'article de David Bingham, »CMOS higher speeds, more drive and analog capability expand its horizons«, paru dans »Electronic Design« Vol 26 n° 23 de novembre 1978, décrit une telle source. Cette source utilise deux transistors MOS identiques et deux transistors de géométries très différentes, cette différence étant compensée dans une résistance. Ce dispositif est susceptible de fournir un courant de référence constant, mais ne permet pas une grande liberté de choix de la valeur du courant obtenu (faible tension aux bornes de la résistance) et dépend d'une manière mal connue de la température.Current sources have already been proposed in this CMOS technology; for example, the article by David Bingham, "CMOS higher speeds, more drive and analog capability expand its horizons", published in "Electronic Design" Vol 26 no 23 of November 1978, describes such a source. This source uses two identical MOS transistors and two transistors of very different geometries, this difference being compensated for in a resistor. This device is capable of supplying a constant reference current, but does not allow great freedom of choice of the value of the current obtained (low voltage across the resistance) and depends in a poorly known manner on the temperature.

L'idée directrice de la présente invention est que l'on sait, en technologie CMOS, réaliser des transistors dont la tension de seuil peut être modifiée par implantation ionique, cette opération se faisant au cours des étapes de fabrication du circuit intégré, de sorte qu'on peut désigner par masquage certains transistors dont la tension de seuil doit être plus forte ou plus faible (en valeur absolue) que d'autres. La tension de seuil de ces transistors choisis peut être ajustée à une valeur désirée par action sur la dose d'ions implantés.The guiding idea of the present invention is that it is known, in CMOS technology, to produce transistors whose threshold voltage can be modified by ion implantation, this operation being carried out during the stages of manufacture of the integrated circuit, so that one can designate by masking certain transistors whose threshold voltage must be higher or lower (in absolute value) than others. The threshold voltage of these chosen transistors can be adjusted to a desired value by acting on the dose of implanted ions.

La théorie et l'expérience montrent que les tensions de seuil différentes de deux transistors ayant subi une implantation ionique différente varient avec la température mais que leur différence ne varie pas.Theory and experience show that the different threshold voltages of two transistors having undergone different ion implantation vary with temperature but that their difference does not vary.

La présente invention propose un montage à transistors particulièrement simple pour utiliser cette propriété et réaliser, à partir de deux transistors ayant des tensions de seuil différentes, une ou plusieurs sources de courant stables en température et indépendantes de l'alimentation en tension.The present invention provides a particularly simple transistor assembly for using this property and producing, from two transistors having different threshold voltages, one or more current sources stable in temperature and independent of the voltage supply.

Pour cela, on utilise des couples de transistors fonctionnant en régime saturé et reliés entre eux par des connexions telles que l'on puisse faire recopier par un transistor les conditions de courant ou de tension existant dans un autre, jusqu'à faire apparaître aux bornes d'une résistance de valeur connue exactement la différence entre les tensions de seuil de deux transitors ayant subi une implantation ionique différente. Le courant qui traverse cette résistance est stable et on s'arrange pour lui faire traverser au moins un transistor MOS fonctionnant en régime saturé et pour faire recopier ce courant (à un facteur de proportionalité près si on le désire) par au moins un autre transistor MOS ayant la même tension de polarisation grille-source que le premier et la même tension de seuil.For this, couples of transistors operating in saturated conditions are used and connected to each other by connections such that the current or voltage conditions existing in another can be copied by a transistor, until the terminals appear of a resistance of known value exactly the difference between the threshold voltages of two transitors having undergone a different ion implantation. The current which crosses this resistance is stable and one arranges to make it cross at least one MOS transistor operating in saturated mode and to make recopy this current (with a factor of proportionality near if it is desired) by at least one other transistor MOS having the same gate-source bias voltage as the first and the same threshold voltage.

Plus précisément, un montage particulièrement simple selon l'invention consiste à avoir une source de tension alimentant en parallèle deux ensembles de transistors MOS en série, chaque transistor de l'un des ensembles ayant un homologue de même type de canal dans l'autre ensemble; chaque ensemble comporte trois transistors et les rapports de géométrie des transistors homologues sont les mêmes pour tous les transistors des ensembles; les premiers transistors, d'un premier type de canal, ont la même tension de seuil et ont leurs grilles réunies, celui du second ensemble ayant en outre sa grille réunie à son drain; les seconds transistors, d'un second type de canal opposé au premier, ont la même tension de seuil et ont leurs grilles réunies, celui du premier ensemble ayant en outre sa grille réunie à son drain; les troisième transistors, du second type de canal, ont respectivement leur grille réunie à leur drain et ont des tensions de seuil différentes (l'un d'eux par exemple n'ayant pas subi comme les autres transistors de même type une implantation ionique destinée à abaisser en valeur absolue sa tension de seuil, ou, réciproquement, ayant lui seul subi une implantation ionique destinée à augmenter en valeur absolue sa tension de seuil). Une résistance de valeur connue, intégrée ou non, est insérée en série entre le second et le troi sième transistor de l'un des ensembles. Enfin, au moins un transistors MOS supplémentaire est prévu, en dehors des deux ensembles, pour servir de générateur de courant d'alimentation constant et stable, ce transistor ayant sa source et sa grille reliées à la source et à la grille du premier ou du troisième transistor de l'un des ensembles et ayant même tension de seuil que le transistor auquel il est relié pour recopier le courant qui traverse ce dernier (à un facteur de proportiona lité connu près).More specifically, a particularly simple assembly according to the invention consists in having a voltage source supplying in parallel two sets of MOS transistors in series, each transistor of one of the sets having a counterpart of the same type of channel in the other set. ; each set comprises three transistors and the geometry ratios of the homologous transistors are the same for all the transistors of the sets; the first transistors, of a first type of channel, have the same threshold voltage and have their gates joined, that of the second assembly further having its gate joined to its drain; the second transistors, of a second type of channel opposite to the first, have the same threshold voltage and have their gates joined, that of the first assembly further having its gate joined to its drain; the third transistors, of the second type of channel, have respectively their gate joined to their drain and have different threshold voltages (one of them for example having not undergone like the other transistors of the same type an ion implantation intended to lower its threshold voltage in absolute value, or, conversely, having alone undergone an ion implantation intended to increase its threshold voltage in absolute value). A resistor of known value, integrated or not, is inserted in series between the second and the third transistor of one of the assemblies. Finally, at least one additional MOS transistor is provided, apart from the two sets, to serve as a constant and stable supply current generator, this transistor having its source and its gate connected to the source and to the gate of the first or of the third transistor of one of the assemblies and having the same threshold voltage as the transistor to which it is connected in order to copy the current flowing through the latter (to within a proportionality factor known).

Plusieurs transistors supplémentaires peuvent être prévus, ayant chacun leur grille et leur source reliées à la grille et à la source respectivement du premier ou du troisième transistor de l'un des ensembles. Chacun de ces transistors supplémentaires sert de source de courant stable puisqu'il recopie le courant stable dans la résistance. Le ou les transistors supplémentaires ont un facteur de géométrie connu par rapport aux transistors auxquels ils sont reliés, de sorte que le courant qu'ils recopient est dans un rapport connu avec le courant stable dans la résistance.Several additional transistors can be provided, each having their gate and their source connected to the gate and to the source respectively of the first or of the third transistor of one of the assemblies. Each of these additional transistors serves as a stable current source since it copies the stable current into the resistor. The additional transistor or transistors have a known geometry factor with respect to the transistors to which they are connected, so that the current which they copy is in a known relationship with the stable current in the resistor.

Dans un mode de réalisation plus particulier, on peut »répartir« chaque premier ou troisième transistor, ainsi que chaque transistor supplé mentaire, c'est à dire constituer, au lieu d'un seul transistor, une pluralité de transistors individuels partiels tous connectés en parallèle (même connexion de grille, de source et de drain) jouant exactement le même rôle qu'un transistor unique mais pouvant être localisés en plusieurs endroits. Dans ces conditions, on peut prévoir côte à côte un premier ou troisième transistor partiel et un transistor supplémentaire partiel qui lui est associé pour constituer une source de courant stable individuelle recopiant le courant dans la résistance avec un facteur de proportionalité qui dépend de la géométrie de ce transistor supplémentaire partiel.In a more particular embodiment, one can "distribute" each first or third transistor, as well as each additional transistor, that is to say constitute, instead of a single transistor, a plurality of individual transistors. partial dual all connected in parallel (same gate, source and drain connection) playing exactly the same role as a single transistor but can be located in several places. Under these conditions, it is possible to provide side by side a first or third partial transistor and a partial additional transistor associated therewith to constitute an individual stable current source copying the current into the resistor with a proportionality factor which depends on the geometry of this partial additional transistor.

Le montage de transistors selon l'invention permet effectivement d'avoir un courant stable dans la résistance du fait qu'il apparaît aux bornes de celle-ci une tension qui est la différence des tensions de seuil de deux transistors MOS dont l'un seulement a subi une implantation ionique d'ajustement. Cette tension, donc le courant qui traverse la résistance, ne dépend ni de la température ni de la tension d'alimentation du circuit et de plus elle est bien stable dans le temps. Le courant produit dans la résistance dépend de la température dans la même mesure que la résistance, et celle-ci est choisie aussi stable que possible, qu'elle soit intégrée ou extérieure. Si elle est intégrée, on choisira parmi les résistances diffusées celle qui présente le plus faible coefficient de température.The mounting of transistors according to the invention effectively makes it possible to have a stable current in the resistor because it appears at the terminals thereof a voltage which is the difference of the threshold voltages of two MOS transistors of which only one has undergone an adjustment ion implantation. This voltage, therefore the current flowing through the resistor, does not depend on the temperature or the supply voltage of the circuit and moreover it is very stable over time. The current produced in the resistor depends on the temperature to the same extent as the resistor, and the latter is chosen to be as stable as possible, whether integrated or external. If it is integrated, one will choose among the resistances diffused that which presents the lowest coefficient of temperature.

En gros et pour résumer, on peut dire que le montage de l'invention comprend un premier couple de transistors homologues dont l'un recopie le courant de l'autre (à un facteur près), un deuxième couple de transistors homologues dont l'un recopie la tension de source de l'autre, un troisième couple de transistors homologues mais à tensions de seuil différentes que engendre une différence de tension, une résistance en série avec l'un des transistors du troisième couple pour rattraper cette différence de tension, et au moins un transistor supplémentaire de recopie (à un facteur près) du courant dans l'un des transistors précédents. La clef de l'invention réside dans la correspondance des rapports de facteurs de géométrie de tous les couples de transistors homologues, et dans la correspondance exacte des tensions de seuil de tous les couples de transistors homologues sauf l'un d'eux qui doit justement engendrer une différence de tension. Il faut aussi s'assurer que la tension de seuil du ou des transistors supplémentaires de recopie de courant est bien la même que la tension de seuil du transistor auquel sa grille et sa source sont reliées.Basically and to summarize, we can say that the arrangement of the invention comprises a first pair of homologous transistors, one of which copies the current of the other (to within a factor), a second pair of homologous transistors, the a copy of the source voltage of the other, a third pair of homologous transistors but at different threshold voltages that generates a voltage difference, a resistance in series with one of the transistors of the third couple to make up for this voltage difference, and at least one additional transistor for copying (to within a factor) of the current in one of the preceding transistors. The key to the invention resides in the correspondence of the ratios of geometry factors of all the pairs of homologous transistors, and in the exact correspondence of the threshold voltages of all the couples of homologous transistors except one of them which must precisely generate a voltage difference. It must also be ensured that the threshold voltage of the additional current copying transistor (s) is indeed the same as the threshold voltage of the transistor to which its gate and its source are connected.

D'autres caractéristiques et avantages de l'invention apparaitront à la lecture de la description détaillée qui suit et qui est faite en référence au dessin annexé dans lequel:

  • - la figure 1 représente un schéma détaillé d'un exemple de réalisation de l'invention,
  • - la figure 2 représente un autre exemple avec une variante d'exécution.
Other characteristics and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawing in which:
  • FIG. 1 represents a detailed diagram of an exemplary embodiment of the invention,
  • - Figure 2 shows another example with an alternative embodiment.

Le circuit de la figure 2 est donc destiné à produire une sourve de courant stable destinée à alimenter une partie de circuit analogique 10 qui est en principe intégrée sur le même substrat que la sourve de courant selon l'invention. Ce circuit analogique peut être par exemple une partie d'amplificateur: de nombreux amplificateurs différentiels notamment utilisent des sources de courant constant.The circuit of FIG. 2 is therefore intended to produce a stable current source intended to supply part of the analog circuit 10 which is in principle integrated on the same substrate as the current source according to the invention. This analog circuit can for example be an amplifier part: many differential amplifiers in particular use constant current sources.

L'ensemble du circuit intégré (partie analogique 10 et source de courant selon l'invention) est alimenté par exemple par des niveaux de tension symétriques +V et -V.The entire integrated circuit (analog part 10 and current source according to the invention) is supplied for example by symmetrical voltage levels + V and -V.

Entre les conducteurs d'alimentation à +V et ­V sont connectés en parallèle deux ensembles similaires de trois transistors en série chacun, respectivement T1, T2 et T3 pour le premier ensemble, et T'1, T'2 et T'3 pour le deuxième ensemble. Le transistor Ti est l'homologue du transistor T'1, le transistor T2 du transistor T'2 et le transistor T3 du transistor T'3. Les transistors T1 et T'1 sont à canal N (par exemple); les transistors T2, T'2 et T3, T'3 sont du type de canal opposé, en l'occurence P dans l'exemple choisi.Between the supply conductors at + V and V are connected in parallel two similar sets of three transistors in series each, respectively T 1 , T 2 and T 3 for the first set, and T ' 1 , T' 2 and T ' 3 for the second set. The transistor Ti is the counterpart of the transistor T ' 1 , the transistor T 2 of the transistor T' 2 and the transistor T 3 of the transistor T ' 3 . The transistors T 1 and T ' 1 are N-channel (for example); the transistors T 2 , T ' 2 and T 3 , T' 3 are of the opposite channel type, in this case P in the example chosen.

Les transistors T1, T2 et T3 peuvent avoir des géométries quelconques; les transistors T'i, T'2 et T'3 ont des géométries dans le même rapport que les transistors T1, T2 et T3, c'est-à-dire qu'll existe un coefficient de proportionalité constant entre les transistors homologues des deux ensembles en série.The transistors T 1 , T 2 and T 3 can have any geometry; the transistors T ' i , T' 2 and T ' 3 have geometries in the same relationship as the transistors T 1 , T 2 and T 3 , that is to say that there exists a constant coefficient of proportionality between the homologous transistors of the two sets in series.

De plus, les transistors homologues T1 et T'1 ont une même tension de seuil; les transistors homologues T2 et T'2 ont aussi une même tension de seuil; par contre les transistors T3 et T'3 ont des tensions de seuil différentes, respectivement VT3 et V'T3. Par exemple, tous les transistors MOS à canal P du circuit intégré, et notamment les transistors T2, T'2 et T'3, ont subi une implantation ionique à travers leur isolement de grille pour abaisser leur tension de seuil. Le transistor T3 ou T'3 au contraire a été masqué pendant cette opération de sorte qu'il conserve une tension de seuil plus élevée en valeur absolue que le transistor T'3 ou T3 et les autres.In addition, the homologous transistors T 1 and T ' 1 have the same threshold voltage; the homologous transistors T 2 and T ' 2 also have the same threshold voltage; on the other hand the transistors T 3 and T ' 3 have different threshold voltages, respectively V T3 and V' T3 . For example, all the P-channel MOS transistors of the integrated circuit, and in particular the transistors T 2 , T ' 2 and T' 3 , have undergone ion implantation through their gate isolation to lower their threshold voltage. The transistor T 3 or T ' 3 on the contrary was masked during this operation so that it retains a higher threshold voltage in absolute value than the transistor T' 3 or T 3 and the others.

De plus, dans le deuxième ensemble en série T'i, T'2, T'3 on a incorporé une résistance R1 en série entre le drain du transistor T'2 et la source du transistor T'a. Il faut noter ici que cette résistance R1 peut être incorporée au circuit intégré, et être alors réalisée sous forme d'une portion de silicium dopé, ou bien elle peut être extérieure au circuit et reliée à celui-ci par l'intermédiaire de broches de connexion extérieure et de liaisons métallisées.In addition, in the second set in series T'i, T ' 2 , T' 3 a resistance R 1 has been incorporated in series between the drain of transistor T ' 2 and the source of transistor T'a. It should be noted here that this resistor R 1 can be incorporated in the integrated circuit, and then be produced in the form of a portion of doped silicon, or it can be external to the circuit and connected to the latter by means of pins of external connection and metallic connections.

Le transistor T'i a son drain relié à sa grille qui elle-même est reliée à la grille du transistor Ti, selon un montage classique dit »en miroir de courants«, de sorte que le courant dans le transistor T1 recopie le courant dans le transistor T'1 à un facteur de proportionalité près que est le rapport K entre la géométrie du transistor Ti et la géométrie du transistor T'i (qui est aussi le rapport entre T2 et T'2 et le rapport entre T3 et T'3).The transistor T ' i has its drain connected to its gate which itself is connected to the gate of the transistor T i , according to a conventional arrangement known as "current mirror", so that the current in the transistor T 1 copies the current in the transistor T ' 1 to a factor of proportionality that is the ratio K between the geometry of the transistor T i and the geometry of the transistor T'i (which is also the ratio between T 2 and T' 2 and the ratio between T 3 and T ' 3 ).

Cette recopie du courant provient du fait que les transistors T1 et T'1 ont même tension grille-source et même tension de seuil, et qu'ils fonctionnent en régime saturé; or, en régime saturé, le courant est donné par la formule.

Figure imgb0001
où VGS est la tension grille-source, VT la tension de seuil, Z/L le facteur de géométrie et k un coefficient qui dépend de la technologie utilisée (technologie qui est la même pour tous les transistors du circuit intégré).This copying of the current comes from the fact that the transistors T 1 and T ' 1 have the same gate-source voltage and the same threshold voltage, and that they operate in saturated mode; however, in saturated regime, the current is given by the formula.
Figure imgb0001
 where V GS is the gate-source voltage, V T the threshold voltage, Z / L the geometry factor and k a coefficient which depends on the technology used (technology which is the same for all the transistors of the integrated circuit).

Pour un même VGS et un même VT, on voit que le courant I1 dans T1 est bien proportionnel au courant I'1 dans T'1, le facteur de proportionalité étant le rapport des géométries des deux transistors.For the same V GS and the same V T , we see that the current I 1 in T 1 is indeed proportional to the current I ' 1 in T' 1 , the proportionality factor being the ratio of the geometries of the two transistors.

Le drain du transistor T2 est relié à sa grille, qui est reliée elle-même aussi à la grille du transistor T'2. Il s'agit encore d'un montage en miroir de courants, mais cette fois ci, les sources des transistors T2 et T'z ne sont pas reliées l'une à l'autre de sorte que la tension grille-source des transistors T2 et T'2 n'est pas directement imposée. Par contre, le courant qui traverse T2 est le même que le courant qui traverse T1 (I1) et le courant qui traverse T'2 est le même que le courant qui traverse T'1 (I'1).The drain of transistor T 2 is connected to its gate, which is itself also connected to the gate of transistor T ' 2 . It is also a mirror assembly of currents, but this time, the sources of the transistors T 2 and T'z are not connected to each other so that the gate-source voltage of the transistors T 2 and T ' 2 is not directly imposed. On the other hand, the current which crosses T 2 is the same as the current which crosses T 1 (I 1 ) and the current which crosses T ' 2 is the same as the current which crosses T' 1 (I ' 1 ).

Les courants dans T2 et T'2 étant imposés et les tensions-grilles étant imposées, la formule de courant donnée précédemment permet de calculer les tensions grille-source des transistors T2 et T'2. Or, ces transistors ont même tension de seuil; ils ont un rapport de géométries K, et ils sont justement parcourus par des courants I1 et I'1 dans un rapport K (I1 = Kl'1). Ceci veut dire que leurs tensions grille-source seront les mêmes. Comme ils ont une tension de grille commune, il en résulte que, sans qu'il y ait une liaison directe entre leurs sources, les tensions V2 et V'2 de leurs sources seront identiques.The currents in T 2 and T ' 2 being imposed and the gate voltages being imposed, the current formula given previously makes it possible to calculate the gate-source voltages of the transistors T 2 and T' 2 . However, these transistors have the same threshold voltage; they have a ratio of geometries K, and they are precisely traversed by currents I 1 and I ' 1 in a ratio K (I 1 = Kl' 1 ). This means that their gate-source voltages will be the same. As they have a common gate voltage, it follows that, without there being a direct connection between their sources, the voltages V 2 and V ′ 2 of their sources will be identical.

Par conséquent, de même que le transistor Ti recopiait le courant dans le transistor T'i, de même, le transistor T2 recopie la tension de source du transistor T'2.Consequently, just as the transistor T i copied the current in the transistor T'i, so also the transistor T 2 copied the source voltage of the transistor T ' 2 .

En ce qui concerne les transistors T3 et T'3, ils ont leurs sources reliées à la tension d'alimentation +V; ils ont de préférence leur grille reliée à leur drain; en appliquant toujours la même formule de calcul du courant en régime saturé, et en tenant compte de ce que les courants I1 et I'1 qui traversent T3 et T'3 sont dans le rapport K des géométries des transistors T3 et T'3, on en déduit immédiatement qu'il apparaît entre les drains (c'est-à-dire les grilles) des transistors T3 et T'3 une différence de tension qui est justement égale à la différence des tensions de seuil de ces transistors. En d'autres mots, si V3 est la tension de drain du transistor T3 et V'3 la tension de drain du transistor T'3 on a

Figure imgb0002
Comme le drain de T3 est relié à la source de T2 on a V3=V2; comme d'autre part la résistance R, est insérée entre le drain de T'3 et la source de T'2, on a
Figure imgb0003
comme enfin on a dit que V2 = V'2 par recopie de tension, on en déduit immédiatement que la chute de tension R1 I'1 dans la résistance R1 est égale à la différence des tensions de seuil des transistors T'3 et T3. Le courant I'1 est donc un courant de valeur bien déterminée stable dans le temps, stable en température, et indépendant de la tension d'alimentation +V, -V.As regards the transistors T 3 and T ' 3 , they have their sources connected to the supply voltage + V; they preferably have their grid connected to their drain; by always applying the same formula for calculating the current in saturated regime, and taking into account that the currents I 1 and I ' 1 which cross T 3 and T' 3 are in the ratio K of the geometries of the transistors T 3 and T ' 3 , we immediately deduce that it appears between the drains (that is to say the gates) of the transistors T 3 and T' 3 a voltage difference which is precisely equal to the difference of the threshold voltages of these transistors. In other words, if V 3 is the drain voltage of transistor T 3 and V ' 3 the drain voltage of transistor T' 3 we have
Figure imgb0002
 As the drain of T 3 is connected to the source of T 2 we have V 3 = V 2 ; as on the other hand the resistance R, is inserted between the drain of T ' 3 and the source of T' 2 , we have
Figure imgb0003
 as finally we said that V 2 = V ' 2 by voltage copying, we immediately deduce that the voltage drop R 1 I' 1 in the resistor R 1 is equal to the difference of the threshold voltages of the transistors T ' 3 and T 3 . The current I ′ 1 is therefore a current of well determined value stable over time, stable in temperature, and independent of the supply voltage + V, -V.

On notera également que le courant I1 dans le premier ensemble en série des transistors Ti, T2, T3, est également un courant stable puisqu'il recopie le courant I'1 à un facteur de proportionalité près qui est le rapport K entre les géométries des transistors du premier et du second ensemble en série. Ce rapport est indépendant de la température bien entendu.It will also be noted that the current I 1 in the first set in series of the transistors T i , T 2 , T 3 , is also a stable current since it copies the current I ' 1 to a factor of proportionality which is the ratio K between the geometries of the transistors of the first and second set in series. This ratio is independent of the temperature of course.

On prévoit alors pour établir un courant d'alimentation constant ii dans une partie de circuit analogique 10, de recopier le courant I1 ou I'1 avec un montage classique en miroir de courants, c'est-à-dire en utilisant au moins un transistor supplémentaire T"1, et on donne à ce transistor T"1 une tension grille-source égale à celle d'un autre transistor parcouru soit par I1 soit par I'1, le transistor T"1 ayant même tension de seuil que le transistor dont il recopiera la tension grille-source. Dans ces conditions, le courant i1 dans le transistor T"1 recopiera le courant I1 ou le courant I'1 avec un facteur de proportionalité qui sera le rapport entre la géométrie du transistor T"1 et le transistor qui aura même tension grille-source que lui.It is then planned to establish a constant supply current ii in an analog circuit part 10, to copy the current I 1 or I ′ 1 with a conventional assembly in mirror of currents, that is to say using at least an additional transistor T " 1 , and this transistor T" 1 is given a gate-source voltage equal to that of another transistor passed through either by I 1 or by I ' 1 , the transistor T " 1 having the same threshold voltage than the transistor whose gate-source voltage it will copy. Under these conditions, the current i 1 in the transistor T " 1 will copy the current I 1 or the current I ' 1 with a proportionality factor which will be the ratio between the geometry of the transistor T " 1 and the transistor which will have the same gate-source voltage as it.

Dans l'exemple représenté sur la figure 1, on a prévu à titre d'exemple de relier la grille du transistor T"i à celle du transistor T'3, les sources de ces deux transistors étant également reliées à la connexion d'alimentation V+. Le transistor T", aura même tension de seuil que le transistor T'3; si le rapport de géométrie entre le transistor T"1 et le transistor T'3 est K', on aura i1 = K' I'1.In the example shown in FIG. 1, provision has been made, by way of example, to connect the gate of transistor T "i to that of transistor T ' 3 , the sources of these two transistors also being connected to the supply connection. V +. The transistor T ", will have the same threshold voltage as the transistor T '3; if the geometry ratio between transistor T " 1 and transistor T ' 3 is K', we will have i 1 = K 'I' 1 .

Le transistor T"1 est alors mis en série entre le circuit analogique 10 et la connexion d'alimentation V+, et on produit ainsi un courant stable rentrant i1 dans le circuit 10.The transistor T " 1 is then placed in series between the analog circuit 10 and the supply connection V +, and a stable current returning i 1 is thus produced in the circuit 10.

Comme on l'a représenté sur la figure 1, on peut également produire un courant sortant i'1 en connectant un transistor de recopie T‴1, en série entre la connexion d'alimentation -V et le circuit analogique 10. Le courant sortant I'1 peut très bien être prévu isolément ou en plus du courant I1 et il n'est pas forcément égal au courant I1. Le transistor T‴1 recopie le courant dans le transistor T'1 (ou T1) si on relie sa grille et sa source à la grille et à la source de T'1 (ou T1 ).As shown in FIG. 1, it is also possible to produce an outgoing current i ' 1 by connecting a feedback transistor T ‴ 1 , in series between the supply connection -V and the analog circuit 10. The outgoing current I ' 1 may very well be provided in isolation or in addition to the current I 1 and it is not necessarily equal to the current I 1 . The transistor T ‴ 1 copies the current in the transistor T ' 1 (or T 1 ) if its gate and its source are connected to the gate and to the source of T' 1 (or T 1 ).

Si K" est le rapport entre la géométrie du transistor T‴1 et celle du transistor T'1, ces deux transistors ayant même tension de seuil, le courant i'1 sera K" I'1.If K "is the ratio between the geometry of transistor T ‴ 1 and that of transistor T ' 1 , these two transistors having the same threshold voltage, the current i' 1 will be K" I ' 1 .

On peut noter qu'on aurait pu produire un autre courant de référence d'alimentation à partir d'un transistor supplémentaire ayant sa grille et sa source connectées à la grille et à la source du transistor T3 au lieu de T'3, mais alors il faudrait prévoir que le transistor supplémentaire de recopie ainsi connceté ait une tension de seuil égale à celle du transistor T3 qui n'est pas la même que les autres.It may be noted that another reference power supply current could have been produced from an additional transistor having its gate and its source connected to the gate and to the source of the transistor T 3 instead of T ' 3 , but then it is necessary should provide that the additional copying transistor thus connceté has a threshold voltage equal to that of the transistor T 3 which is not the same as the others.

Sur la figure 1 on n'a représenté qu'un seul circuit analogique 10 alimenté par un courant i1 rentrant et un courant i'1 sortant; on peut évidemment prévoir plusieurs circuits analogiques chacun alimenté par un transistor de recopie ayant sa grille et sa source reliées à l'un des transistors parcourus par les courants stables I1 ou I'1 (en pratique les transistors T1,T'1 et T'3.In FIG. 1, only one analog circuit 10 is represented, supplied by a re-entering current i 1 and an outgoing current i '1; it is obviously possible to provide several analog circuits each supplied by a feedback transistor having its gate and its source connected to one of the transistors traversed by the stable currents I 1 or I ' 1 (in practice the transistors T 1 , T' 1 and T ' 3 .

Bien entendu, dans tout ce qui précède, quand on parle d'un transistor de recopie de courant, il s'agit d'un transistor de même type de canal que celui auquel sa grille et sa source sont reliées.Of course, in all of the above, when we speak of a current feedback transistor, it is a transistor of the same type of channel as that to which its gate and its source are connected.

A la figure 2, on a représenté un circuit d'alimentation en courant tout à fait analogue à celui de la figure 1, dans lequel on cherche à alimenter plusieurs circuits analogiques 10, 20, etc., nécessitant chacun une référence de courant stable particulière et éventuellement disposés en des endroits différents de la pastille de circuit intégré global.In Figure 2, there is shown a current supply circuit quite similar to that of Figure 1, in which one seeks to supply several analog circuits 10, 20, etc., each requiring a particular stable current reference and possibly arranged in different places of the global integrated circuit chip.

On retrouve sur la figure 2 exactement le premier ensemble en série de trois transistors Ti, T2 et T3 parcourus par le courant I1; on retrouve la résistance en série Ri parcourue par le courant I'1, ainsi que le transistor T'2 parcouru également par ce courant. La différence avec le schéma de la figure 1 réside dans le fait que le transistor T'3 et/ou le transistor T'1 d'une part, ainsi que le transistor T"1 et/ou le transistor T‴1 d'autre part, sont réalisés non pas sous la forme de transistors uniques mais sous la forme d'une pluralité de transistors individuels partiels tous connectés de la même manière (même connexion de grille, de source et de drain) jouant exactement le rôle d'un transistor unique mais pouvant être localisés en plusieurs endroits du circuit intégré. Ainsi, le transistor T'3 se présente sous forme de plusieurs transistors T'31, T'32 . . . etc. tous connectés en parallèle. Le transistor T'1 se présente sous la forme de plusieurs transistors T'11, T 12 . . . etc. Le transistor T"1 se présente sous forme de plusieurs transistorT"11, T"12 . . . etc. Et le transistor T‴1 se présente sous forme de plusieurs transistors T‴11, T‴12 . . . etc.We find in Figure 2 exactly the first set in series of three transistors Ti, T 2 and T 3 traversed by the current I 1 ; we find the series resistance Ri traversed by the current I ' 1 , as well as the transistor T' 2 also traversed by this current. The difference with the diagram of FIG. 1 resides in the fact that the transistor T ' 3 and / or the transistor T' 1 on the one hand, as well as the transistor T " 1 and / or the transistor T ‴ 1 on the other part, are produced not in the form of single transistors but in the form of a plurality of individual partial transistors all connected in the same way (same gate, source and drain connection) playing exactly the role of a transistor single but can be located in several places of the integrated circuit. Thus, the transistor T '3 is in the form of a plurality of transistors T' 31, T '32... etc. all connected in parallel. the transistor T' 1 arises in the form of a plurality of transistors T '11, T 12,... etc. the transistor T "1 is in the form of several transistorT" 11, T "12. . . etc. And the transistor T ‴ 1 is in the form of several transistors T ‴ 11 , T ‴ 12 . . . etc.

On peut alors s'arranger pour localiser un transistor partiel de la pluralité constituant T'3 à côté d'un transistor partiel respectif de la pluralité du type T"1; de même un transistor partiel de T'i à côté d'un transistor du type de T"'1. Chacun des transistors T"11, T"12 etc., ou T‴11. T‴12 etc., recopie le courant d'un transistor partiel T'31, T'32 . . . etc. ou T'11, T'12 . . . etc.We can then arrange to locate a partial transistor of the plurality constituting T ' 3 next to a respective partial transistor of the plurality of the type T "1; likewise a partial transistor of T'i next to a transistor of the type of T "' 1 . Each of the transistors T " 11 , T" 12 etc., or T ‴ 11 . T ‴ 12 etc., copies the current of a partial transistor T '31 , T' 32 . . . etc. or T '11, T' 12. . . etc.

Bien entendu, les courants d'alimentation stables qui en résultent, i11, i12 . . . ou i'11, i'12 . . . sont des courants de recopie de l', dans un rapport de proportionalité correspondant au rapport des facteurs de géométrie des transistors juxtaposés qui donnent naissance à ces courants de recopie.Of course, the resulting stable supply currents, i 11 , i 12 . . . or i '11, i' 12. . . are currents of recopy of the, in a proportionality ratio corresponding to the ratio of the geometry factors of the juxtaposed transistors which give rise to these recopy currents.

Claims (6)

1. Integrated current generator of CMOS-technology, comprising a voltage source (+V, -V) feeding in parallel two sets of series connected MOS transistors, each transistor of one of the sets having a corresponding transistor of the same channel type in the other set, characterized in that each set comprises three transistors (T1, T2, T3, T'1, T'2, T'3), in that the geometrical ratios of corresponding transistors are the same for all of the transistors of the sets, in that the first transistors (T1, T'1) of a first channel type have the same threshold voltage and have their gates interconnected, that of the second set having its gate further connected to its drain, in that the second transistors (T2, T'2) of a second channel type opposite the first have the same threshold voltage and have their gates interconnected, that (T2) of the first set having its gate further connected to its drain, in that the third transistors (T3, T'3) of the second channel type have their gates respectively connected to their drains and have different threshold voltages, a resistor (R1) of known value being inserted in series between the second and the third transistors of one of the sets, at least one further MOS transistor (T"1, T'"1) being provided outside the sets for being used as a constant supply current generator, this transistor (T"1, T‴1) having its source and its gate respectively connected to the source and to the gate of the first or of the third transistor (T'1, T'3, T1, T3) of one of the sets and having the same threshold voltage as the transistor to which it is connected in this manner.
2. Current generator according to claim 1, characterized by the fact that one of the third transistors (T3, T'3) has been subjected to an ion implantation suitable for reducing the absolute value of its threshold voltage, the other of the third transistors (T'3, T3) having been masked during this operation.
3. Current generator according to claim 2, characterized by the fact that all the transistors of the second channel type, opposite to the first, of the current generator have been subjected to said ion implantation, except for one of the third transistors (T3, T'3) which has been masked, or reciprocally.
4. Current generator according to claim 1, characterized by the fact that a plurality of further transistors are provided (T"11, T"12; T"'11, T"'12) each having its gate and its source respectively connected to the gate and to the source of the first or of the third transistor of one of the sets for producing a plurality of current references.
5. Current generator according to claim 4, characterized by the fact that the further transistors have geometrical designs in known relations selected with the geometrical designs of the transistors to which they are connected.
6. Current generator according to any of claims 1 to 5, characterized by the fact that the first and/or the third transistor (T'1, T'3) of the set including the series resistor are made up of a plurality of MOS transistors (T'11, T'12; T'31, T'32) mounted in parallel and connected in the same manner, and that the further transistors are also made up of a plurality of partial MOS transistors (T"11, T"12, T‴11, T‴12) mounted in parallel and connected in the same manner, one further partial transistor being associated with each first and/or third partial transistor (T'31, 1'11) for forming an individual current source.
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FR2494519B1 (en) 1984-10-12
EP0052553A1 (en) 1982-05-26
DE3169594D1 (en) 1985-05-02
JPS57111711A (en) 1982-07-12
US4442398A (en) 1984-04-10
FR2494519A1 (en) 1982-05-21
JPH0261052B2 (en) 1990-12-19

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