EP0049272B1 - Herstellung von mikrominiaturanordnungen unter verwendung der plasmaätzung von silizium mit fluorhaltigen gasverbindungen - Google Patents

Herstellung von mikrominiaturanordnungen unter verwendung der plasmaätzung von silizium mit fluorhaltigen gasverbindungen Download PDF

Info

Publication number
EP0049272B1
EP0049272B1 EP81901056A EP81901056A EP0049272B1 EP 0049272 B1 EP0049272 B1 EP 0049272B1 EP 81901056 A EP81901056 A EP 81901056A EP 81901056 A EP81901056 A EP 81901056A EP 0049272 B1 EP0049272 B1 EP 0049272B1
Authority
EP
European Patent Office
Prior art keywords
etching
fluorine
silicon
chlorine
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP81901056A
Other languages
English (en)
French (fr)
Other versions
EP0049272A1 (de
EP0049272A4 (de
Inventor
Daniel Lawrence Flamm
Dan Maydan
David Nin-Kou Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of EP0049272A1 publication Critical patent/EP0049272A1/de
Publication of EP0049272A4 publication Critical patent/EP0049272A4/de
Application granted granted Critical
Publication of EP0049272B1 publication Critical patent/EP0049272B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Definitions

  • This invention relates to a method for fabricating a microminiature device of the type as defined in the preamble clause of claim 1.
  • Such a method is known from GB-A-2026 395, which describes plasma etching of silicon with CF 3 CI, CF 3 Br and the like.
  • the invention provides a plasma etching process for use in a microminiature device fabricating method in the course of which a silicon surface of the device is to be etched with high selectivity relative to other surfaces of the device in a dry etching apparatus that comprises a plasma established between anode and cathode electrodes, one of which electrodes holds the device to be etched.
  • the plasma results from the imposition of an electric field across a gaseous environment between the electrodes.
  • the gaseous environment comprises a fluorine-containing gaseous compound that provides in the apparatus under the influence of the electric field silicon-etching fluorine species and reaction products that do not etch the other surfaces of the device to any substantial extent relative to the etching of the silicon surface.
  • the fluorine-containing gaseous compound comprises at least one of chlorine trifluoride, bromine trifluoride and iodine trifluoride. If only said fluorine-containing gaseous compound is introduced into the etching chamber, the edge profile of the etched material is completely isotropic.
  • various other gases for example chlorine, to the fluorine-containing gaseous compound, a mixed etching plasma is formed in which the extent of undercutting (maximum lateral etch) is a function of the volume percent of the additive included in the mixture.
  • a substantially uniform and relatively high etching rate for silicon is achieved at relatively low power levels.
  • the etching rate for silicon is significantly higher than the various other materials (for example, silicon dioxide) included in LSI devices.
  • the edge profile achieved by the process is substantially independent of feature size and of the spacing between features.
  • silicon is employed herein and in the claims in a generic sense to encompass doped and undoped monocrystalline and polycrystalline silicon.
  • the workpieces to be etched are positioned on one of the electrodes included in the reaction chamber.
  • the workpieces are placed on the grounded anode electrode.
  • the workpieces are placed on the driven cathode electrode thereof. Either type of apparatus can be used with a fluorine-containing gaseous compound to effect plasma etching of silicon.
  • workpieces previously processed in a plasma etching apparatus wherein the workpieces were mounted on the driven cathode electrode are to be further processed in accordance with the present invention. Accordingly, the main emphasis herein will be directed to etching techniques as practiced in an apparatus in which the workpieces are also placed on the driven cathode electrode. In that way, a continuous high-throughput fabrication sequence is realized.
  • Reactive plasma etching is carried out in, for example, a parallel-plate reactor of the type depicted in Fig. 1 or in a so-called multifaceted reactor of the type shown in Fig. 2.
  • the particular illustrative parallel-plate reactor shown in Fig. 1 comprises an etching chamber 10 defined by a cylindrical nonconductive member 12 and two conductive end plates 14 and 16.
  • the member 12 is made of glass and the plates 14 and 16 are each made of aluminum.
  • the depicted reactor includes a conductive workpiece holder 18 also made, for example, of aluminum.
  • the bottom of the holder 18 constitutes a 25.4 cm. (10-inch) circular surface designed to have seven 7.6 cm. (3-inch) wafers placed thereon.
  • Wafers 20, whose bottom (i.e., front surfaces are to be etched, are indicated in Fig. 1 as being mounted on the bottom surface of the holder 18.
  • the wafers 20 are maintained in place on the holder 18 by a cover plate 24 having apertures therethrough.
  • the apertures are positioned in aligned registry with the wafers 20 and are each slightly smaller in diameter than the respectively aligned wafers. In that way, a major portion of the front surface of each wafer is exposed for etching.
  • the cover plate 24 is secured to the holder 18.
  • the cover plate 24 included in the etching apparatus of Fig. 1 is made of a low-sputter-yield material that does not react chemically with the etching gas to form a nonvolatile material. Suitable such materials include anodized aluminum and fused silica.
  • the workpiece holder 18 shown in Fig. 1 is capacitively coupled via a radio-frequency tuning network 26 to a radio-frequency generator 28 which, by way of example, is designed to drive the holder 18 at a frequency of 13.56 megahertz. Further, the holder 18 is connected through a filter network, comprising an inductor 30 and a capacitor 32, to a meter 34 that indicates a direct-current voltage that approximates the peak value of the radio-frequency voltage applied to the holder 18.
  • the end plate 14 is connected to a point of reference potential such as ground.
  • the plate 14 is the anode of the depicted reactor.
  • the workpiece holder 18 constitutes the driven cathode of the reactor.
  • the anode-to- cathode separation was approximately 25.4 cm (10 inches) and the diameter of anode plate was approximately 43.2 cm (17 inches).
  • the end plate 16 of the Fig. 1 arrangement is also connected to ground. Additionally, an openended cylindrical shield 36 surrounding the holder 18 is connected to the plate 16 and thus to ground. The portion of the holder 18 that extends through the plate 16 is electrically insulated therefrom a nonconductive bushing 38.
  • a fluorine-containing gaseous compound atmosphere is established in the chamber 10 of Fig. 1. Gas is controlled to flow into the indicated chamber from a standard supply 40. Additionally, a prescribed low pressure condition is maintained in the chamber by means of a conventional pump system 42.
  • a reactive plasma is generated in the chamber 10.
  • the plasma established therein has a uniform dark space in the immediate vicinity of the workpiece surfaces to be etched. Volatile products formed at the workpiece surfaces during the etching process are exhausted from the chamber by the system 42.
  • the system depicted in Fig. 2 comprises a cylindrical etching chamber 100 made of an electrically conductive material such as aluminum or stainless steel. Centrally mounted within the chamber 100 is a workpiece holder 102.
  • the particular illustrative holder 102 shown in Fig. 2 includes six flat surfaces or facets. By way of a specific example, each such surface is designed to have four 15.2 cm. (6-inch) wafers mounted thereon.
  • One such wafer is designated in Fig. 2 by reference numeral 104.
  • a supported grid element 106 Interposed between the chamber 100 and the workpiece holder 102 of Fig. 2 is a supported grid element 106.
  • the workpiece holder of the Fig. 2 apparatus is capacitively coupled to and driven by a radio-frequency generator 108 and associated conventional elements.
  • a gas suppy 110 for introducing a specified gas or mixture of gases into the depicted reaction chamber and a standard pump system 112 for establishing a prescribed low-pressure condition in the chamber.
  • Fig. 3 is a sectional depiction of a portion of one of the wafers to be etched in the chamber 10 of Fig. 1 or in the chamber 100 of Fig. 2.
  • a conventionally patterned masking layer 46 is shown formed on a substrate 48 made of mono- crystalline silicone which, for example, is either p-or n-doped to exhibit a resistivity of approximately 1-to-10 ohm-centimeters.
  • the unmasked portions of the silicon substrate 48 are isotropically etched to form recesses therein, as indicated by dashed line 49.
  • the recess 49 etched in the substrate 48 of Fig. 3 represents, for example one step in the process of fabricating an LSI device in which dielectric material subsequently formed in the depicted recess serves to electrically isolate adjacent elements in an LSI chip that includes the substrate 48.
  • Isotropic etching of polysilicon layers is of significant importance in the fabrication of LSI devices.
  • MOS RAMs it is typically necessary in the fabrication sequence to precisely pattern thin layers of polysilicon.
  • one such device fabrication sequence involves initially anisotropically etching an undoped polysilicon layer commonly referred to as the poly 2 level.
  • the poly 2 level after being anisotropically etched, includes portions that underlie a previously patterned doped polysilicon layer (the so-called poly 1 level), as will be apparent from the detailed discussion hereinbelow in connection with the description of Fig. 7. If these underlying poly 2 portions are not removed from the layered structure being fabricated, faulty devices will likely result. Hence, removal of the underlying poly 2 portions is necessary. Such removal may advantageously be carried out in a dry isotropic etching step of the type described herein.
  • Fig. 4 schematically represents in cross-section a portion of an idealized device structure that includes a polysilicon layer to be etched.
  • a thin [for example, a 50 nanometers (500-Angstrom-unit) thick] layer 50 of silicon dioxide is shown on a mono-crystalline silicon member 52.
  • a layer 54 of polycrystalline silicon approximately 500 nanometers (5000 Angstrom units) thick.
  • a conveniently patterned masking layer 56 is provided on top of the layer 54 to be etched.
  • Fig. 4 is to be considered a generic depiction in which the layer 54 is made of undoped or doped polysilicon. Isotropic etching of the layer 54 of Fig. 4 is represented therein by curved dashed lines 58. A completely isotropic profile is represented by the lines 58. In such a profile, the maximum extent of lateral etching (undercutting), designated a in Fig. 4, equals the thickness b of the etched layer 54.
  • the term "doped" polysilicon is intended to refer to a polysilicon layer to which a dopant such as phosphorous has been added.
  • the dopant concentration in such a layer is controlled to establish a resistivity in the range 20-to-100 ohm-centimeters.
  • Various materials are suitable for forming the patterned masking layers 46 and 56 shown in Figs. 3 and 4. These materials include organic or inorganic resists, silicon dioxide, magnesium oxide, aluminum oxide, titanium, tantalum, tungsten oxide, cobalt oxide, and the refractory silicides of titanium, tantalum and tungsten. Masking layers made of these materials are patterned by utilizing standard lithographic and etching techniques.
  • etching can be carried out in, for example, a parallel-plate reactor of the type shown in Fig. 1 or in a multifaceted reactor of the type shown in Fig. 2.
  • a pressure of about 67 microbar (50) micrometers) is established in the etching chamber.
  • a chlorine trifluoride gas flow into the etching chamber of, for example, approximately 10 cubic centimeters per minute is advantageous.
  • a chlorine trifluoride gas flow of, for example, approximately 30 cubic centimeters per minute is established.
  • a power density of, for example, approximately .06 watts per square centimeter is established at the surfaces of the workpieces to be etched in a multifaceted reactor.
  • the corresponding power density is, for example, .025 watts per square centimeter.
  • monocrystalline silicon, undoped polycrystalline silicon and doped polycrystalline silicon were each isotropically etched in the specified equipments at a rate of approximately 175, 120 and 120 nanometers (1750, 1200 and 1200 Angstrom units) per minute, respectively.
  • Isotropic etching processes of the type specified above have a relatively high differential etch rate with respect to, for example, both silicon dioxide and standard resist materials such as HPR-204 (commercially available from Philip A. Hunt Chemical Corp., Palisades Park, N. J.).
  • HPR-204 commercially available from Philip A. Hunt Chemical Corp., Palisades Park, N. J.
  • the aforespecified particular illustrative processes etch silicon approximately 50 times faster than silicon dioxide and about five times faster than resist.
  • the specified processes also etch silicon approximately 50 times faster than materials such as phosphorus-doped glass and silicon nitride. The practical significance of such relatively high differential etch rates for LSI device fabrication is apparent.
  • isotropic plasma-assisted etching utilizing chlorine trifluoride are illustrative only. More generally, such etching can be carried out be selecting pressures, gas flows and power densities in the ranges 2.7 to 667 microbar (2 to 500 micrometers), 2-to-300 cubic centimeters per minute, and 0.01-to-1 watt per square centimeter, respectively.
  • chlorine trifluoride is dissociated in the reaction chamber under the influence of the applied electric field to produce fluorine atoms that rapidly etch silicon isotropically but that etch other materials such as silicon dioxide relatively slowly.
  • the other reaction products formed in the chamber during etching also attack the other workpiece materials such as silicon dioxide slowly relative to the rate at which silicon is etched.
  • fluorine-containing gaseous compounds are suitable, under specified conditions, for isotropically patterning silicon in a dry etching process with high selectivity relative to other materials such as silicon dioxide. These other compounds also dissociate in the reaction chamber to form fluorine species that etch silicon and to form reaction products that do not etch other materials such as silicon dioxide to any substantial extent relative to the etching of silicon.
  • Such other fluorine-containing gaseous compounds are bromine trifluoride (BrF 3 ) and iodine trifluoride (IF3), and can also be utilized to etch silicon isotropically with high selectivity relative to, for example, silicon dioxide. Such etching is carried out in equipment of the type shown in Fig. 1 or Fig. 2 in a plasma-assisted etching process.
  • plasma-assisted etching with BrF 3 and IF 3 can be carried out by selecting pressures, gas flows and power densities in the ranges specified above for CIF 3 .
  • Each of the aforespecified fluorine-containing gaseous compounds is effective by itself, without any other constituent mixed therewith, to etch silicon isotropically. But, additionally, it is also feasible to selectively change some of the etching parameters by using mixtures of gases.
  • chlorine triflouride may be mixed with an inert gas such as argon or with carbon tetrafluoride or with chlorine to selectively reduce the etching rate of silicon.
  • an inert gas such as argon or with carbon tetrafluoride or with chlorine to selectively reduce the etching rate of silicon.
  • fluorine or carbon tetrafluoride or chlorine to chlorine trifluoride enables selective control of the amount of undercutting achieved during the silicon etching process.
  • a particular example of such control, utilizing chlorine as the additive gas, is illustrated by Fig. 5.
  • a polysilicon layer 60 to be etched is shown overlying a layer 62 made, for example, of silicon dioxide.
  • the thickness of the layer 60 is designated b.
  • a patterned masking layer 64 made, for example, of a resist material.
  • the maximum lateral etch dimension in the layer 60 is designated a. In the maximum undercutting case, the etching process is completely isotropic and a equals b.
  • FIG. 7 A cross-sectional schematic representation of a portion of such a device is shown in Fig. 7.
  • Fig. 7 includes a silicon substrate 70 and a silicon dioxide region 72. Portions of the region 72 envelop a doped polysilicon layer 74 designated the poly 1 layer. An undoped polysilicon layer 76 (poly 2) is disposed on top of the oxide region 72. A patterned masking layer 78 made also, for example, of silicon dioxide is formed by standard techniques on top of the poly 2 layer 76.
  • the oxide layer 72 is initially patterned in a standard etching step wherein the oxide layer 72 is typically undercut relative to the right-hand vertical edge of the poly 1 layer 74.
  • the extent of the undercut approximated 200 nanometers (2000 Angstrom units).
  • a so-called filament of polysilicon material is formed beneath the poly 1 layer 74.
  • the polysilicon filament is designated by reference numeral 80. Unless the filament 80 is removed during subsequent processing, device failures arising therefrom can result, as is well known in the art.
  • the pattern to be formed in the poly 2 layer 76 of Fig. 7 is defined by masking layer 78.
  • Anisotropic etching of the layer 76 is then carried. As a result of such etching, the stippled portion 82 of the layer 76 between dashed lines 83 and 84 is removed. Such anisotropic etching does not, however, remove the polysilicon filament 80.
  • the filament 80 is removed in an isotropic plasma-assisted etching step of the type described herein utilizing a fluorine-contained gaseous compound.
  • Such an etching step is effective to remove the polysilicon filament 80.
  • the opening previously formed in the poly 2 layer 76 and defined by the vertical dashed lines 83, 84 is also slightly enlarged laterally).
  • the portion of the oxide layer 72 underlying the stippled region 82 is relatively unaffected during etching of the polysilicon filament 80. For example, if the lateral extent of the filament 80 to be etched is 200 nanometers (2000 Angstrom units), the specified portion of the layer 72 will be thinned by only about 4 nanometers (40 Angstrom units) units.
  • Applicants' etching processes described herein give a relatively high etch rate and a relatively high uniformity of etch rate across each workpiece as well as from workpiece to workpiece. In practice, such variations in etch rate have been determined not to exceed about 5 percent.
  • the processes described herein do not exhibit any proximity effects.
  • the proximity effect is the variation in the lateral extent of undercutting during isotropic etching as a function of the spacing between masking elements. More generally, the edge profile, the etch rate and the selectivity of each of these processes have been determined to be virtually independent of the specific pattern geometry, feature size and masking material involved in the etching operation. Also, significantly, the processes described herein are carried out at relatively low power levels and with a high differential etch rate relative to materials such as silicon dioxide.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)

Claims (7)

1. Mikrominiaturbauelement - Herstellungsverfahren, das wenigstens einen Verfahrensschritt einschließt, bei dem eine Silicium-Fläche des Bauelementes gegenüber wenigstens einer anderen Fläche des Bauelementes geätzt wird, und zwar in einem Plasma, das in einer gasförmigen Umgebung in einer Trockenätzapparatur erzeugt wird, wobei die gasförmige Umgebung eine fluorhaltige gasförmige Verbindung umfaßt, gekennzeichnet durch vorzugsweises Ätzen von Silicium gegenüber Materialien der wenigstens einen anderen Fläche durch Bereitstellen der fluorhaltigen gasförmigen Verbindung, die siliciumätzende Fluor-Spezies und Reaktionsprodukte liefert, die die anderen Flächen des Bauelementes in keinem wesentlichen Ausmaß gegenüber der Ätzung der Siliciumfläche ätzen, wobei die fluorhaltige gasförmige Verbindung wenigstens eine der Verbindungen Chlortrifluorid, Bromtrifluorid und Jodtrifluorid unfaßt.
2. Verfahren nach Anspruch 1, gekennzeichnet durch Einbringen eines zusätzlichen Bestandteils in die gasförmige Umgebung zusäzlich zu der fluorhaltigen Verbindung, der zur Steuerung des Ausmaßes einer seitlichen Hinterschneidung, während die Siliciumfläche isotrop geätzt wird, vorgesehen ist.
3. Verfahren nach Anspruch 1 oder 2, gekennzeichnet durch Einbringen eines aus einem Inertgas, Chlor und Fluor ausgewählten zusätzlichen Bestandteils in die gasförmige Umgebung zusätzlich zu der fluorhaltigen gasförmigen Verbindung.
4. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß die gasförmige Umgebung die fluorhaltige gasförmige Verbindung und Chlor enthält und die Ätzung der Siliciumfläche gesteuert wird, um isotrop zu sein, wobei das maximale Ausmaß einer seitlichen Hinterschneidung mit zunehmendem Volumprozentbetrag des Chlorbestahdteils abnimmt.
5. Verfahren nach einem der vorstehenden Ansprüche 1 bis 4, gekennzeichnet durch Aufrechthalten in der Trockenätzapparatur eines Gasdruckes von annähernd 2, 7 bis 667 Mikrobar (2 bis 500 Millitorr) und einer Leistungsdichte von 0,01 bis 1 Watt pro cm2 an der zu ätzenden Fläche des Bauelementes.
6. Verfahren nach Anspruch 5, dadurch gekennzeichnet, daß das zu ätzende Bauelement auf der angesteuerten Kathodenelektrode einer mehrflächigen plasmaunterstüzten Ätzapparatur befestigt wird, die gasförmige Umgebung Chlortrifluorid umfaßt, ein Druck von 67 Mikrobar (50 Millitorr) in der Apparatur erzeugt wird und eine Leistungsdichte von 0,04 Watt pro cm2 an der zu ätzenden Fläche des Bauelementes erzeugt wird.
7. Verfahren nach einem der vorstehenden Ansprüche 1 bis 6, dadurch gekennzeichnet, daß die Siliciumfläche des Bauelementes eine gemusterte Maskierschicht hierauf trägt, daß das Bauelement auf einer Kathodenelektrode der Apparatur befestigt wird und daß das Ätzen der Siliciumfläche gesteuert wird, um vollständig isotrop zu sein.
EP81901056A 1980-04-07 1981-03-20 Herstellung von mikrominiaturanordnungen unter verwendung der plasmaätzung von silizium mit fluorhaltigen gasverbindungen Expired EP0049272B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/138,083 US4310380A (en) 1980-04-07 1980-04-07 Plasma etching of silicon
US138083 1980-04-07

Publications (3)

Publication Number Publication Date
EP0049272A1 EP0049272A1 (de) 1982-04-14
EP0049272A4 EP0049272A4 (de) 1984-06-13
EP0049272B1 true EP0049272B1 (de) 1986-07-02

Family

ID=22480348

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81901056A Expired EP0049272B1 (de) 1980-04-07 1981-03-20 Herstellung von mikrominiaturanordnungen unter verwendung der plasmaätzung von silizium mit fluorhaltigen gasverbindungen

Country Status (5)

Country Link
US (1) US4310380A (de)
EP (1) EP0049272B1 (de)
JP (2) JPS57500399A (de)
CA (1) CA1160761A (de)
WO (1) WO1981002947A1 (de)

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426246A (en) * 1982-07-26 1984-01-17 Bell Telephone Laboratories, Incorporated Plasma pretreatment with BCl3 to remove passivation formed by fluorine-etch
US4498953A (en) * 1983-07-27 1985-02-12 At&T Bell Laboratories Etching techniques
US4629635A (en) * 1984-03-16 1986-12-16 Genus, Inc. Process for depositing a low resistivity tungsten silicon composite film on a substrate
US4851295A (en) * 1984-03-16 1989-07-25 Genus, Inc. Low resistivity tungsten silicon composite film
US4778562A (en) * 1984-08-13 1988-10-18 General Motors Corporation Reactive ion etching of tin oxide films using neutral reactant gas containing hydrogen
US4544444A (en) * 1984-08-15 1985-10-01 General Motors Corporation Reactive ion etching of tin oxide films using silicon tetrachloride reactant gas
US4654112A (en) * 1984-09-26 1987-03-31 Texas Instruments Incorporated Oxide etch
US4615764A (en) * 1984-11-05 1986-10-07 Allied Corporation SF6/nitriding gas/oxidizer plasma etch system
US4582581A (en) * 1985-05-09 1986-04-15 Allied Corporation Boron trifluoride system for plasma etching of silicon dioxide
US4796562A (en) * 1985-12-03 1989-01-10 Varian Associates, Inc. Rapid thermal cvd apparatus
US4709655A (en) * 1985-12-03 1987-12-01 Varian Associates, Inc. Chemical vapor deposition apparatus
US6087267A (en) * 1986-03-04 2000-07-11 Motorola, Inc. Process for forming an integrated circuit
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
JP2669460B2 (ja) * 1986-10-29 1997-10-27 株式会社日立製作所 エツチング方法
US4787957A (en) * 1987-09-25 1988-11-29 Air Products And Chemicals, Inc. Desmear and etchback using NF3 /O2 gas mixtures
GB2214870B (en) * 1988-02-20 1991-09-11 Stc Plc Plasma etching process
US4998979A (en) * 1988-06-06 1991-03-12 Canon Kabushiki Kaisha Method for washing deposition film-forming device
EP0414372A3 (en) * 1989-07-21 1991-04-24 Sony Corporation Dry etching methods
JP3140068B2 (ja) * 1991-01-31 2001-03-05 東京エレクトロン株式会社 クリーニング方法
US5304282A (en) * 1991-04-17 1994-04-19 Flamm Daniel L Processes depending on plasma discharges sustained in a helical resonator
US5223083A (en) * 1992-01-23 1993-06-29 Micron Technology, Inc. Process for etching a semiconductor device using an improved protective etching mask
US5302239A (en) * 1992-05-15 1994-04-12 Micron Technology, Inc. Method of making atomically sharp tips useful in scanning probe microscopes
US5302238A (en) * 1992-05-15 1994-04-12 Micron Technology, Inc. Plasma dry etch to produce atomically sharp asperities useful as cold cathodes
US5753130A (en) 1992-05-15 1998-05-19 Micron Technology, Inc. Method for forming a substantially uniform array of sharp tips
US5378648A (en) * 1992-07-15 1995-01-03 Micron Technology, Inc. Situ stringer removal during polysilicon capacitor cell plate delineation
JP2650178B2 (ja) * 1992-12-05 1997-09-03 ヤマハ株式会社 ドライエッチング方法及び装置
US5380370A (en) * 1993-04-30 1995-01-10 Tokyo Electron Limited Method of cleaning reaction tube
JP3024449B2 (ja) * 1993-07-24 2000-03-21 ヤマハ株式会社 縦型熱処理炉及び熱処理方法
JP3370806B2 (ja) 1994-11-25 2003-01-27 株式会社半導体エネルギー研究所 Ｍｉｓ型半導体装置の作製方法
JP3512496B2 (ja) * 1994-11-25 2004-03-29 株式会社半導体エネルギー研究所 Ｓｏｉ型半導体集積回路の作製方法
US5757456A (en) * 1995-03-10 1998-05-26 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating involving peeling circuits from one substrate and mounting on other
JP3579492B2 (ja) * 1995-03-16 2004-10-20 株式会社半導体エネルギー研究所 表示装置の作製方法
US6849471B2 (en) * 2003-03-28 2005-02-01 Reflectivity, Inc. Barrier layers for microelectromechanical systems
US6969635B2 (en) * 2000-12-07 2005-11-29 Reflectivity, Inc. Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
US6077451A (en) * 1996-03-28 2000-06-20 Kabushiki Kaisha Toshiba Method and apparatus for etching of silicon materials
AU6037698A (en) 1997-01-22 1998-08-07 California Institute Of Technology Gas phase silicon etching with bromine trifluoride
US6165375A (en) * 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
WO1999034428A1 (en) * 1997-12-31 1999-07-08 Alliedsignal Inc. Method of etching and cleaning using interhalogen compounds
US6699794B1 (en) * 1998-03-09 2004-03-02 Siemens Aktiengesellschaft Self aligned buried plate
US6067999A (en) * 1998-04-23 2000-05-30 International Business Machines Corporation Method for deposition tool cleaning
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6107206A (en) * 1998-09-14 2000-08-22 Taiwan Semiconductor Manufacturing Company Method for etching shallow trenches in a semiconductor body
DE19843984B4 (de) * 1998-09-25 2013-10-24 Robert Bosch Gmbh Verfahren zur Herstellung von Strahlungssensoren
DE19847455A1 (de) * 1998-10-15 2000-04-27 Bosch Gmbh Robert Verfahren zur Bearbeitung von Silizium mittels Ätzprozessen
JP4689841B2 (ja) * 1999-03-04 2011-05-25 サーフィス テクノロジー システムズ ピーエルシー 三フッ化塩素ガス生成装置
US6511859B1 (en) 1999-03-12 2003-01-28 California Institute Of Technology IC-compatible parylene MEMS technology and its application in integrated sensors
US6451642B1 (en) * 1999-07-14 2002-09-17 Texas Instruments Incorporated Method to implant NMOS polycrystalline silicon in embedded FLASH memory applications
US6290864B1 (en) 1999-10-26 2001-09-18 Reflectivity, Inc. Fluoride gas etching of silicon with improved selectivity
US6949202B1 (en) 1999-10-26 2005-09-27 Reflectivity, Inc Apparatus and method for flow of process gas in an ultra-clean environment
US6942811B2 (en) * 1999-10-26 2005-09-13 Reflectivity, Inc Method for achieving improved selectivity in an etching process
US7041224B2 (en) * 1999-10-26 2006-05-09 Reflectivity, Inc. Method for vapor phase etching of silicon
US6960305B2 (en) * 1999-10-26 2005-11-01 Reflectivity, Inc Methods for forming and releasing microelectromechanical structures
US6221784B1 (en) * 1999-11-29 2001-04-24 Applied Materials Inc. Method and apparatus for sequentially etching a wafer using anisotropic and isotropic etching
US6391790B1 (en) 2000-05-22 2002-05-21 Applied Materials, Inc. Method and apparatus for etching photomasks
US7115523B2 (en) * 2000-05-22 2006-10-03 Applied Materials, Inc. Method and apparatus for etching photomasks
US7019376B2 (en) * 2000-08-11 2006-03-28 Reflectivity, Inc Micromirror array device with a small pitch size
US6581612B1 (en) * 2001-04-17 2003-06-24 Applied Materials Inc. Chamber cleaning with fluorides of iodine
US6800210B2 (en) * 2001-05-22 2004-10-05 Reflectivity, Inc. Method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants
US7183201B2 (en) * 2001-07-23 2007-02-27 Applied Materials, Inc. Selective etching of organosilicate films over silicon oxide stop etch layers
US7189332B2 (en) 2001-09-17 2007-03-13 Texas Instruments Incorporated Apparatus and method for detecting an endpoint in a vapor phase etch
US20030073302A1 (en) * 2001-10-12 2003-04-17 Reflectivity, Inc., A California Corporation Methods for formation of air gap interconnects
US7027200B2 (en) * 2002-03-22 2006-04-11 Reflectivity, Inc Etching method used in fabrications of microstructures
US6965468B2 (en) * 2003-07-03 2005-11-15 Reflectivity, Inc Micromirror array having reduced gap between adjacent micromirrors of the micromirror array
KR20040012451A (ko) * 2002-05-14 2004-02-11 어플라이드 머티어리얼스, 인코포레이티드 포토리소그래픽 레티클을 에칭하는 방법
US7067439B2 (en) * 2002-06-14 2006-06-27 Applied Materials, Inc. ALD metal oxide deposition process using direct oxidation
US6803309B2 (en) * 2002-07-03 2004-10-12 Taiwan Semiconductor Manufacturing Co., Ltd Method for depositing an adhesion/barrier layer to improve adhesion and contact resistance
CA2498320A1 (en) 2002-09-20 2004-04-01 Integrated Dna Technologies, Inc. Anthraquinone quencher dyes, their methods of preparation and use
US6913942B2 (en) 2003-03-28 2005-07-05 Reflectvity, Inc Sacrificial layers for use in fabrications of microelectromechanical devices
US6980347B2 (en) * 2003-07-03 2005-12-27 Reflectivity, Inc Micromirror having reduced space between hinge and mirror plate of the micromirror
US7645704B2 (en) * 2003-09-17 2010-01-12 Texas Instruments Incorporated Methods and apparatus of etch process control in fabrications of microstructures
JP4094539B2 (ja) * 2003-12-12 2008-06-04 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
JP4339102B2 (ja) * 2003-12-12 2009-10-07 株式会社半導体エネルギー研究所 表示装置の作製方法
US7091081B2 (en) * 2004-05-21 2006-08-15 International Business Machines Corporation Method for patterning a semiconductor region
US8119210B2 (en) * 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US20060105114A1 (en) * 2004-11-16 2006-05-18 White John M Multi-layer high quality gate dielectric for low-temperature poly-silicon TFTs
US8293430B2 (en) * 2005-01-27 2012-10-23 Applied Materials, Inc. Method for etching a molybdenum layer suitable for photomask fabrication
US7678710B2 (en) * 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7837838B2 (en) * 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7645710B2 (en) * 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US20070259111A1 (en) * 2006-05-05 2007-11-08 Singh Kaushal K Method and apparatus for photo-excitation of chemicals for atomic layer deposition of dielectric film
DE102006039915A1 (de) 2006-08-25 2008-03-20 Deutsches Zentrum für Luft- und Raumfahrt e.V. Halogenhaltige Schichten
US7902018B2 (en) * 2006-09-26 2011-03-08 Applied Materials, Inc. Fluorine plasma treatment of high-k gate stack for defect passivation
JP4799509B2 (ja) * 2007-08-16 2011-10-26 株式会社半導体エネルギー研究所 剥離方法
JP4596287B2 (ja) * 2008-09-19 2010-12-08 カシオ計算機株式会社 シリコンを含む膜のドライエッチング方法
CN103748671A (zh) * 2011-08-25 2014-04-23 大日本网屏制造株式会社 图案形成方法
JP6056136B2 (ja) * 2011-09-07 2017-01-11 セントラル硝子株式会社 ドライエッチング方法
US20180190792A1 (en) * 2017-01-04 2018-07-05 Globalfoundries Inc. Method of forming semiconductor structure and resulting structure
US20220051898A1 (en) * 2018-12-21 2022-02-17 Showa Denko K.K. Etching method using halogen fluoride and method for producing semiconductor
CN111799217B (zh) * 2020-07-17 2024-02-02 上海华虹宏力半导体制造有限公司 存储器字线形貌的控制方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3400066A (en) * 1965-11-15 1968-09-03 Ibm Sputtering processes for depositing thin films of controlled thickness
US3669774A (en) * 1969-11-20 1972-06-13 Rca Corp Low temperature silicon etch
JPS6012779B2 (ja) * 1976-04-28 1985-04-03 株式会社日立製作所 半導体装置の製造方法
JPS54109387A (en) * 1978-02-15 1979-08-27 Hitachi Ltd Etching method
US4208241A (en) * 1978-07-31 1980-06-17 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4226665A (en) * 1978-07-31 1980-10-07 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4211601A (en) * 1978-07-31 1980-07-08 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4190488A (en) * 1978-08-21 1980-02-26 International Business Machines Corporation Etching method using noble gas halides
US4214946A (en) * 1979-02-21 1980-07-29 International Business Machines Corporation Selective reactive ion etching of polysilicon against SiO2 utilizing SF6 -Cl2 -inert gas etchant

Also Published As

Publication number Publication date
JPH0642470B2 (ja) 1994-06-01
JPS57500399A (de) 1982-03-04
CA1160761A (en) 1984-01-17
WO1981002947A1 (en) 1981-10-15
US4310380A (en) 1982-01-12
JPH03114226A (ja) 1991-05-15
EP0049272A1 (de) 1982-04-14
EP0049272A4 (de) 1984-06-13

Similar Documents

Publication Publication Date Title
EP0049272B1 (de) Herstellung von mikrominiaturanordnungen unter verwendung der plasmaätzung von silizium mit fluorhaltigen gasverbindungen
US4383885A (en) Reactive sputter etching of polysilicon utilizing a chlorine etch gas
EP0167136B1 (de) Selektives anisotropisches reaktives Ionenätzverfahren für zusammengesetzte Strukturen aus Polysiliziden
US6461976B1 (en) Anisotropic etch method
US5256245A (en) Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device
US5310454A (en) Dry etching method
US6670278B2 (en) Method of plasma etching of silicon carbide
US6489248B2 (en) Method and apparatus for etch passivating and etching a substrate
US6716758B1 (en) Aspect ratio controlled etch selectivity using time modulated DC bias voltage
US4472237A (en) Reactive ion etching of tantalum and silicon
US6008139A (en) Method of etching polycide structures
US4264409A (en) Contamination-free selective reactive ion etching or polycrystalline silicon against silicon dioxide
KR20020027520A (ko) 에칭 공정용 측벽 폴리머 형성 가스 첨가제
US5453156A (en) Anisotropic polysilicon plasma etch using fluorine gases
WO2001045152A1 (en) Plasma processing of tungsten using a gas mixture comprising a fluorinated gas and oxygen
EP1774542A2 (de) Plasmaätzverfahren für zweischichtigen fotolack
US5880033A (en) Method for etching metal silicide with high selectivity to polysilicon
US5849641A (en) Methods and apparatus for etching a conductive layer to improve yield
US5271799A (en) Anisotropic etch method
JPH06338479A (ja) エッチング方法
US4937643A (en) Devices having tantalum silicide structures
CA1148895A (en) Reactive sputter etching of silicon
GB2098931A (en) Method of plasma etching microminiature devices
US5759922A (en) Control of etch profiles during extended overetch
JPH031825B2 (de)

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19811030

AK Designated contracting states

Designated state(s): DE FR GB NL

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB NL

REF Corresponds to:

Ref document number: 3174887

Country of ref document: DE

Date of ref document: 19860807

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20000223

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20000225

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20000316

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20000331

Year of fee payment: 20

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20010319

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20010320

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Effective date: 20010319

NLV7 Nl: ceased due to reaching the maximum lifetime of a patent

Effective date: 20010320