EP0036494B1 - Integrierte MOS-Halbleiterschaltung - Google Patents

Integrierte MOS-Halbleiterschaltung Download PDF

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Publication number
EP0036494B1
EP0036494B1 EP81101324A EP81101324A EP0036494B1 EP 0036494 B1 EP0036494 B1 EP 0036494B1 EP 81101324 A EP81101324 A EP 81101324A EP 81101324 A EP81101324 A EP 81101324A EP 0036494 B1 EP0036494 B1 EP 0036494B1
Authority
EP
European Patent Office
Prior art keywords
voltage
circuit component
substrate bias
digital circuit
pulse generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP81101324A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0036494A2 (de
EP0036494A3 (en
Inventor
Kurt Dr. Hoffmann
Dieter Dipl.-Ing. Kantz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0036494A2 publication Critical patent/EP0036494A2/de
Publication of EP0036494A3 publication Critical patent/EP0036494A3/de
Application granted granted Critical
Publication of EP0036494B1 publication Critical patent/EP0036494B1/de
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • the invention relates to an integrated MOS semiconductor circuit with a - z. B. designed as a dynamic memory - digital and provided with a clock circuit part, with a trained as a clocked substrate bias generator further circuit part and with two of the supply voltage supplied by a DC voltage supply leads.
  • an oscillator which is different from the clock generator for the digital circuit part is used for clocking the substrate bias generator and this oscillator is also used to control a circuit part which is designed as a voltage multiplier and which supplies an excessive operating voltage to the digital circuit part compared to the supply voltage at the supply connections it is provided that the output of the voltage multiplier supplying the excessive operating voltage to the digital circuit part is connected to the supply connection carrying the reference potential via a limiter circuit made of MOS transistors, and that, finally, the output of the substrate bias generator supplying the substrate bias voltage is mediated in a manner known per se a converter acting as a comparator to an input used to activate the clock provided for the digital circuit part the same and the resulting control of the activation of this clock generator is designed such that activation of the clock generator and thus of the digital circuit part is only possible when the full substrate bias is reached.
  • the circuit according to the invention is thus designed so that an additional operating potential V z arises due to the voltage multiplier, which is preferably used to apply MOS capacitors, that is to say the said varactor capacitors, which, for. B. are used as storage capacitors.
  • the potential V z can also form the supply potential required to operate the digital circuit part. It can be advantageous if the substrate bias V BB and / or the voltage V z supplied by the voltage multiplier SV is stabilized by a control circuit.
  • a clocked substrate bias generator SE in which an oscillator O is provided as a clock generator, is described in DE-OS 28 12 378.
  • the circuit shown in FIG. 1 of DE-OS 28 12 378 for a substrate bias generator can be used directly.
  • the clock generator TG which is responsible for the digital circuit part ES, is in turn supplied with rectangular pulses via an input TE, which come from an external pulse source. It has the task of deriving the clock signals required for operating the digital circuit part ES from the primary pulses obtained via the input TE.
  • the supply potentials V cc and G ND are provided both for the clock generator TG and for the substrate bias generator SE, which incidentally also applies to a converter U provided between the two circuit parts SE and TG.
  • This converter or converter U is also supplied by the two operating potentials V cc and G ND . It has the task of emitting an activation signal to the clock generator TG as soon as the substrate bias voltage V BB supplied by the substrate bias generator SE is fully built up. It is therefore the purpose of the voltage supplied by the converter U to start the clock generator TG only when the substrate bias voltage V BB has reached its desired value.
  • the converter U thus acts as a comparator and can e.g. B. be given by a differential amplifier. The presence of the converter U prevents the digital circuit part ES (for example a semiconductor memory) from being put into operation before the substrate bias is built up and is damaged by the short-circuit current which then occurs.
  • a clocked voltage doubler SV is described in DE-OS 2811 418.
  • the circuit principle described there can also be used to implement DC voltage multipliers that work with any integer ratio between their input voltage and output voltage.
  • the oscillator provided there can easily be replaced by the clock oscillator 0 provided to supply the substrate bias generator SE.
  • the task of the voltage multiplier SV is, as already explained, to generate an increased operating DC voltage required for the operation of the digital circuit part ES, as it is e.g. B. needed to charge storage capacity.
  • the output of the voltage multiplier SV is connected to the reference potential G ND via a limiter circuit BS. It is also connected directly to a further supply input of the digital circuit part ES and carries the increased additional operating potential V z required for the operation of selected circuit parts (e.g. for charging storage capacitors).
  • the substrate bias V BB which is provided by the substrate bias generator SE, on the other hand, benefits all the circuit parts provided in the semiconductor die.
  • the supply potential V cc is made available to the circuit parts O, SE, U, TG and SV. It also serves as the main operating potential for the digital circuit part ES. The same applies to the reference potential G ND .
  • the limiter circuit BS can, for. B. consist of two or more series-connected MOS field effect transistors t, which are connected by connecting their gates with their drains as resistors. The source of the last of these transistors t is at the reference potential G ND .
  • the number of transistors t in series depends on the number of field-effect transistors connected in series in the voltage multiplication circuit SV with respect to the two operating potentials V CC and G ND .
  • the transistors t can also be connected as diodes in the reverse direction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
EP81101324A 1980-03-11 1981-02-24 Integrierte MOS-Halbleiterschaltung Expired EP0036494B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3009303 1980-03-11
DE19803009303 DE3009303A1 (de) 1980-03-11 1980-03-11 Monolithisch integrierte digitale halbleiterschaltung

Publications (3)

Publication Number Publication Date
EP0036494A2 EP0036494A2 (de) 1981-09-30
EP0036494A3 EP0036494A3 (en) 1981-11-25
EP0036494B1 true EP0036494B1 (de) 1984-07-25

Family

ID=6096869

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81101324A Expired EP0036494B1 (de) 1980-03-11 1981-02-24 Integrierte MOS-Halbleiterschaltung

Country Status (4)

Country Link
US (1) US4454431A (enrdf_load_stackoverflow)
EP (1) EP0036494B1 (enrdf_load_stackoverflow)
JP (1) JPS56142663A (enrdf_load_stackoverflow)
DE (2) DE3009303A1 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6177421A (ja) * 1984-08-21 1986-04-21 ラテイス・セミコンダクター・コーポレーシヨン Ｃｍｏｓデバイスのラツチアツプを防止する回路と方法
JPH0618249B2 (ja) * 1984-10-17 1994-03-09 富士通株式会社 半導体集積回路
ATE67617T1 (de) * 1985-08-26 1991-10-15 Siemens Ag Integrierte schaltung in komplementaerer schaltungstechnik mit einem substratvorspannungs- generator.
US4794278A (en) * 1987-12-30 1988-12-27 Intel Corporation Stable substrate bias generator for MOS circuits
KR950002015B1 (ko) * 1991-12-23 1995-03-08 삼성전자주식회사 하나의 오실레이터에 의해 동작되는 정전원 발생회로
CN105024674B (zh) * 2015-03-13 2018-06-12 苏州迈瑞微电子有限公司 一种异步复位装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794862A (en) * 1972-04-05 1974-02-26 Rockwell International Corp Substrate bias circuit
US3838357A (en) * 1973-10-25 1974-09-24 Honeywell Inf Systems Apparatus for using start-up of a crystal oscillator to synchronize power turn-on in various portions of a system
IT1073440B (it) * 1975-09-22 1985-04-17 Seiko Instr & Electronics Circuito elevatore di tensione realizzato in mos-fet
US4030084A (en) * 1975-11-28 1977-06-14 Honeywell Information Systems, Inc. Substrate bias voltage generated from refresh oscillator
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation
DE2812378C2 (de) * 1978-03-21 1982-04-29 Siemens AG, 1000 Berlin und 8000 München Substratvorspannungsgenerator für integrierte MIS-Schaltkreise
JPS5525220A (en) * 1978-08-11 1980-02-22 Oki Electric Ind Co Ltd Substrate bias generation circuit
US4229667A (en) * 1978-08-23 1980-10-21 Rockwell International Corporation Voltage boosting substrate bias generator
JPS5951750B2 (ja) * 1978-11-24 1984-12-15 富士通株式会社 基板バイアス発生回路
US4296340A (en) * 1979-08-27 1981-10-20 Intel Corporation Initializing circuit for MOS integrated circuits

Also Published As

Publication number Publication date
EP0036494A2 (de) 1981-09-30
DE3009303A1 (de) 1981-09-24
EP0036494A3 (en) 1981-11-25
DE3164950D1 (de) 1984-08-30
JPS56142663A (en) 1981-11-07
JPH0213821B2 (enrdf_load_stackoverflow) 1990-04-05
US4454431A (en) 1984-06-12

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