EP0036494B1 - Integrated mos semiconductor circuit - Google Patents
Integrated mos semiconductor circuit Download PDFInfo
- Publication number
- EP0036494B1 EP0036494B1 EP81101324A EP81101324A EP0036494B1 EP 0036494 B1 EP0036494 B1 EP 0036494B1 EP 81101324 A EP81101324 A EP 81101324A EP 81101324 A EP81101324 A EP 81101324A EP 0036494 B1 EP0036494 B1 EP 0036494B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- circuit component
- substrate bias
- digital circuit
- pulse generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/205—Substrate bias-voltage generators
Definitions
- the invention relates to an integrated MOS semiconductor circuit with a - z. B. designed as a dynamic memory - digital and provided with a clock circuit part, with a trained as a clocked substrate bias generator further circuit part and with two of the supply voltage supplied by a DC voltage supply leads.
- an oscillator which is different from the clock generator for the digital circuit part is used for clocking the substrate bias generator and this oscillator is also used to control a circuit part which is designed as a voltage multiplier and which supplies an excessive operating voltage to the digital circuit part compared to the supply voltage at the supply connections it is provided that the output of the voltage multiplier supplying the excessive operating voltage to the digital circuit part is connected to the supply connection carrying the reference potential via a limiter circuit made of MOS transistors, and that, finally, the output of the substrate bias generator supplying the substrate bias voltage is mediated in a manner known per se a converter acting as a comparator to an input used to activate the clock provided for the digital circuit part the same and the resulting control of the activation of this clock generator is designed such that activation of the clock generator and thus of the digital circuit part is only possible when the full substrate bias is reached.
- the circuit according to the invention is thus designed so that an additional operating potential V z arises due to the voltage multiplier, which is preferably used to apply MOS capacitors, that is to say the said varactor capacitors, which, for. B. are used as storage capacitors.
- the potential V z can also form the supply potential required to operate the digital circuit part. It can be advantageous if the substrate bias V BB and / or the voltage V z supplied by the voltage multiplier SV is stabilized by a control circuit.
- a clocked substrate bias generator SE in which an oscillator O is provided as a clock generator, is described in DE-OS 28 12 378.
- the circuit shown in FIG. 1 of DE-OS 28 12 378 for a substrate bias generator can be used directly.
- the clock generator TG which is responsible for the digital circuit part ES, is in turn supplied with rectangular pulses via an input TE, which come from an external pulse source. It has the task of deriving the clock signals required for operating the digital circuit part ES from the primary pulses obtained via the input TE.
- the supply potentials V cc and G ND are provided both for the clock generator TG and for the substrate bias generator SE, which incidentally also applies to a converter U provided between the two circuit parts SE and TG.
- This converter or converter U is also supplied by the two operating potentials V cc and G ND . It has the task of emitting an activation signal to the clock generator TG as soon as the substrate bias voltage V BB supplied by the substrate bias generator SE is fully built up. It is therefore the purpose of the voltage supplied by the converter U to start the clock generator TG only when the substrate bias voltage V BB has reached its desired value.
- the converter U thus acts as a comparator and can e.g. B. be given by a differential amplifier. The presence of the converter U prevents the digital circuit part ES (for example a semiconductor memory) from being put into operation before the substrate bias is built up and is damaged by the short-circuit current which then occurs.
- a clocked voltage doubler SV is described in DE-OS 2811 418.
- the circuit principle described there can also be used to implement DC voltage multipliers that work with any integer ratio between their input voltage and output voltage.
- the oscillator provided there can easily be replaced by the clock oscillator 0 provided to supply the substrate bias generator SE.
- the task of the voltage multiplier SV is, as already explained, to generate an increased operating DC voltage required for the operation of the digital circuit part ES, as it is e.g. B. needed to charge storage capacity.
- the output of the voltage multiplier SV is connected to the reference potential G ND via a limiter circuit BS. It is also connected directly to a further supply input of the digital circuit part ES and carries the increased additional operating potential V z required for the operation of selected circuit parts (e.g. for charging storage capacitors).
- the substrate bias V BB which is provided by the substrate bias generator SE, on the other hand, benefits all the circuit parts provided in the semiconductor die.
- the supply potential V cc is made available to the circuit parts O, SE, U, TG and SV. It also serves as the main operating potential for the digital circuit part ES. The same applies to the reference potential G ND .
- the limiter circuit BS can, for. B. consist of two or more series-connected MOS field effect transistors t, which are connected by connecting their gates with their drains as resistors. The source of the last of these transistors t is at the reference potential G ND .
- the number of transistors t in series depends on the number of field-effect transistors connected in series in the voltage multiplication circuit SV with respect to the two operating potentials V CC and G ND .
- the transistors t can also be connected as diodes in the reverse direction.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
Die Erfindung betrifft eine integrierte MOS-Halbleiterschaltung mit einem - z. B. als dynamischer Speicher ausgebildeten - digitalen und mit einem Taktgeber versehenen Schaltungsteil, mit einem als getakteter Substratvorspannungsgenerator ausgebildeten weiteren Schaltungsteil sowie mit zwei die von einer Gleichspannungsquelle gelieferte Versorgungsspannung führenden Versorgungsanschlüssen.The invention relates to an integrated MOS semiconductor circuit with a - z. B. designed as a dynamic memory - digital and provided with a clock circuit part, with a trained as a clocked substrate bias generator further circuit part and with two of the supply voltage supplied by a DC voltage supply leads.
Als einschlägiger Stand der Technik kann hier die französische Patentschrift 2 333 296 (vgl. Fig. 3) genannt werden. Bei der dort beschriebenen Ausgestaltung dient zur Taktsteuerung der Substratvorspannungsgenerators ein Oszillator, der die Aufgabe hat, als Taktgeber für die als Speicher ausgebildete Digitalschaltung zu arbeiten. Es wird also auch bei der bekannten Halbleiterschaltung der Tatsache Rechnung getragen, daß bei digitalen Halbleiterschaltungen häufig nicht nur zwei Betriebspotentiale sondern noch ein weiteres Betriebspotential erforderlich ist, das zur Erzeugung einer zwischen der Rückseite des Halbleiterplättchens und den Schaltungsteilen an der Vorderseite desselben liegenden Substratvorspannung gebraucht wird.French patent specification 2,333,296 (cf. FIG. 3) can be mentioned here as the relevant prior art. In the embodiment described there, an oscillator is used for clock control of the substrate bias generator, which has the task of working as a clock generator for the digital circuit designed as a memory. It is also taken into account in the known semiconductor circuit that digital semiconductor circuits often require not only two operating potentials but also a further operating potential which is used to generate a substrate bias lying between the back of the semiconductor die and the circuit parts on the front of the same .
Jedoch ist in diesem Zusammenhange festzustellen, daß im Interesse der Vermeidung einer Zerstörung der integrierten Halbleiterschaltung der Taktgeber erst nach dem Aufbau der Substratvorspannung VBB eingeschaltet werden sollte, was bei der bekannten Schaltung offensichtlich nicht der Fall ist. Ferner ist man bei vielen Digitalschaltungen, z. B. bei dynamischen Speichern, daran interessiert, daß eine die zwischen den beiden Anschlüssen des Halbleiterkörpers liegende Spannungsdifferenz übertreffende Hilfsspannung Vz zur Verfügung steht, insbesondere dann, wenn die Schaltung mit aufzuladenden Varaktorkondensatoren versehen ist. Es ist nun Aufgabe der Erfindung, eine integrierte MOS-Halbleiterschaltung nach der obigen Definition derart auszugestalten, daß den soeben angegeben Gesichtspunkten Rechnung getragen wird.However, it should be noted in this connection that in the interest of avoiding destruction of the integrated semiconductor circuit, the clock should only be switched on after the substrate bias voltage V BB has been built up, which is obviously not the case with the known circuit. Furthermore, many digital circuits, e.g. B. in dynamic memories, interested in the fact that the voltage difference lying between the two connections of the semiconductor body surpassing auxiliary voltage V z is available, in particular when the circuit is provided with varactor capacitors to be charged. It is an object of the invention to design an integrated MOS semiconductor circuit according to the above definition in such a way that the aspects just stated are taken into account.
Erfindungsgemäß ist hierzu vorgesehen, daß zur Taktung des Substratvorspannungsgenerators ein vom Taktgeber für den digitalen Schaltungsteil verschiedener Oszillator verwendet ist und dieser Oszillator gleichzeitig zur Steuerung eines als Spannungsvervielfacher ausgebildeten und eine im Vergleich zu der an den Versorgungsanschlüssen liegenden Versorgungsspannung überhöhte Betriebsspannung an den digitalen Schaltungsteil liefernden Schaltungsteils vorgesehen ist, daß dabei der die überhöhte Betriebsspannung an den digitalen Schaltungsteil liefernde Ausgang des Spannungsvervielfachers über eine Begrenzerschaltung aus MOS-Transistoren an den das Bezugspotential führenden Versorgungsanschluß gelegt ist, und daß schließlich in an sich bekannter Weise der die Substratvorspannung liefernde Ausgang des Substratvorspannungsgenerators unter Vermittlung eines als Komparator wirkenden Umformers an einen der Aktivierung des für den digitalen Schaltungsteil vorgesehenen Taktgebers dienenden Eingang desselben gelegt und die hierdurch gegebene Steuerung der Aktivierung dieses Taktgebers derart ausgebildet ist, daß erst mit Erreichung der vollen Substratvorspannung eine Aktivierung des Taktgebers und damit des digitalen Schaltungsteils möglich ist.According to the invention, it is provided that an oscillator which is different from the clock generator for the digital circuit part is used for clocking the substrate bias generator and this oscillator is also used to control a circuit part which is designed as a voltage multiplier and which supplies an excessive operating voltage to the digital circuit part compared to the supply voltage at the supply connections it is provided that the output of the voltage multiplier supplying the excessive operating voltage to the digital circuit part is connected to the supply connection carrying the reference potential via a limiter circuit made of MOS transistors, and that, finally, the output of the substrate bias generator supplying the substrate bias voltage is mediated in a manner known per se a converter acting as a comparator to an input used to activate the clock provided for the digital circuit part the same and the resulting control of the activation of this clock generator is designed such that activation of the clock generator and thus of the digital circuit part is only possible when the full substrate bias is reached.
Die erfindungsgemäße Schaltung ist also so ausgebildet, daß aufgrund des Spannungsvervielfachers ein zusätzliches Betriebspotential Vz entsteht, das vorzugsweise zur Beaufschlagung von MOS-Kondensatoren, also den besagten Varaktorkondensatoren, dient, die z. B. als Speicherkondensatoren eingesetzt sind. Das Potential Vz kann aber auch anstelle von Vcc das zum Betrieb des digitalen Schaltungsteils benötigte Versorgungspotential bilden. Dabei kann vorteilhaft sein, wenn die Substratvorspannung VBB und/oder die vom Spannungsvervielfacher SV gelieferte Spannung Vz durch einen Regelkreis stabilisiert wird.The circuit according to the invention is thus designed so that an additional operating potential V z arises due to the voltage multiplier, which is preferably used to apply MOS capacitors, that is to say the said varactor capacitors, which, for. B. are used as storage capacitors. However, instead of V cc, the potential V z can also form the supply potential required to operate the digital circuit part. It can be advantageous if the substrate bias V BB and / or the voltage V z supplied by the voltage multiplier SV is stabilized by a control circuit.
Eine der Erfindung entsprechende Halbleiterschaltung wird nun anhand des in der Zeichnung dargestellten Blockschaltbilds beschrieben.A semiconductor circuit according to the invention will now be described with reference to the block diagram shown in the drawing.
Die beiden Versorgungsanschlüsse des die Schaltung aufnehmenden Halbleiterplättchens sind mit den Betriebspotentialen Vcc und GND beaufschlagt, die dann den einzelnen Schaltungsteilen in der aus der Zeichnung ersichtlichen Weise zugeführt werden. Als Schaltungsteile sind neben dem digitalen Schaltungsteil ES noch vorgesehen :
- Ein durch die von den beiden Betriebspotentialen Vcc und GND (= Bezugspotential (Masse)) definierten Betriebsspannung beaufschlagter Oszillator O, der insbesondere als RC-Oszillator ausgebildet ist. Er liefert periodische Rechteckimpulse gleicher Amplitude, die zur Steuerung des Substratvorspannungserzeugers SE und des Spannungsvervielfachers SE (z. B. eines Spannungsverdopplers) dient.
- An oscillator O acted upon by the operating voltage defined by the two operating potentials V cc and G ND (= reference potential (ground)), which is designed in particular as an RC oscillator. It supplies periodic square-wave pulses of the same amplitude, which are used to control the substrate bias generator SE and the voltage multiplier SE (e.g. a voltage doubler).
Ein getakteter Substratvorspannungserzeuger SE, bei dem ein Oszillator O als Taktgeber vorgesehen ist, ist in der DE-OS 28 12 378 beschrieben. Die in Fig. 1 der DE-OS 28 12 378 dadargestellte Schaltung für einen Substratvorspannungserzeuger kann unmittelbar angewendet werden.A clocked substrate bias generator SE, in which an oscillator O is provided as a clock generator, is described in DE-OS 28 12 378. The circuit shown in FIG. 1 of DE-OS 28 12 378 for a substrate bias generator can be used directly.
Der für den digitalen Schaltungsteil ES zuständige Taktgeber TG wird seinerseits über einen Eingang TE mit Rechteckimpulsen beaufschlagt, die von einer externen Impulsquelle kommen. Er hat die Aufgabe, die zum Betrieb des digitalen Schaltungsteils ES erforderlichen Taktsignale aus den über den Eingang TE erhaltenen Primärimpulsen abzuleiten. Sowohl für den Taktgeber TG als auch für den Substratvorspannungsgenerator SE sind die Versorgungspotentiale Vcc und GND vorgesehen, was übrigens auch für einen zwischen den beiden Schaltungsteilen SE und TG vorgesehenen Umformer U gilt.The clock generator TG, which is responsible for the digital circuit part ES, is in turn supplied with rectangular pulses via an input TE, which come from an external pulse source. It has the task of deriving the clock signals required for operating the digital circuit part ES from the primary pulses obtained via the input TE. The supply potentials V cc and G ND are provided both for the clock generator TG and for the substrate bias generator SE, which incidentally also applies to a converter U provided between the two circuit parts SE and TG.
Dieser Umformer oder Umwandler U wird ebenfalls durch die beiden Betriebspotentiale Vcc und GND versorgt. Er hat die Aufgabe, an den Taktgeber TG ein Aktivierungssignal abzugeben, sobald die vom Substratvorspannungsgenerator SE gelieferte Substratvorspannung VBB voll aufgebaut ist. Somit ist es Zweck der vom Umwandler U gelieferten Spannung, erst dann den Taktgeber TG in Betrieb zu setzen, wenn die Substratvorspannung VBB ihren Sollwert erreicht hat. Der Umwandler U wirkt somit als Komparator und kann z. B. durch einen Differenzverstärker gegeben sein. Durch die Anwesenheit des Umwandlers U wird vermieden, daß der digitale Schaltungsteil ES (z. B. ein Halbleiterspeicher) vor dem Aufbau der Substratvorspannung in Betrieb gesetzt und durch den dann auftretenden Kurzschlußstrom beschädigt wird.This converter or converter U is also supplied by the two operating potentials V cc and G ND . It has the task of emitting an activation signal to the clock generator TG as soon as the substrate bias voltage V BB supplied by the substrate bias generator SE is fully built up. It is therefore the purpose of the voltage supplied by the converter U to start the clock generator TG only when the substrate bias voltage V BB has reached its desired value. The converter U thus acts as a comparator and can e.g. B. be given by a differential amplifier. The presence of the converter U prevents the digital circuit part ES (for example a semiconductor memory) from being put into operation before the substrate bias is built up and is damaged by the short-circuit current which then occurs.
Ein getakteter Spannungsverdoppler SV ist in der DE-OS 2811 418 beschrieben. Das dort beschriebene Schaltungsprinzip läßt sich auch zur Realisierung von Gleichspannungsvervielfachern verwenden, die mit einem beliebigen ganzzahligen Verhältnis zwischen ihrer Eingangsspannung und Ausgangsspannung arbeiten. Der dort vorgesehene Oszillator kann ohne weiteres durch den zur Versorgung des Substratvorspannungsgenerators SE vorgesehenen Taktoszillator 0 ersetzt werden. Aufgabe des Spannungsvervielfachers SV ist es, wie bereits dargelegt, eine zum Betrieb des digitalen Schaltungsteils ES benötigte erhöhte Betriebsgleichspannung zu erzeugen, wie sie z. B. zum Aufladen von Speicherkapazitäten benötigt wird.A clocked voltage doubler SV is described in DE-OS 2811 418. The circuit principle described there can also be used to implement DC voltage multipliers that work with any integer ratio between their input voltage and output voltage. The oscillator provided there can easily be replaced by the
Der Ausgang des Spannungsvervielfachers SV ist über eine Begrenzerschaltung BS an das Bezugspotential GND gelegt. Er ist außerdem unmittelbar an einen weiteren Versorgungseingang des digitalen Schaltungsteils ES geschaltet und führt das zum Betrieb auserwählter Schaltungsteile (z. B. zum Aufladen von Speicherkondensatoren) benötigte erhöhte zusätzliche Betriebspotential Vz.The output of the voltage multiplier SV is connected to the reference potential G ND via a limiter circuit BS. It is also connected directly to a further supply input of the digital circuit part ES and carries the increased additional operating potential V z required for the operation of selected circuit parts (e.g. for charging storage capacitors).
Die Substratvorspannung VBB, die vom Substratvorspannungsgenerator SE zur Verfügung gestellt wird, kommt hingegen allen im Halbleiterplättchen vorgesehenen Schaltungsteilen zugute. Das Versorgungspotential Vcc ist, wie bereits festgestellt, den Schaltungsteilen O, SE, U, TG und SV zur Verfügung gestellt. Es dient außerdem als Hauptbetriebspotential für den digitalen Schaltungsteil ES. Dasselbe gilt für das Bezugspotential GND.The substrate bias V BB , which is provided by the substrate bias generator SE, on the other hand, benefits all the circuit parts provided in the semiconductor die. As already stated, the supply potential V cc is made available to the circuit parts O, SE, U, TG and SV. It also serves as the main operating potential for the digital circuit part ES. The same applies to the reference potential G ND .
Die Begrenzerschaltung BS kann z. B. aus zwei oder mehreren hintereinandergeschalteten MOS-Feldeffekttransistoren t bestehen, die durch Verbindung ihrer Gates mit ihren Drains als Widerstände geschaltet sind. Die Source des letzten dieser Transistoren t liegt am Bezugspotential GND. Die Anzahl der in Reihe liegenden Transistoren t richtet sich nach der Anzahl der in der Spannungsvervielfachungsschaltung SV bezüglich der beiden Betriebspotentiale Vcc und GND hintereinander geschalteten Feldeffekttransistoren. Die Transistoren t können übrigens auch als in Sperrichtung liegende Dioden geschaltet sein.The limiter circuit BS can, for. B. consist of two or more series-connected MOS field effect transistors t, which are connected by connecting their gates with their drains as resistors. The source of the last of these transistors t is at the reference potential G ND . The number of transistors t in series depends on the number of field-effect transistors connected in series in the voltage multiplication circuit SV with respect to the two operating potentials V CC and G ND . The transistors t can also be connected as diodes in the reverse direction.
Claims (3)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19803009303 DE3009303A1 (en) | 1980-03-11 | 1980-03-11 | MONOLITHICALLY INTEGRATED DIGITAL SEMICONDUCTOR CIRCUIT |
| DE3009303 | 1980-03-11 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0036494A2 EP0036494A2 (en) | 1981-09-30 |
| EP0036494A3 EP0036494A3 (en) | 1981-11-25 |
| EP0036494B1 true EP0036494B1 (en) | 1984-07-25 |
Family
ID=6096869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP81101324A Expired EP0036494B1 (en) | 1980-03-11 | 1981-02-24 | Integrated mos semiconductor circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4454431A (en) |
| EP (1) | EP0036494B1 (en) |
| JP (1) | JPS56142663A (en) |
| DE (2) | DE3009303A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6177421A (en) * | 1984-08-21 | 1986-04-21 | ラテイス・セミコンダクター・コーポレーシヨン | Circuit and method of preventing latch-up of complementary metal oxide semiconductor device |
| JPH0618249B2 (en) * | 1984-10-17 | 1994-03-09 | 富士通株式会社 | Semiconductor integrated circuit |
| DE3681540D1 (en) * | 1985-08-26 | 1991-10-24 | Siemens Ag | INTEGRATED CIRCUIT IN COMPLEMENTARY CIRCUIT TECHNOLOGY WITH A SUBSTRATE PRELOAD GENERATOR. |
| US4794278A (en) * | 1987-12-30 | 1988-12-27 | Intel Corporation | Stable substrate bias generator for MOS circuits |
| KR950002015B1 (en) * | 1991-12-23 | 1995-03-08 | 삼성전자주식회사 | Static source voltage generating circuit operated by an oscillator |
| CN105024674B (en) * | 2015-03-13 | 2018-06-12 | 苏州迈瑞微电子有限公司 | A kind of asynchronous reset |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3794862A (en) * | 1972-04-05 | 1974-02-26 | Rockwell International Corp | Substrate bias circuit |
| US3838357A (en) * | 1973-10-25 | 1974-09-24 | Honeywell Inf Systems | Apparatus for using start-up of a crystal oscillator to synchronize power turn-on in various portions of a system |
| IT1073440B (en) * | 1975-09-22 | 1985-04-17 | Seiko Instr & Electronics | VOLTAGE LIFT CIRCUIT MADE IN MOS-FET |
| US4030084A (en) * | 1975-11-28 | 1977-06-14 | Honeywell Information Systems, Inc. | Substrate bias voltage generated from refresh oscillator |
| JPS53130990A (en) * | 1977-04-20 | 1978-11-15 | Toshiba Corp | Integrated circuit device |
| US4142114A (en) * | 1977-07-18 | 1979-02-27 | Mostek Corporation | Integrated circuit with threshold regulation |
| DE2812378C2 (en) * | 1978-03-21 | 1982-04-29 | Siemens AG, 1000 Berlin und 8000 München | Substrate bias generator for MIS integrated circuits |
| JPS5525220A (en) * | 1978-08-11 | 1980-02-22 | Oki Electric Ind Co Ltd | Substrate bias generation circuit |
| US4229667A (en) * | 1978-08-23 | 1980-10-21 | Rockwell International Corporation | Voltage boosting substrate bias generator |
| JPS5951750B2 (en) * | 1978-11-24 | 1984-12-15 | 富士通株式会社 | Substrate bias generation circuit |
| US4296340A (en) * | 1979-08-27 | 1981-10-20 | Intel Corporation | Initializing circuit for MOS integrated circuits |
-
1980
- 1980-03-11 DE DE19803009303 patent/DE3009303A1/en not_active Withdrawn
-
1981
- 1981-02-24 EP EP81101324A patent/EP0036494B1/en not_active Expired
- 1981-02-24 DE DE8181101324T patent/DE3164950D1/en not_active Expired
- 1981-03-03 US US06/240,197 patent/US4454431A/en not_active Expired - Lifetime
- 1981-03-09 JP JP3372081A patent/JPS56142663A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE3164950D1 (en) | 1984-08-30 |
| US4454431A (en) | 1984-06-12 |
| DE3009303A1 (en) | 1981-09-24 |
| JPS56142663A (en) | 1981-11-07 |
| JPH0213821B2 (en) | 1990-04-05 |
| EP0036494A3 (en) | 1981-11-25 |
| EP0036494A2 (en) | 1981-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE4130191C2 (en) | Constant voltage generator for a semiconductor device with cascaded charging or discharging circuit | |
| DE2541131C2 (en) | Circuit arrangement for keeping the switching delay of FET inverter stages constant in an integrated circuit | |
| DE2359646A1 (en) | INTEGRATED DRIVER CIRCUIT WITH FIELD EFFECT TRANSISTORS | |
| DE3814667A1 (en) | BACK VOLTAGE GENERATOR | |
| DE2359647A1 (en) | CIRCUIT ARRANGEMENT FOR GENERATING A COMPENSATED CONTROL VOLTAGE | |
| EP0010137A1 (en) | Substrate polarisation voltage generator circuit | |
| DE2620187B2 (en) | Monostable multivibrator circuit | |
| DE2130909A1 (en) | Unsaturated logic circuit for TTL and DTL circuits | |
| EP0036494B1 (en) | Integrated mos semiconductor circuit | |
| DE3042323C2 (en) | Resonant circuit | |
| DE69805717T2 (en) | Charge pump voltage generator with self-oscillating control circuit | |
| DE69113414T2 (en) | Integrated constant current supply. | |
| DE4117882A1 (en) | BOOSTER CIRCUIT FOR A SEMICONDUCTOR MEMORY | |
| EP0013686A1 (en) | Latch circuit | |
| DE2627047A1 (en) | SEMI-CONDUCTOR SWITCH | |
| DE2812375C2 (en) | Analog-to-digital converter | |
| DE2130916A1 (en) | Transmission circuit for digital signals | |
| DE2001560A1 (en) | Asymmetrical delay circuit | |
| DE2262719A1 (en) | PULSE GENERATOR CIRCUIT | |
| EP0459313B1 (en) | Comparator circuit for an integrator | |
| DE1809207B2 (en) | Astable high frequency integrated circuit multivibrators - consist of two AND gates with two other elements to give good performance | |
| DE1299715B (en) | Circuit arrangement for an electronic frequency divider with an integration circuit | |
| DE4443606C1 (en) | Resetting signal circuit for vehicle anti-theft device | |
| EP0025104A1 (en) | Circuit arrangement for generating a resetting signal at the application of constant supply voltage and of two clock voltages | |
| DE2632199A1 (en) | Integratable voltage multiplier with cascaded FET stages - each providing supply for next stage and each having two cross-coupled FETs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
| AK | Designated contracting states |
Designated state(s): DE FR GB IT |
|
| AK | Designated contracting states |
Designated state(s): DE FR GB IT |
|
| 17P | Request for examination filed |
Effective date: 19811028 |
|
| ITF | It: translation for a ep patent filed |
Owner name: STUDIO JAUMANN |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Designated state(s): DE FR GB IT |
|
| REF | Corresponds to: |
Ref document number: 3164950 Country of ref document: DE Date of ref document: 19840830 |
|
| ET | Fr: translation filed | ||
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed | ||
| ITTA | It: last paid annual fee | ||
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20000211 Year of fee payment: 20 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20000229 Year of fee payment: 20 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20000426 Year of fee payment: 20 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20010223 |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: PE20 Effective date: 20010223 |