EP0036494A3 - Monolitic integrated digital semiconductor circuit - Google Patents

Monolitic integrated digital semiconductor circuit Download PDF

Info

Publication number
EP0036494A3
EP0036494A3 EP81101324A EP81101324A EP0036494A3 EP 0036494 A3 EP0036494 A3 EP 0036494A3 EP 81101324 A EP81101324 A EP 81101324A EP 81101324 A EP81101324 A EP 81101324A EP 0036494 A3 EP0036494 A3 EP 0036494A3
Authority
EP
European Patent Office
Prior art keywords
monolitic
semiconductor circuit
integrated digital
digital semiconductor
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81101324A
Other languages
German (de)
Other versions
EP0036494B1 (en
EP0036494A2 (en
Inventor
Kurt Dr. Hoffmann
Dieter Dipl.-Ing. Kantz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0036494A2 publication Critical patent/EP0036494A2/en
Publication of EP0036494A3 publication Critical patent/EP0036494A3/en
Application granted granted Critical
Publication of EP0036494B1 publication Critical patent/EP0036494B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
EP81101324A 1980-03-11 1981-02-24 Integrated mos semiconductor circuit Expired EP0036494B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3009303 1980-03-11
DE19803009303 DE3009303A1 (en) 1980-03-11 1980-03-11 MONOLITHICALLY INTEGRATED DIGITAL SEMICONDUCTOR CIRCUIT

Publications (3)

Publication Number Publication Date
EP0036494A2 EP0036494A2 (en) 1981-09-30
EP0036494A3 true EP0036494A3 (en) 1981-11-25
EP0036494B1 EP0036494B1 (en) 1984-07-25

Family

ID=6096869

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81101324A Expired EP0036494B1 (en) 1980-03-11 1981-02-24 Integrated mos semiconductor circuit

Country Status (4)

Country Link
US (1) US4454431A (en)
EP (1) EP0036494B1 (en)
JP (1) JPS56142663A (en)
DE (2) DE3009303A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6177421A (en) * 1984-08-21 1986-04-21 ラテイス・セミコンダクター・コーポレーシヨン Circuit and method of preventing latch-up of complementary metal oxide semiconductor device
JPH0618249B2 (en) * 1984-10-17 1994-03-09 富士通株式会社 Semiconductor integrated circuit
ATE67617T1 (en) * 1985-08-26 1991-10-15 Siemens Ag INTEGRATED CIRCUIT USING COMPLEMENTARY CIRCUIT TECHNOLOGY WITH A SUBSTRATE PRE-VOLTAGE GENERATOR.
US4794278A (en) * 1987-12-30 1988-12-27 Intel Corporation Stable substrate bias generator for MOS circuits
KR950002015B1 (en) * 1991-12-23 1995-03-08 삼성전자주식회사 Static source voltage generating circuit operated by an oscillator
CN105024674B (en) * 2015-03-13 2018-06-12 苏州迈瑞微电子有限公司 A kind of asynchronous reset

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2333296A1 (en) * 1975-11-28 1977-06-24 Honeywell Inf Systems SUBSTRATE POLARIZATION TENSION GENERATED BY REGENERATION OSCILLATOR
US4061929A (en) * 1975-09-22 1977-12-06 Kabushiki Kaisha Daini Seikosha Circuit for obtaining DC voltage higher than power source voltage
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794862A (en) * 1972-04-05 1974-02-26 Rockwell International Corp Substrate bias circuit
US3838357A (en) * 1973-10-25 1974-09-24 Honeywell Inf Systems Apparatus for using start-up of a crystal oscillator to synchronize power turn-on in various portions of a system
JPS53130990A (en) * 1977-04-20 1978-11-15 Toshiba Corp Integrated circuit device
DE2812378C2 (en) * 1978-03-21 1982-04-29 Siemens AG, 1000 Berlin und 8000 München Substrate bias generator for MIS integrated circuits
JPS5525220A (en) * 1978-08-11 1980-02-22 Oki Electric Ind Co Ltd Substrate bias generation circuit
US4229667A (en) * 1978-08-23 1980-10-21 Rockwell International Corporation Voltage boosting substrate bias generator
JPS5951750B2 (en) * 1978-11-24 1984-12-15 富士通株式会社 Substrate bias generation circuit
US4296340A (en) * 1979-08-27 1981-10-20 Intel Corporation Initializing circuit for MOS integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4061929A (en) * 1975-09-22 1977-12-06 Kabushiki Kaisha Daini Seikosha Circuit for obtaining DC voltage higher than power source voltage
FR2333296A1 (en) * 1975-11-28 1977-06-24 Honeywell Inf Systems SUBSTRATE POLARIZATION TENSION GENERATED BY REGENERATION OSCILLATOR
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE International Solid-State Circuits Conference, 13. Februar 1980 New York (US) A.C. GRAHAM et al.: "Battery Backup Circuits for Memories", seiten 58 und 59. * ganzes dokument * *
IEEE Journal of Solid-State Circuits, Band SC-15, Nr. 5, Oktober 1980 New York (US) J.Y. CHAN: "A 100ns 5 V only 64 K x 1 MOS Dynamic RAM", seiten 839-846. * seite 842, figur 6; Abschnitt "Cell Plate Generation Circuit" * *
PATENTS ABSTRACTS OF JAPAN, Band 3, Nr. 2, 13. Januar 1979 seite 164E83 & JP-A-53 130 990 (Tokyo Shibaura Denki K.K.) (15.11.1978) * zusammenfassung * *

Also Published As

Publication number Publication date
US4454431A (en) 1984-06-12
DE3009303A1 (en) 1981-09-24
EP0036494B1 (en) 1984-07-25
JPH0213821B2 (en) 1990-04-05
DE3164950D1 (en) 1984-08-30
JPS56142663A (en) 1981-11-07
EP0036494A2 (en) 1981-09-30

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