EP0019651B1 - Circuit électronique pour un relais à régime de temps déterminable - Google Patents

Circuit électronique pour un relais à régime de temps déterminable Download PDF

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Publication number
EP0019651B1
EP0019651B1 EP19790101750 EP79101750A EP0019651B1 EP 0019651 B1 EP0019651 B1 EP 0019651B1 EP 19790101750 EP19790101750 EP 19790101750 EP 79101750 A EP79101750 A EP 79101750A EP 0019651 B1 EP0019651 B1 EP 0019651B1
Authority
EP
European Patent Office
Prior art keywords
divider
output
input
chain
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19790101750
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German (de)
English (en)
Other versions
EP0019651A1 (fr
Inventor
Erwin Mauz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Westdeutsche Elektrogeraetebau GmbH
Original Assignee
Westdeutsche Elektrogeraetebau GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westdeutsche Elektrogeraetebau GmbH filed Critical Westdeutsche Elektrogeraetebau GmbH
Priority to EP19790101750 priority Critical patent/EP0019651B1/fr
Priority to DE7979101750T priority patent/DE2966462D1/de
Publication of EP0019651A1 publication Critical patent/EP0019651A1/fr
Application granted granted Critical
Publication of EP0019651B1 publication Critical patent/EP0019651B1/fr
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
    • H01H47/04—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay for holding armature in attracted position, e.g. when initial energising circuit is interrupted; for maintaining armature in attracted position, e.g. with reduced energising current

Definitions

  • the invention relates to an electronic circuit arrangement for a relay with time behavior which can be determined by actuating a switch, which contains a clock generator, a divider chain, astable and / or monostable and / or bistable flip-flops, logic logic elements and an output circuit for controlling the relay.
  • the invention is therefore based on the object of constructing an electronic circuit arrangement of the type described at the outset as a multipurpose assembly such that it can be operated with simple means, for example. can be optimally converted and used in the entire area of application by assigning different connections or even by changing the equipment only to a small extent, in order to control a relay with the desired timing. Furthermore, the task is to design the circuit arrangement so that several condition combinations specific for certain functions can be connected or supplemented with a single combination of logic elements to form partial assemblies such that between several connections for the switch acting in the input circuit and for Output circuits, the circuit arrangement with the desired timing for the control of the relay can be selected, if possible in such a way that only the specific external connection points are occupied.
  • the task is to make the circuit arrangement suitable for integration in a compact semiconductor component, in which the same component is always used - only by different wiring of the connection points, for example. with code signals, with input signals supplied by the switch and with the relay at various output connections - all practically required designs, both with regard to the time behavior function and with respect to the time range, can be realized.
  • a selection matrix which can be controlled two-dimensionally by DC voltage signals in accordance with the number of connected divider stage outputs.
  • Circuit arrangements with an electronic divider chain in combination with an RC oscillator have already become known (for example "electronic industry 5 - 1978, page 17), but these are only designed for specific applications.
  • a circuit arrangement according to in the first-mentioned group of features a relay with different timing functions and also within a large range of different delay, hold and drop times.
  • the divider chain as a multiple decade divider is made up of alternating "2" divider and "5" divider stages. Then it can be ensured that because of the additional control of a link branch with a meandering clock function of twice the frequency, ie. half the divider ratio, the blinking times and the blinking pauses are exactly the same length.
  • the clock generator in the frequency-determining circuit contains an adjustable RC element, which is composed of a potentiometer and a capacitor and can be connected to external solder connections.
  • an adjustable RC element which is composed of a potentiometer and a capacitor and can be connected to external solder connections.
  • the last-mentioned part of the task according to the invention namely a compact combination of the associated structural units on a semiconductor chip of the integrated type while observing all of the aforementioned and indicated possible variations, can be achieved in that at least the divider chain or the multiple decade divider, if appropriate with the associated one Selection matrix, and / or the FLIP-FLOP function chain with its associated condition combination integrated on a semiconductor module and the coding inputs of the selection matrix and the control inputs of the condition elements, and possibly connections of the clock generator for the external RC -Member and the clock inputs, reset inputs, the output circuits and the power supply lines are attached to the external solder connections of the semiconductor module in the technology characteristic of this.
  • an identical semiconductor component can be used for all practical applications, the production costs of which can be reduced considerably because it can be used in large quantities due to the possibility of universal use.
  • the bistable multivibrator 1 (FF,) is connected on the input side to the output "Z" of the selection matrix 2 via the line 3, while the two reset inputs 4 and 5 are connected to one another via the connecting line 6.
  • the voltage at its reset input 5 is namely determined by the structural units (OR 2 ) 8, (OR,) 9, (NOR,) 10 and by the control voltages "H” on the lines 11 applied to them and supplied by the switch (in case “1""delayed", 12 (for case “2”: delayed) and 13 (for case “3”: “pulse lengthening or shortening") at inputs 14a, 14b and 14c.
  • the signal on line 13 acts on input 14c of MONO-FLOPS 15 (MF 2 ), to whose output 16 an input 18 of NOR 4 element 19 is connected via negation element (N 4 ) 17.
  • the output 20 is connected via the line 21 to the set input 22 of the bistable multivibrator (FF 3 ) 23, at the set output 118 of which a signal is conducted via the line 24 and its branch 24 'to the input 25 of the NOR element 10 .
  • the units between the input 14c and the line 24 form a connection chain (15, 17, 19, 23) connected upstream of the NOR, link 10, which chain the input signal for the case "3" at the input 14c into that for the relay function "Pulse lengthening / shortening" necessary signal form on line 24 'converted.
  • the lines 3 and 6 are also connected to the inputs 26, 27 of the OR 4 element 28, the output line 29 of which, together with the output signal "Z" inverted via the N e negation element 30, on line 31 via line 32, the NOR e - Element 33 applied, the signal at its output 33 'via line 34 to the set input 35 and the signal on the output line 29 to the reset input 36 of the bistable flip-flop 37 (FF 4 ).
  • the signal at the set output 38 in turn acts on the input signal for the case "1, the OR 7 element 40, together with the input signal inverted by the N 2 negative element 39; the output signal of the OR 7 element 40 is thus effective on line 41 as long as the inverted input signal for the case "1" is present as "L” at the second input of the OR 7 element 40 and is passed to an output stage (not shown); after the end of the input signal for the case "1", the OR 7 element is 40 "H” applied to one input so that the voltage changes at the other input cannot take effect.
  • the set output 43 is connected via line 43 ', the N 1 negation element 44 to the one input 45 of the NOR 2 element 46, the other input 47 of which is the same as an input of the OR 7 element 40 with the one through the N 2 Negation element 39 is applied to the inverted input signal for the case "1".
  • the output 48 of the NOR 2 element 46 is connected to a first input 49 via the line 50, the signal on the line 24 lies via the line 24 "at the third input 51 of the NOR 5 element 52 and at the second input 53 another output signal from a similar link chain, which belongs to the input signal for the case "2.”
  • the output 54 of the NOR 5 element 52 is passed to a further output stage, not shown, via the line 55.
  • Case “1” also includes the diagrams of FIG. 4b for the blinking relay with the exact halving of the period.
  • the output signal of the OR 4 member 28, together with that of the N 6 member 30, results in a pulse sequence which is offset by exactly half a period compared to the signal in the output of the OR 4 member 28 at the output of the NOR e member 33, so that at the set input 35 of the bistable FF 4- flip-flop 37 alternately an "H” and an "L” signal occur and the set output 38 the desired flashing function occurs, the duration of the OR 7 member 40 on line 41 by the input signal for the event "1" is limited.
  • the input signal for case “3" is in the automatic part of the timing function corresponding to that of the input signal for case “2"; it only differs from the other in that the switch "signal time” disappears in an extreme manner to the short time of the MONO-FLOP stage (15 in FIG. 2) and the drop at the output 118 of the bistable FF 3 flip-flop 23 on “L” almost exactly after the preset divider period has elapsed. This corresponds to the time behavior of the "pulse lengthening or shortening" (cf. FIG. 4d).
  • the inside of the dash-dotted frame 201 represents the circuit arrangement accommodated on an integrated semiconductor component, of which, however, only those parts are drawn here which are not shown in FIG. 2 and FIG. 3 or are shown in less detail; between terminals "Z", “Z” 'and “R” (3, 31, 6), "1", “2” and “3” (11, 12 and 13) and finally the output lines 41 and 55 thus insert the circuit parts of FIGS. 2 and 3 analogously.
  • the clock generator 210 controls via a divider pre-stage (": 32") 211 in a manner known per se the multiple decade divider 212 (corresponding to the divider chain 7) (with the interposition of a transistor stage 213, the Schmitt trigger stage 214 and the Negation element 215).
  • the divider stages are each made up of a "5" divider and a “2" divider stage combined to form “10" divider stages; that's why, for example. at the A 'output double the frequency of that of the "A" output. All divider outputs A ', A, ...
  • the control signals of the cases “1", “2”, “3” each come about via a negation element 221, the Schmitt trigger stage 222 at an external solder connection 223, 224 and 225, respectively.
  • Each of these inputs is again in a manner known per se on a voltage divider on positive voltage; By connecting to ground when the switch is actuated, the positive input signals are generated.
  • Both the positive bias and the Schmitt trigger levels serve to increase the interference immunity.
  • the RC element connected from the outside to the solder connections 228, 229 from the potentiometer 226 and capacitor 227 is connected in the frequency-determining circuit;
  • the frequency of the generator 210 and thus the time period preset on the divider chain at the outputs 3, 31 is finely adjusted with the potentiometer 226 between the values of the decadal stages.
  • the solder connections 228, 229 are also biased positively by voltage dividers 230, 231.
  • a voltage regulator stage 233 is connected via solder connections 232, 232a to the current source for the voltage supply of the circuit arrangement outside and inside the semiconductor module.
  • the Schmitt trigger stage 235 and the negation elements 236, 237 can be used to reset signals into the circuit arrangement to connections which are still free Links are initiated; with the connection of the solder connection 238 from the outside by the capacitor 239, each flip-flop is automatically reset when the operating voltage is applied by the MONO-FLOP stage 240. Both connections are in turn set to positive voltage by voltage dividers 241, 242, so that the required interference immunity is ensured.
  • the reset signals occurring on lines 236a, 237a and 240a are optionally applied to lines 240a and 236a in the input of OR 2 element 8 (FIG. 2) or lines 237a and 240a in the input of OR 3 element.
  • the outputs 41 and 55 are each connected via a power amplifier stage 243, 244 or 245 to the external solder connections 246, 247 or 248, each of which is made interference-proof by a rectifier (e.g. 249) with positive bias. Between the output 55 and the power amplifier stage 244 there is a negation element 250, which has been mentioned several times in connection with FIG. 3.
  • This circuit branch is the one that is used for the relay control in the cases of timing behavior functions described above.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Relay Circuits (AREA)
  • Electronic Switches (AREA)

Claims (6)

1. Circuit électronique pour un relais dont le comportement dans le temps peut être déterminé par l'actionnement d'un commutateur, qui comprend un générateur de rythme (210), une chaîne de division (7), des bascules astables et/ou monostables et/ou bistables, des circuits logiques et un circuit de sortie pour l'attaque du relais, caractérisé en ce que la sortie d'au moins un étage de la chaîne de division (7) commandée par le générateur de rythme (210), de préférence par l'intermédiaire d'un pré- étage de division (211), attaque une bascule bistable (1) appartenant à une chaîne de fonction "FLIP-FLOP" dont le signal de sortie (43), conjointement avec un signal de commande ("1", "2" ou "3") fourni par le commutateur, est appliqué, sur des conducteurs (11, 12, 13) contenus dans le circuit d'entrée, par l'intermédiaire d'une chaîne de circuits logiques composée de certains des circuits logiques, éventuellement avec incorporation de circuits OU ("OR") (42), de négation ("N"), (39, 44), NI ("NOR") (46, 52), à l'entrée du circuit de sortie (41, 55), le signal de commande ("1", "2" ou "3"), éventuellement conjointement avec un signal de remise à zéro ("RESET") est appliqué, à au moins l'une des trois connexions (14a, 14b, 14c) des conducteurs (11, 12, 13) du circuit d'entrée, connexions qui sont toutes connectées à l'entrée de remise à zéro (5) de la chaîne de division (7) (a) la première connexion (14b), par l'intermédiaire d'une première combinaison de conditions (BK,), composée d'un premier (9) et d'un deuxième (8) circuits OU ("OR"), connectés en série, chacun par l'une de ses entrées, (b) la deuxième connexion (14a), par l'intermédiaire d'une deuxième combinaison de conditions (BK2) composée de la première combinaison de conditions (BK,) et d'un circuit NI ("NOR") (10) connecté en amont de cette combinaison à une deuxième entrée du premier circuit OU ("OR") (9), (c) et la troisième connexion (14c), par l'intermédiaire d'une troisième combinaison de conditions (BK3), composée d'une bascule monostable (15) (MONO-FLIP-FLOP), de circuits de négation (17), NI ("NOR") (19) et d'une bascule bistable (FLIP-FLOP) (23), les signaux de sortie des chaînes de circuits logiques comportant des bascules bistables (par exemple 37 "FF4", 116 "FF2", 23 "FF3") ou un circuit NI (par exemple 46), attaquant chacun une autre entrée du circuit NI ("NOR") (10) de la deuxième conbinaison de conditions (BK2).
2. Circuit électronique selon la revendication 1, caractérisé en ce qu'entre les sorties de plusieurs étages de la chaîne de division (7) et les entrées des bascules bistables (1) attaquées, se trouve une . matrice de sélection (2) commandable, codée dans les deux dimensions par des signaux de tension continue ("x", "y"), en fonction du nombre des sorties (A, A', ... D', D) des étages de division qui leur sont raccordés.
3. Circuit électronique selon l'une des revendications 1 et 2, caractérisé en ce que, en supplément de l'une ("Z") des sorties d'étages de la chaîne de division (7), éventuellement par l'intermédiaire d'une matrice de sélection (2), une autre sortie ("Z'") possédant un demirapport de division, est connectée par l'intermédiaire d'une chaîne de circuits logiques, à l'entrée de mise à un d'une autre bascule bistable ("FF4") (37), dont le signal de sortie (38) est appliqué, avec le premier signal de commande ("1 "), à l'entrée (41) d'un circuit de sortie comportant un amplificateur de puissance (41), par l'intermédiaire d'un circuit OU ("OR") (40).
4. Circuit électronique selon l'une des revendications 1 à 3, caractérisé en ce que la chaîne de division (7) est construite sous la forme d'un diviseur décadique multiple (212) composé d'étages de division ("2") et d'étages de division ("5") en alternance.
5. Circuit électronique selon l'une des revendications 1 à 4, caractérisé en ce que le générateur de rythme (210) renferme, dans le circuit déterminant la fréquence, un circuit RC réglable (potentiomètre 226, condensateur 227) qui peut être raccordé aux connexions soudées extérieures.
6. Circuit électronique selon l'une des revendications 1 à 5, caractérisé en ce qu'au moins la chaîne de division (7) ou les diviseurs décadiques multiples (212), éventuellement avec la matrice de sélection (2) correspondante et/ou la chaîne de fonction FLIP-FLOP, avec sa combinaison de conditions correspondante (BK1, BK2, ou BK3 respectivement) sont rassemblées intégrées sur un composant semi-conducteur et les entrées de codage ("x", "y") de la matrice de sélection (2) et les entrées de commande (11, 12, 13) des combinaisons de conditions et ainsi qu'éventuellement des connexions du générateur de rythme (210) prévues pour le circuit RC extérieur (236, 237) et les entrées de rythme (213, 214, 215), entrées de remise à zéro (236a, 237a, 240a), les circuits de sortie et les conducteurs d'alimentation en courant arrivant à des connexions soudées extérieures (216, 217; 223 à 225; 234, 238; 228, 229; 246 à 248; 232, 232a) sont montées dans la technologie caractéristique pour ces composants.
EP19790101750 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable Expired EP0019651B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19790101750 EP0019651B1 (fr) 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable
DE7979101750T DE2966462D1 (en) 1979-06-01 1979-06-01 Electronic circuit for a relay with a determinable time-rating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19790101750 EP0019651B1 (fr) 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable

Publications (2)

Publication Number Publication Date
EP0019651A1 EP0019651A1 (fr) 1980-12-10
EP0019651B1 true EP0019651B1 (fr) 1983-12-07

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EP19790101750 Expired EP0019651B1 (fr) 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable

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DE (1) DE2966462D1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2224784A1 (de) * 1972-05-20 1973-12-06 Volkswagenwerk Ag Digitales zeitrelais zur gewinnung eines betaetigungssignals vorbestimmter zeitdauer
DE2243799B2 (de) * 1972-09-04 1975-01-23 Schleicher Gmbh & Co Relais-Werke Kg, 1000 Berlin Elektronisches Zeltverzögerungsglied für Ein- oder Mehrbereichs-Zeltrelais
DD136686B1 (de) * 1978-05-18 1983-04-27 Dietrich Armgarth Programmierbare integrationfaehige zeitsteuerschaltung

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DE2966462D1 (en) 1984-01-12
EP0019651A1 (fr) 1980-12-10

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