EP0019651A1 - Circuit électronique pour un relais à régime de temps déterminable - Google Patents

Circuit électronique pour un relais à régime de temps déterminable Download PDF

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Publication number
EP0019651A1
EP0019651A1 EP19790101750 EP79101750A EP0019651A1 EP 0019651 A1 EP0019651 A1 EP 0019651A1 EP 19790101750 EP19790101750 EP 19790101750 EP 79101750 A EP79101750 A EP 79101750A EP 0019651 A1 EP0019651 A1 EP 0019651A1
Authority
EP
European Patent Office
Prior art keywords
divider
output
input
chain
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19790101750
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German (de)
English (en)
Other versions
EP0019651B1 (fr
Inventor
Erwin Mauz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Westdeutsche Elektrogeraetebau GmbH
Original Assignee
Westdeutsche Elektrogeraetebau GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westdeutsche Elektrogeraetebau GmbH filed Critical Westdeutsche Elektrogeraetebau GmbH
Priority to EP19790101750 priority Critical patent/EP0019651B1/fr
Priority to DE7979101750T priority patent/DE2966462D1/de
Publication of EP0019651A1 publication Critical patent/EP0019651A1/fr
Application granted granted Critical
Publication of EP0019651B1 publication Critical patent/EP0019651B1/fr
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
    • H01H47/04—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay for holding armature in attracted position, e.g. when initial energising circuit is interrupted; for maintaining armature in attracted position, e.g. with reduced energising current

Definitions

  • the present invention relates to an electronic circuit arrangement for a relay with a time behavior which can be defined by the actuation of a switch and which contains a valley generator, a divider chain, astable and / or monostable and / or bistable flip-flops, logic logic elements and an output circuit for controlling the relay.
  • the present invention is therefore based on the object of constructing an electronic circuit arrangement of the type described in the introduction so compactly that it can be operated with simple means, for example can be optimally converted and used in the entire area of application by assigning different connections or even by changing the equipment only to a small extent, in order to control a relay with the desired timing.
  • the task is to design the circuit arrangement in such a way that a plurality of structural units or assemblies specific to certain functions can be connected or supplemented with a single common group of structural units in such a way that between several connections for the switch acting in the input circuit and for output circuits the circuit arrangement with the desired timing for the control of the relay can be selected, if possible in such a way that only the specific external connection points are occupied.
  • the task is to design the circuit arrangement suitable for integration in a compact semiconductor component, in which the same component is always used - only by different wiring of the connection points, for example.
  • code signals with input signals supplied by the switch and with the relay at various output connections - all practically required designs, both with regard to the time behavior function and with respect to the time range, can be realized.
  • OR OR
  • negation negation
  • NOR NOW-NOCH
  • RESET reset
  • a two-dimensionally corresponding DC voltage signal corresponds to the number of connected divider stage outputs (A, A ', ... D', D).
  • "y" codes selectable selection matrix.
  • Circuit arrangements with an electronic divider chain in combination with an RC oscillator have already become known (for example "electronic industry 5 - 1978, page 17), but these are only designed for specific applications.
  • a circuit arrangement according to the first feature group already implement a relay with different timing functions and also within a large range of different delay, hold and drop times even select the time ranges only by the type of external voltage connection of special connections.
  • blinking relay controls can also be implemented with the same timing behavior functions.
  • the divider chain as a multiple decade divider is made up of alternating "2" divider and "5" divider stages. Then it can be ensured that because of the additional control of a link branch with a meandering clock function of twice the frequency, ie. half the divider ratio, the blinking times and the blinking pauses are exactly the same length.
  • the clock generator in the frequency-determining circuit contains an adjustable RC element composed of a potentiometer and a capacitor.
  • the levels of the divider time range selection can be continuously changed and each delay value can be set effortlessly and continuously.
  • the last-mentioned part of the object according to the invention namely a compact combination of the associated structural units on a semiconductor component which integrates ten design while observing all of the aforementioned and indicated possibilities of variation can be achieved by integrating at least the divider chain - possibly with its associated selection matrix - and / or the FLIP-FLOP function chain with its condition elements integrated on a semiconductor module and the coding inputs the divider chain selection matrix or control inputs of the condition elements, as well as, if applicable, the clock generator for the external RC element or the clock inputs, reset inputs, the output circuits and the power supply lines to external solder connections of the semiconductor component in the for this characteristic technology.
  • an identical semiconductor component can be used for all practical applications, the production costs of which can be reduced considerably because it can be used in large numbers due to the possibility of universal use.
  • the bistable multivibrator 1 (FF 1 ) is connected on the input side to the output "Z" of the selection matrix 2 via line 3, while the two reset inputs 4 and 5 are connected to one another via line 6.
  • the voltage at its reset input 5 is namely determined by the structural units (OR 2 ) 8, (OR 1 ) 9, (NOR 1 ) 1 0 , and at these applied input voltages "H” on the lines 11 supplied by the switch (in the case of "1””suitdelayed"), 12 (for case “2”: waste delayed) and 13 (for case “3”: "pulse-lengthening or shortening”).
  • the signal on line 13 is the result of loading input 14 of MONO-FLOPS 15, to whose output 16 an input 18 of NOR 4 element 19 is connected via negation element (N 4 ) 17.
  • the output 2o is connected via line 21 to the set input 22 of the bistable multivibrator (FF 3 ) 23, the output signal of which is led via lines 24 and 25 to line 13 of NOR 1 element 1o.
  • the units between the input 14 and the line 24 form a link chain (15, 17, 19, 23) connected upstream of the NOR 4 link lo, which converts the input signal "3" at the input 14 into the "pulse-extending / - Shortening "necessary signal form on line 13.
  • Lines 3 and 6 are also connected to the inputs 26, 27 of the OR 4 element 28, the output thereof Line 29 together with the inverted via the N 6 negation element 3o output signal "Z '" on the line 31 via the line 32 to the NOR 6 element 33, the output signal via the line 34, the set input 35 and the signal on the output line 29 the reset input 36 of the bistable multivibrator 37.
  • the set output 38 in turn acts on the OR 7 element 40 together with the input signal “1” inverted by the N 2 negative element 39; the output signal of the OR7 element is thus effective on line 41, as long as the inverted input signal "1” is present as "L” at the second input of the OR 7 element, and is given to an output stage (not shown); after the end of the input signal "1", the OR 7 element 4o has "H” applied to one input, so that the voltage changes at the other input cannot take effect.
  • the set output 42 is connected via line 43, the N 1 negation element 44 to the one input of the NOR 2 element 46, the other input 47 of which is also acted upon by the inverted input signal "1".
  • the output 48 of the NOR 2 link 46 is connected to a first input 49 via the line 50, the signal on the line 24 is at the third input 51 of the NOR 5 link 52 and a further output signal from a similar link chain at the second input 53 belonging to the input signal "2".
  • the output 54 of the NOR 5 element 52 is passed to a further output stage, not shown, via the line 55.
  • Case “1” also includes the diagrams in Fig. 4b for the flashing relay with an exact halving of the period.
  • the output signal of the OR 4 element together with that of the N 6 negative element 3o results in a pulse sequence at the output of the NOR 6 element 33 which is offset by exactly half a period compared to the signal in the output of the OR 4 element 28, so that at the set input 35 the bistable FF 4 flip-flop 37 alternately an "H” and an "L” signal occur and the set output 38 the desired flashing function occurs, the duration of the OR 7 member 4o on line 41 limited by the input signal "1" becomes.
  • the output 109 of the FF 1 flip-flop lo4 is set to "H", so that an "L” signal is present at the input 111 of the NOR 2 member 112 via the N 1 negative element llo, and an "H” signal comes to an end at the output 113 of the NOR 2 element.
  • the inside of the dash-dotted frame 2ol represents the circuit arrangement accommodated on an integrated semiconductor module, of which, however, only those parts are drawn which are not shown in FIG. 2 and FIG. 3 or are shown in less detail; between the connections "Z", “Z '" and “R” (202, 203, 2o4), "1", “2” and “3” (2 0 5, 2o6 and 207) and finally 208 and 209 are insert the circuit parts of Figures 2 and 3 analogously.
  • the generator 21o controls the decadal divider chain 212 via a divider pre-stage (": 32") 211 in a manner known per se (with the interposition of a transistor stage 213, the Schmitt trigger stage 214 and the negation element 215).
  • the divider stages are each composed of a "5" divider and a “2" divider stage, alternating to "10" divider stages; that's why, for example. at the A'-output double the frequency of "A" -output. All divider outputs A ', A, ...
  • D', D lead into the row lines, the connections 216, 217 via the Schmitt trigger stages 218, 219 to the connections "x", "y” of the row lines of the two-dimensional selection matrix 220, at the outputs 203, 2 0 2 of which - as is also known from similar cases - the divider chain output signals lie.
  • the input signals "1", “2”, “3” each come about via a negation element 221, the Schmitt trigger stage 222 at an external solder connection 223, 224 and 225, respectively.
  • Each of these inputs is again in a manner known per se on a voltage divider on positive voltage; By connecting to ground when the switch is actuated, the positive input signals are generated.
  • Both the positive bias and the Schmitt trigger levels serve to increase the interference immunity.
  • the RC element connected from the outside to the solder connections 228, 229 in the frequency-determining circuit is connected to the generator 21o from the potentiometer 226 and the capacitor 227;
  • the frequency of the generator 21o and thus the time period preset on the divider chain at the outputs 2o2, 2o3 is finely adjusted with the potentiometer 226 between the decadal stages.
  • the solder connections 228, 229 are also biased positively by voltage dividers 230, 231.
  • a voltage regulator stage 234 is connected via the solder connections 232, 233 to the current source for the voltage supply of the circuit arrangement outside and inside the semiconductor module.
  • each flip-flop is automatically reset when the operating voltage is applied by the MONO-FLOP stage 24o. Both connections are in turn set to positive voltage by voltage dividers 241, 242, so that the required interference immunity is ensured.
  • the on the lines Reset signals occurring at 236a, 237a and 24oa are optionally applied to lines 24oa and 236a in the input of OR 2 element 8 (FIG. 2) or lines 237a and 24oa in the input of OR 3 element.
  • the outputs 2o8 (41 in Fig. 2) and 209 (55 in Fig. 2) are each connected via a power amplifier stage 243, 244 and 245 to the external solder connections 246, 247 and 248, each of which is connected by a rectifier positive bias (e.g. 249) is made interference-proof.
  • a negation element 25 0 is the one that is used for the relay control in the cases of timing behavior functions described above.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Relay Circuits (AREA)
  • Electronic Switches (AREA)
EP19790101750 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable Expired EP0019651B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19790101750 EP0019651B1 (fr) 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable
DE7979101750T DE2966462D1 (en) 1979-06-01 1979-06-01 Electronic circuit for a relay with a determinable time-rating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19790101750 EP0019651B1 (fr) 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable

Publications (2)

Publication Number Publication Date
EP0019651A1 true EP0019651A1 (fr) 1980-12-10
EP0019651B1 EP0019651B1 (fr) 1983-12-07

Family

ID=8186130

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19790101750 Expired EP0019651B1 (fr) 1979-06-01 1979-06-01 Circuit électronique pour un relais à régime de temps déterminable

Country Status (2)

Country Link
EP (1) EP0019651B1 (fr)
DE (1) DE2966462D1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2224784A1 (de) * 1972-05-20 1973-12-06 Volkswagenwerk Ag Digitales zeitrelais zur gewinnung eines betaetigungssignals vorbestimmter zeitdauer
DE2243799B2 (de) * 1972-09-04 1975-01-23 Schleicher Gmbh & Co Relais-Werke Kg, 1000 Berlin Elektronisches Zeltverzögerungsglied für Ein- oder Mehrbereichs-Zeltrelais
DE2606983B1 (de) * 1976-02-20 1977-04-21 Siemens Ag Halbleiterbaustein aus integrierten Transistoren,insbesondere fuer Steuereinrichtungen von Fernsprechvermittlungsanlagen
DD136686A1 (de) * 1978-05-18 1979-07-18 Dietrich Armgarth Integrierter zeitsteuerschaltkreis

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2224784A1 (de) * 1972-05-20 1973-12-06 Volkswagenwerk Ag Digitales zeitrelais zur gewinnung eines betaetigungssignals vorbestimmter zeitdauer
DE2243799B2 (de) * 1972-09-04 1975-01-23 Schleicher Gmbh & Co Relais-Werke Kg, 1000 Berlin Elektronisches Zeltverzögerungsglied für Ein- oder Mehrbereichs-Zeltrelais
DE2606983B1 (de) * 1976-02-20 1977-04-21 Siemens Ag Halbleiterbaustein aus integrierten Transistoren,insbesondere fuer Steuereinrichtungen von Fernsprechvermittlungsanlagen
DD136686A1 (de) * 1978-05-18 1979-07-18 Dietrich Armgarth Integrierter zeitsteuerschaltkreis

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS AUSTRALIA, Band 36, NR. 6, September 1974, Sydney G. SWAIN "The XR-2240: a versatile programmable timer" Seiten 74 bis 77 *

Also Published As

Publication number Publication date
EP0019651B1 (fr) 1983-12-07
DE2966462D1 (en) 1984-01-12

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