EP0019651A1 - Electronic circuit for a relay with a determinable time-rating - Google Patents

Abstract

1. Electric circuit arrangement for a relay with time behaviour determinable by the actuation of a switch, comprising a timing pulse generator (210), a divider chain (7), astable and/or monostable and/or bistable trigger stages, logic linkage members and an output circuit for the actuation of the relay, characterised in that the output of at least one stage of the divider chain (7) controlled by the timing pulse generator (210), preferably through a divider preliminary stage (211), acts upon a bistable trigger stage (1) pertaining to a FLIP-FLOP function chain, the output signal (43) of which trigger stage, together with a control signal ("1", "2" or "3") delivered by the switch, lies on leads (11, 12, 13) in the input circuit through a linkage member chain assembled from some of the logic linkage members, possibly with inclusion of OR-members (42), Negation members (39, 44), NOR-members (46, 52), at the entry of the output circuit (41, 55), while the control signal ("1", "2" or "3"), possibly together with a RESET-signal (236a, 240a), lies on at least one of three terminals (14a, 14b, 14c) of the leads (11, 12, 13) of the input circuit, of which (a) the first terminal (14b) lies through a first condition combination (BK1 ), consisting of a first (9) and a second (8) OR-member connected in series with one of its inputs in each case, (b) the second terminal (14a) lies through a second condition combination (BK2 ), consisting of the first condition combination (BK1 ) and a NOR-member (10) connected in series before this at a second input of the first OR-member (9) (c) and the third terminal (14c) lies through a third condition combination (BK3 ), consisting of monostable trigger stage (15) (MONO-FLIP-FLOP), Negation members (17), NOR-members (19) and bistable trigger stage (FLIP-FLOP) (23), on the reset input (5) of the divider chain (7), while the output signals of the linkage member chains act with bistable trigger stages (for example 37 "FF4 ", 116 "FF2 ", 23 "FF3 ") or NOR-member (for example 46) each upon a further input of the NOR-member (10) of the second condition combination (BK2 ).

Description

The present invention relates to an electronic circuit arrangement for a relay with a time behavior which can be defined by the actuation of a switch and which contains a valley generator, a divider chain, astable and / or monostable and / or bistable flip-flops, logic logic elements and an output circuit for controlling the relay.

Relays with definable time behavior triggered by the actuation of a switch exist in the relevant technical area of technology of the time-keeping switch in numerous and sometimes very different embodiments. First of all, a distinction has to be made between analog time-keeping switches, for example. an RC circuit to determine the time behavior in connection with a non-linear discharge element, e.g. a switching diode, a thyristor or the like. or in the purely mechanical version an electromechanical or a pneumatic escapement are used, on the one hand, and relays, some of which are made up of digital units, e.g. Counters or the like Make use or are built entirely in digital technology.

This variety of practical designs is partly due to the fact that not only switching times in the order of magnitude, ie. in several powers of ten different areas depending on the application, but also relay control circuit arrangements with different, typical time behavior, e.g. delayed or delayed, impnls-prolonging or shortening, stimulating, additive delayed-and others.

Until now, these requirements could only be met in different time ranges and with different timing functions by means of partially completely different constructions; extreme examples are the staircase lighting time switches, electronic flasher relays, toggle relays, capacitor wiping relays, etc. Digital time relays meet all requirements with regard to the time range, but they require more effort and can only be produced at relatively high costs all if different time behavior is required, which can only be achieved with digital timing relays using complex chains of logic links.

The present invention is therefore based on the object of constructing an electronic circuit arrangement of the type described in the introduction so compactly that it can be operated with simple means, for example can be optimally converted and used in the entire area of application by assigning different connections or even by changing the equipment only to a small extent, in order to control a relay with the desired timing. In an increased form, the task is to design the circuit arrangement in such a way that a plurality of structural units or assemblies specific to certain functions can be connected or supplemented with a single common group of structural units in such a way that between several connections for the switch acting in the input circuit and for output circuits the circuit arrangement with the desired timing for the control of the relay can be selected, if possible in such a way that only the specific external connection points are occupied.

In the last increase, the task is to design the circuit arrangement suitable for integration in a compact semiconductor component, in which the same component is always used - only by different wiring of the connection points, for example. With code signals, with input signals supplied by the switch and with the relay at various output connections - all practically required designs, both with regard to the time behavior function and with respect to the time range, can be realized.

The above-described task of the initially most general form is achieved according to the invention in that the output of at least one stage of the divider chain controlled by the clock generator, preferably via a divider pre-stage, acts on a bistable multivibrator belonging to a FLIP-FLOP function chain, the output signal of which together with a input signal supplied by the switch via logic gates, possibly with the interposition of OR ("OR"), negation ("N"), NOW-NOCH ("NOR") elements at the input of the output circuit, the input signal - if necessary together with a reset ("RESET") signal via an OR and / or an upstream WEDER-NOCH and / or an upstream link chain comprising a monostable multivibrator (MONO-FLOP) negation-NEDER-NOCH ^£ links and bistable flip-flop (FLIP-FLOP) are at the reset input of the divider chain.

In a further embodiment, between the outputs of several stages of the divider chain and the inputs of the flip-flop (s) acted upon, a two-dimensionally corresponding DC voltage signal ("x") corresponds to the number of connected divider stage outputs (A, A ', ... D', D). , "y") codes selectable selection matrix.

Circuit arrangements with an electronic divider chain in combination with an RC oscillator have already become known (for example "electronic industry 5 - 1978, page 17), but these are only designed for specific applications. On the other hand, with a circuit arrangement according to the first feature group already implement a relay with different timing functions and also within a large range of different delay, hold and drop times even select the time ranges only by the type of external voltage connection of special connections. If, in addition to the one output ("Z") of the divider stages - optionally via a selection matrix - a further output ("Z"') with half the division ratio is connected via a link chain to the input of a further bistable multivibrator whose Output signal together with an input signal ("1") via an OR gate at the input of an output circuit, blinking relay controls can also be implemented with the same timing behavior functions.

Particularly in connection with the last-mentioned application, it may be useful if the divider chain as a multiple decade divider is made up of alternating "2" divider and "5" divider stages. Then it can be ensured that because of the additional control of a link branch with a meandering clock function of twice the frequency, ie. half the divider ratio, the blinking times and the blinking pauses are exactly the same length.

In all the configurations described so far, it is also advantageous if the clock generator in the frequency-determining circuit contains an adjustable RC element composed of a potentiometer and a capacitor. With this potentiometer, for example, the levels of the divider time range selection can be continuously changed and each delay value can be set effortlessly and continuously.

The last-mentioned part of the object according to the invention, namely a compact combination of the associated structural units on a semiconductor component which integrates ten design while observing all of the aforementioned and indicated possibilities of variation can be achieved by integrating at least the divider chain - possibly with its associated selection matrix - and / or the FLIP-FLOP function chain with its condition elements integrated on a semiconductor module and the coding inputs the divider chain selection matrix or control inputs of the condition elements, as well as, if applicable, the clock generator for the external RC element or the clock inputs, reset inputs, the output circuits and the power supply lines to external solder connections of the semiconductor component in the for this characteristic technology.

In this form, an identical semiconductor component can be used for all practical applications, the production costs of which can be reduced considerably because it can be used in large numbers due to the possibility of universal use.

• Fig.l: einen wesentlichen Teil der Zeitverhaltens-Funktionen mit verschiedenen Schalterbetätigungs-Arten
  • A Dauerbetrieb mit Anzug-Verzögerung
  • B Kurzbetrieb mit Abfall-Verzögerung
  • C beliebiger Dauer mit konstanter Relaiszeit
  • D additive Anzugverzögerung
• Fig.2: ein Blockschaltbild für denjenigen Teil, der die Wirkung der vom Schalter gelieferten Eingangsimpulse bei der Auslösung der Zeitverhaltensfunktion betrifft;
• Fig.3: ein Blockschaltbild für denjenigen Teil, der den automatisch ablaufenden Abschnitt der Zeitverhaltens-Funktion betrifft;
• Fig.4: a) die Spannungsdiagramme an verschiedenen Knotenpunkten der Schaltungsanordnung für die Anzug-Verzögerung
  • b) do. für die Blinkschaltung
  • c) do. für die Abfall-Verzögerung
  • d) do. für Impulsverlängerung bzw. -verkürzung;
• Fig.5: ein Blockschaltbild für denjenigen Teil, der zur Ergänzung der Teile von Fig.2 und Fig.3 zu einer Halbleiter-Kompaktbaustein-geeigneten Schaltungsanordnung gehört.

In the following an embodiment of the invention is described with reference to the drawing; it represents:

• Fig.l: an essential part of the timing functions with different switch actuation types
  • A Continuous operation with pull-in delay
  • B Short operation with a delay in waste
  • C any duration with constant relay time
  • D additive pull-in delay
• 2 shows a block diagram for the part which relates to the effect of the input pulses supplied by the switch when the time behavior function is triggered;
• 3 shows a block diagram for the part which relates to the automatically running section of the time behavior function;
• Fig.4: a) the voltage diagrams at various nodes of the circuit arrangement for the pull-in delay
  • b) do. for the flashing circuit
  • c) do. for the waste delay
  • d) do. for pulse lengthening or shortening;
• 5 shows a block diagram for the part which belongs to a semiconductor compact circuit suitable circuit arrangement to complement the parts of FIGS. 2 and 3.

In FIG. 1, below the time diagram "A" for the input signal generated by the switch, those "1" for the desired pull-in delay, "2" for a flashing relay operating normally, "3" for a flashing relay with pull-in delay are shown. In case B - input signal generated by the switch - diagram "1" shows the desired time behavior for dropout delay, diagram "2" the case of the wiping relay, diagram "3" the case of the blinking relay with dropout delay and diagram "4" the case of a relay which picks up again after a predetermined period of time.

Among the two input signal diagrams C ₁ and C ₂ for a long or short pulse is the relay function with constant duration, ie. in the first case for the function "pulse-shortening", drawn in the second for the function "pulse-lengthening". Finally, the relay function for additive delay is shown below D with repeated switch actuation.

In FIG. 2, the bistable multivibrator 1 (FF ₁ ) is connected on the input side to the output "Z" of the selection matrix 2 via line 3, while the two reset inputs 4 and 5 are connected to one another via line 6. As long as there is no pulse "L" at the reset input 5 of the divider chain 7, the divider chain 7 is blocked; the voltage at its reset input 5 is namely determined by the structural units (OR ₂ ) 8, (OR ₁ ) 9, (NOR ₁ ) 1 ₀ , and at these applied input voltages "H" on the lines 11 supplied by the switch (in the case of "1""suitdelayed"), 12 (for case "2": waste delayed) and 13 (for case "3": "pulse-lengthening or shortening").

The signal on line 13 is the result of loading input 14 of MONO-FLOPS 15, to whose output 16 an input 18 of NOR ₄ element 19 is connected via negation element (N ₄ ) 17. The output 2o is connected via line 21 to the set input 22 of the bistable multivibrator (FF ₃ ) 23, the output signal of which is led via lines 24 and 25 to line 13 of NOR ₁ element 1o. The units between the input 14 and the line 24 form a link chain (15, 17, 19, 23) connected upstream of the NOR ₄ link lo, which converts the input signal "3" at the input 14 into the "pulse-extending / - Shortening "necessary signal form on line 13.

Lines 3 and 6 are also connected to the inputs 26, 27 of the OR ₄ element 28, the output thereof Line 29 together with the inverted via the N ₆ negation element 3o output signal "Z '" on the line 31 via the line 32 to the NOR ₆ element 33, the output signal via the line 34, the set input 35 and the signal on the output line 29 the reset input 36 of the bistable multivibrator 37. The set output 38 in turn acts on the OR ₇ element 40 together with the input signal “1” inverted by the N ₂ negative element 39; the output signal of the OR7 element is thus effective on line 41, as long as the inverted input signal "1" is present as "L" at the second input of the OR ₇ element, and is given to an output stage (not shown); after the end of the input signal "1", the OR ₇ element 4o has "H" applied to one input, so that the voltage changes at the other input cannot take effect.

The set output 42 is connected via line 43, the N ₁ negation element 44 to the one input of the NOR ₂ element 46, the other input 47 of which is also acted upon by the inverted input signal "1". The output 48 of the NOR ₂ link 46 is connected to a first input 49 via the line 50, the signal on the line 24 is at the third input 51 of the NOR ₅ link 52 and a further output signal from a similar link chain at the second input 53 belonging to the input signal "2". The output 54 of the NOR ₅ element 52 is passed to a further output stage, not shown, via the line 55.

4 shows the diagrams belonging to the input signals "1", "2" and "3" for various nodes of the circuit arrangement. In the case where "1" in 4a is in the "H" at the input of NOR ₁ -Gliedes 1o a "L" whose output, which via the OR ₁ - 9 - OR2, and - lo - links to the reset input 5 the divider chain 7 is guided, whereupon this starts.

Case "1" also includes the diagrams in Fig. 4b for the flashing relay with an exact halving of the period. The output signal of the OR ₄ element together with that of the N ₆ negative element 3o results in a pulse sequence at the output of the NOR ₆ element 33 which is offset by exactly half a period compared to the signal in the output of the OR ₄ element 28, so that at the set input ³⁵ the bistable FF ₄ flip-flop 37 alternately an "H" and an "L" signal occur and the set output 38 the desired flashing function occurs, the duration of the OR ₇ member 4o on line 41 limited by the input signal "1" becomes.

In case "2" occurs on the input side, ie. in the switch output circuit section the function shown in FIG. 4c with an "H" signal during the activated switch position, during the duration of which the divider chain 7 is blocked; this "H" signal is present at the output of the OR ₂ element 8. The input signal "3" - regardless of its duration - generates a short pulse "H" at the output of the MF ₂ MONO-FLOP module 15, which is inverted by the N ₄ negation element 17, so that the output 2o of the NOR ₄ -link 19 is an "H" short pulse, which now has the same effect as the input signal "1", namely that the divider chain is released.

The structural units shown in FIG. 3 and their combination in terms of circuitry are important for the description of the automatically running part of the time behavior functions. As already described, the matrix output signals "Z '", "Z" and the reset signal "R" on lines lol, lo2 and lo3 act on the bistable FF ₁ flip-flop lo4 or via the OR ₄ element 1 ₀ 5, the N ₆ link lo6 and the NOR ₆ link lo7 the bistable multivibrator 108.

After the preset divider period has elapsed, the output 109 of the FF ₁ flip-flop lo4 is set to "H", so that an "L" signal is present at the input 111 of the NOR ₂ member 112 via the N ₁ negative element llo, and an "H" signal comes to an end at the output 113 of the NOR ₂ element. Via the NOR ₅ link 114 it becomes an "L" signal, that is, after the delay time preset on the divider chain has elapsed, an "H" status behind an unrepresented negation link, ie. the transition to the "H" control signal for the relay required for the desired "pull-in delay" function. When the input signal "1" drops after the switch is reset to the non-activated position, an "L" state occurs at the output 113 of the NOR ₂ element, and thus after the negation behind the NOR ₅ element 114, a drop back to "L" a (see Fig.4a).

If an "L" state occurs after the switch on line lo3 is reset in the case of input signal "2", then the divider chain is released and after the preset period of time the output lo9 of the FF ₁ flip-flop lo4 is set to "H"; An “H” signal is then present at the reset input 115 of the bistable FF ₂ multivibrator 116, that is to say an “L” signal at the set output 117; the switching states at the output lo9 of the bistable FF ₁ flip-flop lo4 and also at that 117 of the bistable FF ₂ flip-flop 116 thus reverse and the signal in the time behavior function then changes to "L" and at the output of the negation element, not shown behind the NOR ₅ link 114 also in "L"; this then corresponds to the time behavior function for "drop delay" (cf. FIG. 4c).

The case of the input signal "3" is in the automatic part of the timing function corresponding to that of the input signal "2"; so it only differs in that the switch "signal time" extremely disappears to the short time of the MONO-FLOP stage (15 in FIG. 2) and the drop at the output 118 of the bistable FF ₃ flip-flop 119 falls to "L" takes place almost exactly after the preset divider period has elapsed. This corresponds to the time behavior of the "pulse lengthening or shortening" (see Fig. 4d).

In FIG. 5, the inside of the dash-dotted frame 2ol represents the circuit arrangement accommodated on an integrated semiconductor module, of which, however, only those parts are drawn which are not shown in FIG. 2 and FIG. 3 or are shown in less detail; between the connections "Z", "Z '" and "R" (202, 203, 2o4), "1", "2" and "3" (2 ₀ 5, 2o6 and 207) and finally 208 and 209 are insert the circuit parts of Figures 2 and 3 analogously.

liegen.The generator 21o controls the decadal divider chain 212 via a divider pre-stage (": 32") 211 in a manner known per se (with the interposition of a transistor stage 213, the Schmitt trigger stage 214 and the negation element 215). The divider stages are each composed of a "5" divider and a "2" divider stage, alternating to "10" divider stages; that's why, for example. at the A'-output double the frequency of "A" -output. All divider outputs A ', A, ... D', D lead into the row lines, the connections 216, 217 via the Schmitt trigger stages 218, 219 to the connections "x", "y" of the row lines of the two-dimensional selection matrix 220, at the outputs 203, 2 ₀ 2 of which - as is also known from similar cases - the divider chain output signals

lie.

The input signals "1", "2", "3" each come about via a negation element 221, the Schmitt trigger stage 222 at an external solder connection 223, 224 and 225, respectively. Each of these inputs is again in a manner known per se on a voltage divider on positive voltage; By connecting to ground when the switch is actuated, the positive input signals are generated. Both the positive bias and the Schmitt trigger levels serve to increase the interference immunity.

The RC element connected from the outside to the solder connections 228, 229 in the frequency-determining circuit is connected to the generator 21o from the potentiometer 226 and the capacitor 227; The frequency of the generator 21o and thus the time period preset on the divider chain at the outputs 2o2, 2o3 is finely adjusted with the potentiometer 226 between the decadal stages. The solder connections 228, 229 are also biased positively by voltage dividers 230, 231. A voltage regulator stage 234 is connected via the solder connections 232, 233 to the current source for the voltage supply of the circuit arrangement outside and inside the semiconductor module.

Via the solder connection 234, by means of the Schmitt trigger stage 235 and the negation elements 236, 237, reset signals can be introduced into the circuit arrangement at still free connections of logic elements; with the connection of the solder connection 238 from the outside by the capacitor 239, each flip-flop is automatically reset when the operating voltage is applied by the MONO-FLOP stage 24o. Both connections are in turn set to positive voltage by voltage dividers 241, 242, so that the required interference immunity is ensured. The on the lines Reset signals occurring at 236a, 237a and 24oa are optionally applied to lines 24oa and 236a in the input of OR ₂ element 8 (FIG. 2) or lines 237a and 24oa in the input of OR ₃ element.

The outputs 2o8 (41 in Fig. 2) and 209 (55 in Fig. 2) are each connected via a power amplifier stage 243, 244 and 245 to the external solder connections 246, 247 and 248, each of which is connected by a rectifier positive bias (e.g. 249) is made interference-proof. Between the output 2o9 and the power amplifier stage 244 there is a negation element 25 ₀ , which has been mentioned several times in connection with FIG. This circuit branch is the one that is used for the relay control in the cases of timing behavior functions described above.

Claims (6)

1. Electronic circuit arrangement for a relay with time behavior which can be determined by actuating a switch,
containing a clock generator, a divider chain, astable and / or monostable and / or bistable flip-flops, logic gates and an output circuit for controlling the relay,
characterized in that the output of at least one stage of the divider chain (220) controlled by the clock generator (21o in FIG. 5) - preferably via a divider pre-stage (211) - is a bistable flip-flop stage (1 in FIG .2 or lo4 in FIG. 3), the output signal of which, together with an input signal supplied by the switch (lines 11, 12 or 13), is connected via logic logic elements, optionally with the interposition of OR - ("OR") - (11 ₀ ), Negations - ("N") - (39, 44), WEDER-NOCH - ("NOR") - (19) elements at the input of the output circuit (208, 209), the input signal - optionally together with a reset ("RESET") signal (236a, 24oa) via an OR (8, 9) and / or an upstream WEDER-NOCH ("NOR") element (lo) and / or an upstream link chain comprising a monostable multivibrator (15) (MONO-FLOP), negation (17), NOW-NOCH limbs (19) and a bistable multivibrator (FLIP-FLOP) (23) at the reset input (5) the divider chain (7). 2. Electronic circuit arrangement according to claim 1, characterized in that between the outputs of several stages of the divider chain (7 in Fig.2, 212 in Fig.5) and the inputs of the loaded flip-flop (s) (1 and 37) a corresponding to Number of connected divider stage outputs (A, A ', ... D', D) two-dimensionally controllable selection matrix (2 in Fig. 2, 22o in Fig. 5) coded by direct voltage signals ("x", "y") lies. 3. Electronic circuit arrangement according to one of claims 1 and 2,
characterized in that in addition to the one output ("Z") of the divider stages (7) - optionally via a selection matrix (2) - a further output (Z ') with half the division ratio via a link chain at the input (35 ) a further bistable multivibrator (37) is connected, the output signal (38) together with an input signal ("1") via an OR gate (4o) at the input (41) of an output circuit (208, 243, 244 in Fig.5 ) is present. 4. Electronic circuit arrangement according to one of claims 1 to 3,
characterized in that the divider chain (212) is constructed as a multiple decade divider from alternating "2" divider and "5" divider stages (FIG. 5). 5. Electronic circuit arrangement according to one of claims 1 to 4,
characterized in that the clock generator (210) contains an adjustable RC element (potentiometer 226, capacitor 227) in the frequency-determining circuit. 6. Electronic circuit arrangement according to one of claims 1 to 5,
characterized in that at least the divider chain (212) - optionally with its associated selection matrix (220) - and / or the FLIP-FLOP function chain (lo4, lo8, 116, 119) with their condition elements are integrated on a semiconductor module and the coding inputs ("x", "y") of the divider chain selection matrix (220) or control inputs (2 ₀ 5, 2o6, 207) of the condition elements, and optionally connections of the clock generator (210) for the external RC Element (226, 227) or the clock inputs (213, 214, 215), reset inputs (236a, 237a, 24oa), the output circuits (243, 244, 245) and the power supply lines to external solder connections (216, 217 or 223 to 225, or 234, 238 or 228, 229 or 246 to 248 or 232, 233) of the semiconductor component in the for this characteristic technology (201 in Fig.5).

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