EP0006988B1 - Anordnung zur Taktsignalrückgewinnung bei der digitalen Signalübertragung - Google Patents

Anordnung zur Taktsignalrückgewinnung bei der digitalen Signalübertragung Download PDF

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Publication number
EP0006988B1
EP0006988B1 EP79101609A EP79101609A EP0006988B1 EP 0006988 B1 EP0006988 B1 EP 0006988B1 EP 79101609 A EP79101609 A EP 79101609A EP 79101609 A EP79101609 A EP 79101609A EP 0006988 B1 EP0006988 B1 EP 0006988B1
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EP
European Patent Office
Prior art keywords
signal
voltage
input
frequency
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP79101609A
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German (de)
English (en)
French (fr)
Other versions
EP0006988A1 (de
Inventor
Otmar Dipl.-Ing. Ringelhaan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT79101609T priority Critical patent/ATE1081T1/de
Publication of EP0006988A1 publication Critical patent/EP0006988A1/de
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the invention relates to an arrangement for clock recovery in digital signal transmission with a phase discriminator which contains a control input for the input signal and whose signal output is connected via a first loop filter to the control input of the first voltage-controlled oscillator.
  • phase-locked loops are known in which the output of a phase discriminator is connected to the control input of a voltage-controlled oscillator via a so-called loop filter. Such an arrangement is shown in FIG. 1.
  • the phase discriminator used can be an exclusive OR gate in the event that the two signals to be compared are continuously present.
  • the input signal is generally discontinuous, so that in this case the phase discriminator is implemented by a switch controlled by the input signal with regard to its wear times.
  • the loop filter consists of the combination of a low-pass filter and an integrator for generating the control voltage for the voltage-controlled oscillator.
  • the locally generated clock signal is emitted from the voltage-controlled oscillator both to the comparator input and to the clock signal output.
  • Such a phase locked loop can be understood as a bandpass filter of certain quality for the clock signal.
  • the quality of this bandpass is directly dependent on the cut-off frequency of the low-pass filter in the loop filter.
  • a very low cut-off frequency of the loop filter and thus a high quality of the bandpass permits only slow fluctuations in the control signal of the voltage-controlled oscillator and thus only slow fluctuations in the locally generated clock signal.
  • the desired high quality is at the expense of the capture range in which the phase-locked loop can adjust to the clock frequency of the digital signals.
  • the object of the invention is therefore to develop an arrangement of the type mentioned in the introduction, in which short synchronization times are achieved with as little effort as possible and, in addition to a large capture range, a high quality of the correspondingly constructed phase-locked loop is ensured.
  • the object is achieved in that, in the case of digital signals in the RZ format, the output of the first voltage-controlled oscillator is connected both to the signal input of the phase discriminator and to the signal input of a frequency-phase comparator in that the signal output of this frequency-phase comparator is connected via a second loop filter to the control input of a second voltage-controlled oscillator and that the output of the second voltage-controlled oscillator is connected both to the clock input of the frequency-phase comparator and to the output terminal of the arrangement.
  • a preferred development of the arrangement according to the invention results from the fact that at least one of the voltage-controlled oscillators is an astable multivibrator.
  • Another preferred embodiment of the invention results from the fact that the first loop filter has a comparatively high cutoff frequency and the second loop filter has a comparatively low cutoff frequency.
  • a variant of the arrangement according to the invention is expedient in which a differentiator with a downstream rectifier is connected upstream of the phase discriminator for processing digital signals in the NRZ format.
  • phase-locked loop which consists of the series connection of a phase locked loop and a frequency. and phase locked loop exists.
  • the phase-locked loop largely corresponds to that according to the prior art, ie it has a phase comparator PD on the input side, to the signal output of which the control input RE1 of a first voltage-controlled oscillator VC01 is connected via a first low-pass filter LF, 1.
  • a known controllable astable multivibrator was provided as the voltage-controlled oscillator.
  • the output signals of the first oscillator VC01 are supplied both to the signal input SE of the phase discriminator PD and to the signal input Si of a frequency-phase comparator, which outputs an output signal to the control input RE2 of a second voltage-controlled oscillator via a second loop filter LF2.
  • the second voltage-controlled oscillator VC2 is also designed as an astable multivibrator and outputs the local clock signal generated by it both to the output terminal A and to the comparator input VI of the frequency-phase comparator.
  • the pulse diagram according to FIG. 3 is used to explain the mode of operation of the phase locked loop according to FIG. 2.
  • 1 is that of the first voltage-controlled.
  • Oscillator VC01 designated clock signal. 2 denotes a discontinuously occurring input signal, the pulses of which occur in the normal position. A phase shift between the clock pulses and the input signal pulses of 90 ° is referred to as the standard position.
  • the switch in the phase comparator PD is closed for the duration of the input signal pulses according to line 2, so that the pulse sequence shown in line 3 results as the output signal of this phase comparator. It can be seen that the DC mean value of the pulse sequence shown in line 3 is 0, that is. the first voltage-controlled oscillator VC01 is not detuned.
  • Line 4 shows the input signal again, but here outside the normiage, in a phase shift of only 45 ° between the signal pulses and the clock pulses>.
  • the output signal of the phase discriminator during its closing period results in the signal shown in line 5 with pulses, the positive part of which clearly predominates.
  • the DC mean value of these pulses results in a positive value, which acts as a manipulated variable at the first voltage-controlled oscillator VC01 and leads to a phase shift of the locally generated clock signal in the desired sense.
  • Line 6 again shows the input signal outside the normal position, the individual pulses are shifted by 135 ° with respect to the clock pulses. This results in the output signal of the phase comparator shown in line 7 with a clear predominance of the negative part, so that the integrator contained in the first loop filter LF1 generates a negative readjustment voltage for the first voltage-controlled oscillator VC01 and thereby effects a corresponding phase control.
  • the loop filter blocks the output signal of the phase discriminator arranged in the frequency-phase comparator during the occurrence of the strongly jittered input signal.
  • This output signal is the difference between the clock signal generated in the second voltage-controlled oscillator VC02 and the input signal.
  • the frequency discriminator is effective, which only outputs a fluctuating DC voltage to the second loop filter LF2, which, after appropriate integration, is fed to the second control input RE2 of the second voltage-controlled oscillator VC02 and effects a corresponding readjustment of this oscillator.
  • the output signal of the frequency discriminator has also become zero.
  • the phase discriminator takes effect and effects a further readjustment of the second voltage-controlled oscillator VC02, but now only with regard to its phase.
  • a locally generated clock signal can be taken from the output terminal A and is synchronous with the clock of the input signal frequency and phase.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Dc Digital Transmission (AREA)
  • Forging (AREA)
  • Investigation Of Foundation Soil And Reinforcement Of Foundation Soil By Compacting Or Drainage (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
EP79101609A 1978-05-29 1979-05-25 Anordnung zur Taktsignalrückgewinnung bei der digitalen Signalübertragung Expired EP0006988B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT79101609T ATE1081T1 (de) 1978-05-29 1979-05-25 Anordnung zur taktsignalrueckgewinnung bei der digitalen signaluebertragung.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2823343 1978-05-29
DE2823343A DE2823343B1 (de) 1978-05-29 1978-05-29 Verfahren und Anordnung zur Taktsignalrueckgewinnung bei digitaler Signaluebertragung

Publications (2)

Publication Number Publication Date
EP0006988A1 EP0006988A1 (de) 1980-01-23
EP0006988B1 true EP0006988B1 (de) 1982-05-19

Family

ID=6040426

Family Applications (1)

Application Number Title Priority Date Filing Date
EP79101609A Expired EP0006988B1 (de) 1978-05-29 1979-05-25 Anordnung zur Taktsignalrückgewinnung bei der digitalen Signalübertragung

Country Status (7)

Country Link
EP (1) EP0006988B1 (enrdf_load_stackoverflow)
JP (1) JPS54161812A (enrdf_load_stackoverflow)
AT (1) ATE1081T1 (enrdf_load_stackoverflow)
AU (1) AU526026B2 (enrdf_load_stackoverflow)
BR (1) BR7903319A (enrdf_load_stackoverflow)
DE (2) DE2823343B1 (enrdf_load_stackoverflow)
DK (1) DK219379A (enrdf_load_stackoverflow)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4356518A (en) * 1980-02-01 1982-10-26 Ampex Corporation High frequency digital PCM decoding apparatus
JPS5933950A (ja) * 1982-08-18 1984-02-24 Matsushita Electric Ind Co Ltd クロツク抽出回路
GB2138227B (en) * 1983-04-12 1987-02-04 Sony Corp Digital video tape recorder apparatus
JPS60206339A (ja) * 1984-03-30 1985-10-17 Victor Co Of Japan Ltd デジタル信号復調装置のビツトクロツク信号発生装置
AU584882B2 (en) * 1984-04-19 1989-06-08 Donson Industries Pty. Ltd. Non-return disc-valve
FR2597689B1 (fr) * 1986-04-22 1988-06-10 Trt Telecom Radio Electr Dispositif pour la recuperation de rythme convenant notamment pour un systeme de transmission d'informations utilisant dans un sens de transmission le principe dit d'a.m.r.t.
US4825448A (en) * 1986-08-07 1989-04-25 International Mobile Machines Corporation Subscriber unit for wireless digital telephone system
JPS63120538A (ja) * 1986-11-08 1988-05-24 Nec Corp タイミング再生回路
AR242878A1 (es) * 1986-11-27 1993-05-31 Siemens Ag Disposicion de circuito para derivar una senal de reloj auxiliar de datos a partir de la frecuencia y/o de la fase de reloj de una senal digital sincronica o plesiocronica.
KR102662413B1 (ko) * 2017-12-29 2024-04-30 엘지디스플레이 주식회사 표시 패널용 전극 접속 구조

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2324853C3 (de) * 1973-05-17 1981-09-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Schaltungsanordnung zur Rückgewinnung des Bittaktes aus einem empfangenen binären Nachrichtensignal
NL7513610A (nl) * 1975-11-21 1977-05-24 Philips Nv Ontvanger voor synchrone signalen met dubbele fasevergrendelde lus.
US4017803A (en) * 1976-01-29 1977-04-12 Sperry Rand Corporation Data recovery system resistant to frequency deviations
DE2621403A1 (de) * 1976-05-14 1977-12-01 Licentia Gmbh Verfahren und schaltungsanordnung zur herleitung eines quasi-synchronen bittaktes aus einem binaeren nachrichtensignal

Also Published As

Publication number Publication date
BR7903319A (pt) 1979-12-11
DE2823343B1 (de) 1979-08-16
JPS6144422B2 (enrdf_load_stackoverflow) 1986-10-02
JPS54161812A (en) 1979-12-21
AU526026B2 (en) 1982-12-16
AU4749279A (en) 1979-12-06
EP0006988A1 (de) 1980-01-23
DE2962880D1 (en) 1982-07-08
ATE1081T1 (de) 1982-06-15
DK219379A (da) 1979-11-30

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